Re: gEDA-user: vpiHandles for the regs and nets

[EMAIL PROTECTED] said: > I have been having trouble with getting vpiHandles for the regs and > nets under my top level module. I have enclosed the code anyone knwo > what I am doing wrong??? vpi_interate(vpiNet...) and vpiReg are relatively recently added. As of 0.6 only the vpiInternalScope wo

Re: gEDA-user: conditional assign gets compile error

I double-checked the -1995 standard. This: 64'dz is not valid. Decimal values can only have numeric digits. It looks like VCS is in error for accepting it, and Icarus Verilog is in error for emitting a useless error message;-) -- Steve Williams"The woods are lovely, dark and

Re: gEDA-user: conditional assign gets compile error

[EMAIL PROTECTED] said: > Actually, according to the 2001 standard, 64'dz is valid... I really need to but that printed copy of the new standard. Thanks. -- Steve Williams"The woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, steve at p

Re: gEDA-user: geda-user: Icarus Verilog on MacOS X Problem

[EMAIL PROTECTED] said: > Is there any support for dynamic DLL in MacOS X or a possibility to > make Icarus Verilog without dynamic DLLs? Read the file "macosx.txt" included in the root of the source tree. This answers your exact question. -- Steve Williams"The woods are love

Re: gEDA-user: Icarus Verilog on MacOS X Problem

[EMAIL PROTECTED] said: > I think it's a OSX problem with differs btw linux and MacOS X > directory structures. Any hints are usefull, I'm a design engineer, > not a software guru. Well, it seems that the dlcompat library was not installed, or was not installed where the compiler/autoconf can

Re: gEDA-user: Icarus Verilog on MacOS X Problem

[EMAIL PROTECTED] said: > I did find a /usr/include/sys/malloc.h (at least on my version of OS > X), but it looks like kernel code. Can we switch to using stdlib.h > for the malloc() prototype? Already done. Someone sent me a patch. -- Steve Williams"The woods are lovely, dark

Re: gEDA-user: Icarus Verilog on MacOS X Problem

[EMAIL PROTECTED] said: > Anyway, the summary of the patch is: stdlib.h instead of malloc.h, and > unistd.h for the optarg/optind prototypes. The general pattern for what I try to do is include , and also include if it exists. configure figures out the latter. I just missed a few places, that

Re: gEDA-user: Assertion Error from vvp

[EMAIL PROTECTED] said: > vvp: symbols.cc:93: void split_node_ (tree_node_ *): Assertion `! cur-> > parent->leaf_flag' failed. The symbol table that vvp created somehow got trashed. Your plidrv module trashing memory maybe? -- Steve Williams"The woods are lovely, dark and deep.

Re: gEDA-user: Assertion Error from vvp

[EMAIL PROTECTED] said: > It is a quite large executeable (96..2 meg) could that have anything > to do with it?? The 0.6 release had a bug under Windows that the 0.6.1 release fixed. If you are using a Windows binary, make sure you have the 0.6.1 release, and not the 0.6 release. (I've removed t

gEDA-user: Binaries for GTKWave

I've updated the GTKWave binaries that I keep on my FTP site to The latest Tony release 1.3.19. I have a src rpm, binary rpms for alpha and Intel (RedHat 7.1 and compatible) and a Windows installer for the Windows binary. I also have the original source tarball here.

gEDA-user: SMI Page

Does anybody know where the SMI (Software Model Interface) PLI module has gotten to? The link I have on the Icarus Verilog plug-ins page is dead. -- Steve Williams"The woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, steve at picturel.co

Re: gEDA-user: Save/Restart Features in Verilog 2001?

[EMAIL PROTECTED] said: > I was wondering if Icarus Verilog supports the new Verilog 2001 $save > and $restart checkpointing features. If not, is there a method that > people use to get a similar capability? It does not, and for the record I do not believe checkpointing is a 2001 feature. It is

Re: gEDA-user: Save/Restart Features in Verilog 2001?

[EMAIL PROTECTED] said: > However, I see that annex is prefaced with "The system tasks and > functions described in this annex are for informative purposes only > and are not part of the IEEE standard Verilog HDL." Ah, I missed that whole section:-) Still, $save/$incsave/$restart are pretty unl

Re: gEDA-user: Using iVerilog with fileio

[EMAIL PROTECTED] said: > You might want to change your LDFLAGS to be '-G'. Depending on which > linker you're using, -shared may not be accepted... Whatever worked to compile/link system.vpi should also work with making the fileio.vpi mdoule. [EMAIL PROTECTED] said: > Regardless, looks like y

Re: gEDA-user: Iverilog support SWIFT models??

[EMAIL PROTECTED] said: > Does the Iverilog compiler support SWIFT models?? Anyone have any > experience with this?? No, because I have no idea what SWIFT is. Support for VirtexIIPro also begs this question because of the swift models for the processor. I've been watching out for information o

Re: gEDA-user: Iverilog support SWIFT models??

(Moving this conversation to geda-dev..) [EMAIL PROTECTED] said: > The PLI interface seems to be implemented in the module lmtv.o, that > is shipped in the smartmodel lib directory. An `nm lmtv.o' reveals > the following undefined symbols: Most of those acc_ and tf_ functions are indeed suppo

Re: gEDA-user: Fileio in iVerilog

[EMAIL PROTECTED] said: > Terry Barnaby posted an email http://archives.seul.org/geda/dev/ > Mar-2001/msg00125.html saying that he had added fopenr, fopenw, > fgetc, fputc, fread and fwrite1 into his system.vpi. $fopen, $fputc, fgetc and a few other Verilog-2001 fileio tasks are in the system.vp

Re: gEDA-user: iverilog FPGA examples

[EMAIL PROTECTED] said: > While poking around the verilog/examples directory, I noticed that > initial values for registers don't seem to be handled anymore. That is true, although I'm looking into recovering that functionality in the new synthesizer. [EMAIL PROTECTED] said: > Also, it doesn'

Re: gEDA-user: iverilog FPGA examples

[EMAIL PROTECTED] said: > I am very interested in using iverilog to generate configurations for > parts such as a Triscend e5, which claims to be much like Xilinx in > its arrangement, but they do not publish their configuration language. If their implementation tools accept EDIF, then all you n

Re: gEDA-user: iverilog: Creating a .vpi file on Windows

[EMAIL PROTECTED] said: > I'm trying to get VPI working with Icarus Verilog on Windows 2K. I > don't think that iverilog-vpi is available for Windows yet. I would be delighted if some Windows geek (er... genius:-) were to write an iverilog-vpi.bat file that does what the iverilog-vpi script do

gEDA-user: RPMS for GTKWave-1.3.20

I've made RPM packages of GTKWave 1.3.20. The 1.3.20 fixes a time scale bug that was reported against Icarus Verilog. Turned out to be a gtkwave problem, so Tony fixed it (to make 1.3.20) and I'm mirroring the source and distributing packages: That directory

gEDA-user: Re: gEDA: RPMS for GTKWave-1.3.20

[EMAIL PROTECTED] said: > The new Windows binary (sans installer) can be found there. I keep > VC++ and the project stuff for gtkwave on my old machine just for > those builds since they are a big, big PITA. GTKWave can be compiled w/ the mingw port of gcc, and makefiles. That's how I do it, whe

gEDA-user: Icarus Verilog snapshot 20021117, prerelease for v0.7

This is hopefully the last snapshot before the upcoming 0.7 release, so not much has changed. Some simple bugs were fixed, and some packaging updates were made. I encourage people to test installers as well as the product itself. I'd also be interested in collecting precompiled packages from othe

gEDA-user: Icarus Verilog snapshot 20021207, prerelease for v0.7

The last prerelease for Icarus Verilog v0.7 led to a flurry of bug reports, so I have made another prerelease. A fair number of bugs were fixed in this. As with the last prerelease, I encourage people to test the installers as well as the packages. This is also the last chance for port managers t

gEDA-user: Icarus Verilog RELEASE 0.7

I've made the base release files for 0.7. It's done. I'm too tired to write release notes, so I'll do it later. (I need a secratary.) I've done the Windows build and installer, and the Linux RPMS for i386 and alpha. I'm now ready to start collecting binaries for all the other targets, so porting

Re: gEDA-user: Icarus Verilog RELEASE 0.7

Gack! Cut-and-paste error! Change these to: RPMS for RedHat 7.X (Should work on Mandrake as we

Re: gEDA-user: Icarus Verilog RELEASE 0.7

[EMAIL PROTECTED] said: > Here you go. The contents go in /usr/local. It includes the > libdl.dylib that I linked against. My feeling is that if someone > already has dlcompat installed, they probably will compile from > source. I've transferred it to here:

Re: gEDA-user: Icarus Verilog: selecting parts of an array

integer i; for (i = 0; i < 64; i = i + 8) begin @posedge(clk) data = test[i:(i+8)]; end Don't you mean @(posedge clk)? -- Steve Williams"The woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, steve at picturel.com and lines

Re: gEDA-user: icarus verilog testsuite for iverilog_vpi

[EMAIL PROTECTED] said: > I am new to icarus verilog system. Before I jump into using them, I > like to make sure all setup is correct, so I download ivtest from > sourceforge.org to see all things in good shape. We need way more information. What system are you using? Which version of Icarus Ve

Re: gEDA-user: icarus verilog testsuite for iverilog_vpi

[EMAIL PROTECTED] said: > I am using Linux (Redhat 8.0) and icarus verilog is v0.7. I am using > gcc compiler v3.2. Please let me know if there is anything else I > should reply. OK, this suggests that you are using the precompiled rpm. This is fine. It appears that the problem is with the compil

Re: gEDA-user: Icarus Verilog: selecting parts of an array

>integer i; >for (i = 0; i < 64; i = i + 8) begin >@posedge(clk); >data = test[i:(i+8)]; >end [EMAIL PROTECTED] said: > Is the above a valid Verilog code snippet (ignoring the erroneous > posedge statement) ??? No, non-constant part selects are not allowed in Verilog-1995. In Verilog 20

Re: gEDA-user: icarus verilog testsuite for iverilog_vpi

[EMAIL PROTECTED] said: > Actually I was more interested in using vpi modules, I will try to > compile it from source. There is a hello_vpi example is /usr/share/doc/verilog-0.7 as well. If this works, then the linking problems are a matter for the gcc 3.2 runtime, and you should have no problem

Re: gEDA-user: icarus verilog testsuite for iverilog_vpi

[EMAIL PROTECTED] said: > I like to use tf_exprinfo routine in my c++ routine. I didn't see this > routine in veriuser.h, if I declare extern tf_exprinfo routine in this > file, would it work? No, because tf_exprinfo is not implemented. Icarus Veriog officially supports the PLI 2.0 (the vpi_* rou

Re: gEDA-user: icarus verilog

[EMAIL PROTECTED] said: > I just have read an article at linuxjournal.com about icarus verilog. > It mentioned that icarus verilog can handle from small to medium size > of design. Can you tell me the approximate range of limit? There is no limit per se., other then the capacities of your compu

gEDA-user: RPMS for gtkwave-1.3.22-1

I've made RedHat RPMS for gtkwave-1.3.22p1, and placed them here: ftp://icarus.com/pub/eda/gtkwave/RPMS/gtkwave-1.3.22p1-0.src.rpm ftp://icarus.com/pub/eda/gtkwave/RPMS/gtkwave-1.3.22p1-0.alpha.rpm I've only build the alpha rpm, because the point of this was to get an alpha binary that does

Re: gEDA-user: Verilog 2001

[EMAIL PROTECTED] said: > What is the state of, and planeed future for Verilog 2001 constructs > in Icarus? I'm specifically interested in bit selects in arrays, > arrays of instances, multi-dimensional arrays, and generate constructs. Some of Verilog-2001 is already supported, including signed

Re: gEDA-user: Verilog 2001

[EMAIL PROTECTED] said: > Why you run far away to SystemVerilog with your Integral types and > lay still down needed Verilog 2001 support in case of configuration / > generate? Integral types borrow the infrastructure of real types which are a -1995 feature that I was missing. I simply chose to

Re: gEDA-user: Verilog 2001

[integral types and language support] [EMAIL PROTECTED] said: > Your reasons laying in performance wasn't clear to me. My point was that there are cases in a Verilog simulation where 4-value logic (0,1,x,z) doesn't really need to be fully simulated and the simulation engine can use native integ

gEDA-user: gtkwave 1.3.23 packages

I've make RPMS of gtkwave-1.3.23 for i386 and alpha. The packages are available here: The 1.2.23 version adds visual display of dead zones (the area between $dumpoff and $dumpon) in a different color, so that it is visually obvious that the dump is not

Re: gEDA-user: putting it all together

[EMAIL PROTECTED] said: > I am studying the use of Icarus Verilog to create an RTL netlist. From > that netlist, which has INV, OR, NAND, etc defined, I am trying to > understand how to flow the netlist into Magic. The best way to get from Verilog to MAGIC is to write a code generator that genera

Re: gEDA-user: putting it all together

(This may be more like a subject for the geda-dev list.) [EMAIL PROTECTED] said: > I have a combination of chip logic design and layout experience that > should let me make headway in this kind of project. Would you please > tell us more about the steps involved in making a icarus verilog code

Re: gEDA-user: PDX open source conference

[EMAIL PROTECTED] said: > http://conferences.oreillynet.com/os2003/ That's flying distance for me, but the convention prices are kinda steep for a starving open-source developer:-( -- Steve Williams"The woods are lovely, dark and deep. steve at icarus.com But I have pro

gEDA-user: Random Icarus Verilog user question

Question: Does anybody out there use Icarus Verilog on Linux/Itanium? It seems that Model Tech. thinks they are the first to support 64bit Linux. They qualified it by saying "64-bit Linux-based Intel Itanium" and since not many people can afford Intel Itanium systems, Linux-based or otherwise, so

gEDA-user: Waveform Compare for LXT

I find myself in need of a waveform compare that works for very large LXT files. The simulation run I'm trying to compare is too long for VCD files to be practical (diff chokes) and I know there are differences I don't want. I need to find the time and signal for the first difference. -- Steve Will

gEDA-user: Icarus Verilog command files for OpenCores PCI core

I'm interested in getting the PCI core from opencores.org to simulate under Icarus Verilog. Does anyone have a command file that I can use to run a simulation? -- Steve Williams"The woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://ww

Re: gEDA-user: Icarus Verilog command files for OpenCores PCI core

Stephen Williams wrote: I'm interested in getting the PCI core from opencores.org to simulate under Icarus Verilog. Does anyone have a command file that I can use to run a simulation? OK, I got impatient. Here's a command file that does it: +incdir+$(PCI)/bench/verilog +incdir+$(PCI)/r

Re: gEDA-user: Icarus Verilog: FPGA-like automatic initialized registers?

Tommy Thorn wrote: Thanks to both Stephen and Alexander for the rapid response. On Sunday 10 August 2003 11:40, Stephen Williams wrote: ... or simulation specific initialization initial begin for (...) reg[$i] = 0; (I'm sloppy on the syntax here). In Icarus Verilog, and

Re: gEDA-user: Icarus Verilog: FPGA-like automatic initialized registers?

[EMAIL PROTECTED] wrote: I'm a Verilog, but I've tried researching this question in vain, so I turn to this forum. In standard Verilog, registers start out in the unknown (x) state, and initialization either requires explicit reset logic, eg. always @(posedge clk) if (~reset_n) begin

Re: gEDA-user: iVerilog -tfpga: if-else errors?

Mike Butts wrote: In iVerilog, synthesizing even a simple if-else results in errors: For example, this simple FF with clock enable and asynch reset from the Alternate Verilog FAQ: module dff_cke (data, clock, reset, cke, q); // port list input data, clock, reset, cke; output q;

Re: gEDA-user: iVerilog -tfpga: if-else errors?

Mike Butts wrote: Hi Stephen, thanks for the super quick reply. I filed the bug report a few days ago, when I posted to geda-user without realizing I had to join first (duh). I hope the fix is in your latest 20030810 snapshot. I'm *delighted* to see you've added -parch=lpm, that's precisely th

Re: gEDA-user: iVerilog -tfpga: if-else errors?

Stephen Williams wrote: Normally, I would try to get a bug report into the ivl-bugs database before really working on a problem like this, but I happen to be in the area anyhow, so I'll let it slide:-) You *did* file a bug report. My mailer confused me, but it is there and well formed.

Re: gEDA-user: iVerilog -tfpga: if-else errors?

Mike Butts wrote: In iVerilog, synthesizing even a simple if-else results in errors: For example, this simple FF with clock enable and asynch reset from the Alternate Verilog FAQ: module dff_cke (data, clock, reset, cke, q); // port list input data, clock, reset, cke; output q;

Re: gEDA-user: problems with icarus ..

Lars Segerlund wrote: I am trying to synthesice a simple adder, and I am getting errors like this. Does anybody know whats going wrong ? module addc(A, B, CIN, COUT, Q); input A, B, CIN; output COUT, Q; assign Q=A ^ B ^ CIN; assign COUT= (A & B) | (A & CIN) | (B & CIN); endmodu

Re: gEDA-user: problems with icarus ..

Lars Segerlund wrote: Thanks, The same works for me, now I probably have to look at the source a bit :-( I was trying to use the lpm target, but I don't know if this is the correct way ? You're doing it the right way. The generic LPM target is new, and therefore needs some fleshing out

Re: gEDA-user: GTKWave status?

Matt Ettus wrote: I'm confused about gtkwave. Could some one answer the following -- Is gtkwave still being actively developed? Yes. Which is the latest version? The latest in the 1.3 branch is 1.3.31, which adds LXT2 support. Are both the 1.3 and 2.0 branches moving forward? What is the lates

Re: gEDA-user: system task calling with iverilog

[EMAIL PROTECTED] wrote: Hi, What are the system tasks that iverilog support? I like to use $fscanf, $dumpvar, $readmemh, $ungetc and etc for my code. I didn't have a problem compileing with iverilog for these codes, but when I tried to run this with vvp, I am getting all errors for these tasks. I

Re: gEDA-user: VHDL Compiler

Bill Cox wrote: I gree. In general both Verilog and VHDL are nearly equivalent from the end-user perspective. However, from a developer standpoint, Verilog is far superior. VHDL has all kinds of crazy nonsense that almost no one ever uses. Also, the VHDL LRM (language reference manual) is a

Re: gEDA-user: Icarus snapshot 20040606 on Solaris

-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 Joshua Boyd wrote: | I'm trying to compile Icarus 20040606 on Solaris 9. It fails with: | mv functor.d dep/functor.d | flex -PVL -s -olexor.cc ./lexor.lex | "./lexor.lex", line 348: warning, -s option given but default rule can | be matched | bison --v

gEDA-user: Re: EDA-user: Icarus snapshot 20040606 on Solaris

-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 Joshua Boyd wrote: | Now Icarus 20040606 will install on both solaris and Irix (I have 0.7 | running fine on irix, but I wanted to upgrade), but trying to run the | resulting a.out file gives this: | system: Unable to find a `system.vpi' module on the s

Re: gEDA-user: Icarus snapshot 20040606 on Solaris

-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 Dave McGuire wrote: | On Jul 30, 2004, at 12:31 PM, Stephen Williams wrote: |> bison has been a consistent source of irritation/entertainment |> as every few months they seem to change the argument meanings. |> I'm tempted to just include

Re: gEDA-user: icarus verilog, svector question

-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 Joshua Boyd wrote: | In svector.h, there is a specialization: | inline svector::svector(unsigned size) | | How mad is the speed hit from leaving this out? | | The reason I ask is because doing specialization in this manner is | non-standard. I believe

Re: gEDA-user: Icarus Verilog building from CVS

-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 Joshua Boyd wrote: | Autoconf in vvp... | configure.in:13: warning: AC_CANONICAL_HOST invoked multiple times | autoconf/specific.m4:393: AC_MINGW32 is expanded from... | ../aclocal.m4:86: AX_WIN32 is expanded from... | configure.in:13: the top level | |

Re: gEDA-user: icarus verilog: IVL_LPM_CMP_EQ not supported by this target

-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 Ming Deng wrote: | I ran the sample file on Icarus Verilog 0.7, got the same result. | | After taking a briefly look into the code, I found there were no any | comparators implemented for fpga-lpm. See the following snippet from | tgt-fpga/d-lpm.c The

Re: gEDA-user: icarus verilog: IVL_LPM_CMP_EQ not supported by this target

be compiled into LPM_COMPARE and LPM_CONSTANT devices. But |>unfortunately most LPM_COMPARE devices have not been implemented yet. |> |>Ming Deng |> |> |> |> |>Stephen Williams wrote: |> |>> -BEGIN PGP SIGNED MESSAGE- |>> Hash: SHA1 |>> |>>

gEDA-user: Icarus Verilog Release 0.8

-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 Some of you have already noticed that Icarus Verilog 0.8 has appeared on the FTP site. Start from the Icarus Verilog home page: and follow the link to the 0.8 software, and from there you will get release notes and li

gEDA-user: Icarus Verilog Snapshot 20041004

-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 Hi all, This snapshot is actually a *Release Candidate* for the 0.8 release. I've cleaned up the easy and stupid bugs (I think) and I've done some cleanup. This snapshot is available as source and precompiled forms For a variety of targets. The initial

Re: gEDA-user: Icarus Verilog Release 0.8

-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 Stephen Williams wrote: | | Some of you have already noticed that Icarus Verilog 0.8 has | appeared on the FTP site. Start from the Icarus Verilog home | page: <http://www.icarus.com/eda/verilog> and follow the link | to the 0.8 software, an

Re: gEDA-user: Unexplained Icarus warning

David Howland wrote: The test code that produces this is as follows: -8< module test (D, clk, en, Q); input D, clk, en; output Q; reg Q; always @(clk)// this is line 8 begin if(en==1) begin Q = D; end end endmo

Re: gEDA-user: Unexplained Icarus warning

David Howland wrote: Stephen Williams wrote: It's valid verilog, but kind-of a weird device you are modeling there. Are you really trying to make a D-type flip-flop that loads on both edges of the clock input? The Icarus Verilog synth- esizer doesn't quite know what to make of it, so it

Re: gEDA-user: Bug fixed?

-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 David Howland wrote: | I see from the mailing lists that there is a known bug, in icarus | verilog, that gives the following error: | | error: Asynchronous if statement is missing the else clause. You're doing synthesis? It's not necesarily a bug, take

Re: gEDA-user: Bug fixed?

-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 David Howland wrote: | Stephen Williams wrote: | |> You're doing synthesis? It's not necesarily a bug, take a look |> at the line that it is reporting and see if the error actually |> makes sense. This error will only happen if y

Re: gEDA-user: Bug fixed?

-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 David Howland wrote: |> In this case, you'd get better results if you specified a more |> specific arch=, rather then let it make the generic LPM devices. |> The problem here is that there are just some code generator functions |> missing for the archit

Re: gEDA-user: Bug fixed?

-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 David Howland wrote: | I'm sorry about all the mail to the list, I've just 'discovered' the | gEDA tools (more specifically iverilog). | | After changing my code to run through the icarus synthesis flow, I | finally end up with these: | | fpga.tgt: IVL_

Re: gEDA-user: Arrays in Icarus

David Howland wrote: Is this kind of notation supported? It seems Icarus is having trouble with it: wire [31:0] intconnect [2:0]; meaning an array of four 32-bit wires, named 'intconnect'. Not currently supported. Sorry. -- Steve Williams"The woods are lovely, dark and deep. st

Re: gEDA-user: gEDA Suite CD .isos available

-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 John Doty wrote: |>Then, burn it to a CD and use the CD to |>install the entire gEDA Suite on any (Linux) computer you wish. | | | Well, not just any Linux computer. Only Intel architectures. Yes, I know | (but old Mac hardware is so solid under Linux,

Re: gEDA-user: iverilog question ?

using OS version : Red Hat Enterprise Linux WS release 3 (Taroon) Kernel 2.4.21-4.0.1.ELsmp on an i686 iverilog version : Icarus Verilog version 0.7 ($Name: s20040915 $) Copyright 1998-2003 Stephen Williams Our code compiles fine until it hits real variables, values and expressions. many of our librar

Re: gEDA-user: Register enables in Icarus

David Howland wrote: Say I want to make a clocked, enabled register. This would simply be the following in behavioral verilog: always @(posedge clk) begin if (en) begin Q <= D; end end That works for me. It simulates fine, and it synthesizes too. I think there is something

Re: gEDA-user: PCB suggestion

-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 Marvin Dickens wrote: | On Mon, 2005-01-10 at 23:09 -0500, Dan McMahill wrote: | | |>I'm not a QT fan. Despite the claims I've heard to its cross-platform |>nature, I've had fairly bad luck with having it run correctly on |>non-intel-architecture syste

Re: gEDA-user: PAL/CPLD programming

William Dieter wrote: I am looking for software to generate JEDEC files that can be programmed into 22v10 PAL's and some of the older MACH isp parts. Is there anything open source that is available that will run under Linux? I found Icarus PAL, but it only seems to read JEDEC files, not write them

Re: gEDA-user: PAL/CPLD programming

William Dieter wrote: On Tue, 11 Jan 2005 16:02:48 -0800, Stephen Williams <[EMAIL PROTECTED]> wrote: Icarus PAL should include a pal.tgt plug-in for Icarus Verilog that adds a code generator to Icarus Verilog. This code generator can *write* JEDEC files. I don't suppose its the so

Re: gEDA-user: PCB suggestion

Magnus Danielson wrote: From: "Bert Douglas" <[EMAIL PROTECTED]> Subject: Re: gEDA-user: PCB suggestion Date: Wed, 12 Jan 2005 19:27:38 -0600 Message-ID: <[EMAIL PROTECTED]> From: "Dave McGuire" <[EMAIL PROTECTED]> Motif is, as well as Xaw, X11 Toolkit based, but as a comercial product lots of pe

Re: gEDA-user: More footprint stuff

-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 DJ Delorie wrote: |>Now you might think that anybody could just get a copy of RHEL and |>stick it on the web for free download, thus undercutting RedHat's |>ability to sell their CDs for more than $0.00. There is a catch, |>however. | | | This has been

Re: gEDA-user: How to obtain a generated C++ from Icarus?

-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 Konstantin Savenkov wrote: | I want to integrate hardware components, written in Verilog, to our simulation | modeling environment. It seems convinient to translate Verilog module in C++ | and use a proper wrapper, which provides the interface, required

gEDA-user: Icarus Verilog 0.8.1

-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 I've received various bug reports to the 0.8 release, and once again it's to the point where as often as not the answer is to get the source from CVS. Unfortunately, the CVS 0.8 branch is not always accessible to users, and more then new users should be

gEDA-user: Icarus Verilog 0.8.1 SPARC Binaries

-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 An anonymous contributer has graciously made packages of Icarus Verilog 0.8.1 for Solaris 8 SPARC. These packages are here for download. I have no means to test them, so success reports are welcome. -

gEDA-user: Icarus Verilog at Wescon

-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 I seem to have allowed myself to be talked into a presentation at Wescon 2005, which I'm now fleshing out. The title is to be: ~ "Icarus Verilog in Mixed Vendor Environments" and I would like to include in my presentation some case studies from users ot

Re: gEDA-user: Icarus Verilog 0.8.1 SPARC Binaries

-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 Joshua Boyd wrote: | On Mon, Feb 21, 2005 at 01:12:57PM -0800, Stephen Williams wrote: |>An anonymous contributer has graciously made packages of |>Icarus Verilog 0.8.1 for Solaris 8 SPARC. These packages are |>here for download. I have no

Re: gEDA-user: Compilation problem with icarus 0.8.1?

-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 The problem is "m - 1'b1". The variable "m" is an integer which has an indefinite width. (For example, it can have different widths on different compilers.) Replace that with "reg signed [31:0]" if you want to be explicit about its size. Yes, other comp

Re: gEDA-user: icarus 0.8 code gen doesn't like my design -- anyone seen this error?

-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 Mark Schellhorn wrote: | I'm trying to debug the following error message from iverilog when | compiling my design with icarus v0.8.1: | | CODE GENERATION -t dll | ... invoking target_design | ivl: vector.c:86: allocate_vector: Assertion `(base + idx) <

Re: gEDA-user: Compilation problem with icarus 0.8.1?

-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 Mark Schellhorn wrote: | Hi Stephen, | | Thanks for your response! | | I tried using a sized reg for m as well but I still get the error: Hmm, looks like d and e are also used in that manner. However, I see that someone pointed out that the constant pro

Re: gEDA-user: icarus 0.8 code gen doesn't like my design -- anyone seen this error?

tor.c:86: allocate_vector: Assertion `(base + idx) < (256*1024)' failed. |> |>If I reduce the size of the mem vector then it works. The bad news for me is |>that my problem code is inside a Xilinx block RAM library cell, so I can't just |>code around it without changin

Re: gEDA-user: Icarus misses unconnected nets?

-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 Tom Hawkins wrote: | Icarus is not reporting unconnected nets with -Wall. Am I missing | something? I always thought it did. | | 1 module test (x); | 2 output x; | 3 wire b; | 4 assign x = b; | 5 endmodule | | $ ive

Re: gEDA-user: Icarus misses unconnected nets?

-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 Tom Hawkins wrote: | Stephen Williams wrote: | |> Tom Hawkins wrote: |> | Icarus is not reporting unconnected nets with -Wall. Am I missing |> | something? I always thought it did. |> | |> | 1 module test (x); |> |

Re: gEDA-user: Icarus multiplier lpm

-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 Tom Hawkins wrote: | I hit a case with Icarus synthesis involving embedded | multiplication expressions inside concatenations. Outside | a concat, the multiplier is synthesized to the correct | precision. However, inside a concat, the multiplier | pre

Re: gEDA-user: Icarus multiplier lpm

-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 Tomasz Motylewski wrote: |>However, it turns out that the IEEE1364-1995 standard was overruled |>by the -2001 standard which changes the rule to the width of a |>multiply being figured the same way the widths of a sum are figured. |>The older behavior m

Re: gEDA-user: Icarus: Verilog implementation, System Verilog support

-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 Günter Dannoritzer wrote: | Hi, | | I have been using Icarus Verilog now for a few months and start to love | it. Now I got the task to start looking into using System Verilog and | saw that Icarus has a compiler switch for that. | | How much of System

Re: gEDA-user: iverilog EDIF VCC/GND references?

Harold D. Skank wrote: People, I'm trying to get an EDIF file generated by iverilog-fpga transferred to a Lattice package (ispLEVER, Version 4.2 - Linux). It appears that the Lattice package needs to know how iverilog handled the VCC and GND references in the design. Looking at the EDIF file, I w

Re: gEDA-user: cell0 and cell1 references in EDIF file?

Harold D. Skank wrote: People, I need some help here! I'm using iverilog to provide simulation capability, and to generate an EDIF design file to submit to a Lattice Semiconductor package for place and route. Everything seems to go OK up to the submission of the EDIF file, at which point the Latt

Re: gEDA-user: study the source codes of iverilog

-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 chen chen wrote: | Recently, I study the source file of iverilog. Is there someone also does | the same work? | The source code is very hard to understand because there have not the | explain documents of it. Dose someone can help me? Or where can I d

Re: gEDA-user: Icarus Verilog: Asynchronous if statement is missing the else clause

-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 CN wrote: | -- | module latch1 (clk, d, q); | input clk, d; | output q; | reg q; | | always @ (clk or d) begin |if (clk == 1'b1) begin | q = d; |end | end | | endmodule | -- | | With the command line | iverilog -tfpga -p

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