[gem5-dev] changeset in gem5: tests: Create base classes to encapsulate com...

changeset e428871da248 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=e428871da248 description: tests: Create base classes to encapsulate common test configurations Most of the test cases currently contain a large amount of duplicated boiler plate

[gem5-dev] changeset in gem5: tests: Always specify memory mode in every te...

changeset ffec48040ac1 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=ffec48040ac1 description: tests: Always specify memory mode in every test system. Previous to this change we didn't always set the memory mode which worked as long as we never

[gem5-dev] changeset in gem5: cpu: rename the misleading inSyscall to noSqu...

changeset 1c97b57d5169 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=1c97b57d5169 description: cpu: rename the misleading inSyscall to noSquashFromTC isSyscall was originally created because during handling of a syscall in SE mode the threadcontext

[gem5-dev] changeset in gem5: o3: Fix issue with LLSC ordering and speculation

changeset 55fa95053ee8 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=55fa95053ee8 description: o3: Fix issue with LLSC ordering and speculation This patch unlocks the cpu-local monitor when the CPU sees a snoop to a locked address. Previously we

[gem5-dev] changeset in gem5: arch: Make the ISA class inherit from SimObject

changeset 877293183bdf in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=877293183bdf description: arch: Make the ISA class inherit from SimObject The ISA class on stores the contents of ID registers on many architectures. In order to make reset values

[gem5-dev] changeset in gem5: arm: Make ID registers ISA parameters

changeset 25ebe5e13a07 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=25ebe5e13a07 description: arm: Make ID registers ISA parameters This patch makes the values of ID_ISARx, MIDR, and FPSID configurable as ISA parameter values. Additionally,

[gem5-dev] changeset in gem5: mem: Fix a bug in the memory serialization fi...

changeset b08ec9cf2e3f in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=b08ec9cf2e3f description: mem: Fix a bug in the memory serialization file naming This patch fixes a bug that caused multiple systems to overwrite each other physical memory. The

[gem5-dev] changeset in gem5: config: Replace second keyboard with a mouse.

changeset 175421e57fff in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=175421e57fff description: config: Replace second keyboard with a mouse. The platform has two KMI devices that are both setup to be keyboards. This patch changes the second

[gem5-dev] changeset in gem5: scons: Fix libelf linking errors when using c...

changeset b958d9fa867c in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=b958d9fa867c description: scons: Fix libelf linking errors when using clang/llvm This patch fixes a linking error that occurs when using clang/llvm in combination with older

[gem5-dev] changeset in gem5: ruby: Fix missing cxx_header in Switch

changeset 8f8c911ab5a7 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=8f8c911ab5a7 description: ruby: Fix missing cxx_header in Switch This patch addresses a warning related to the swig interface generation for the Switch class. The cxx_header is now

[gem5-dev] changeset in gem5: mem: Add sanity check to packet queue size

changeset 5490105626dc in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=5490105626dc description: mem: Add sanity check to packet queue size This patch adds a basic check to ensure that the packet queue does not grow absurdly large. The queue should

[gem5-dev] changeset in gem5: cpu: Fix the traffic gen read percentage

changeset 8f24dcb13b85 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=8f24dcb13b85 description: cpu: Fix the traffic gen read percentage This patch fixes the computation that determines whether to perform a read or a write such that the two corner

[gem5-dev] changeset in gem5: config: Reduce DRAM controller regression tra...

changeset bcb7441ae83c in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=bcb7441ae83c description: config: Reduce DRAM controller regression traffic rate This patch changes the traffic generator period such that it does not completely saturate the DRAM

[gem5-dev] changeset in gem5: stats: Update DRAM regression stats to match ...

changeset ebabcce1880f in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=ebabcce1880f description: stats: Update DRAM regression stats to match new config This patch updates the regression stats to reflect the change in the traffic gen configuration.

[gem5-dev] changeset in gem5: dev: Fix the Pl111 timings by separating pixe...

changeset e88cf95d33d3 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=e88cf95d33d3 description: dev: Fix the Pl111 timings by separating pixel and DMA clock This patch fixes the Pl111 timings by creating a separate clock for the pixel timings. The

[gem5-dev] changeset in gem5: arm: Fix DMA event handling bug in the PL111 ...

changeset bf428987f54e in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=bf428987f54e description: arm: Fix DMA event handling bug in the PL111 model The PL111 model currently maintains a list of pre-allocated DmaDoneEvents to prevent unnecessary heap

[gem5-dev] changeset in gem5: scons: Add support for google protobuf building

changeset 0c0ec9d87746 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=0c0ec9d87746 description: scons: Add support for google protobuf building This patch enables the use of protobuf input files in the build process, thus allowing .proto files to be

[gem5-dev] changeset in gem5: base: Add wrapped protobuf output streams

changeset 6e6b8d8ab258 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=6e6b8d8ab258 description: base: Add wrapped protobuf output streams This patch adds support for outputting protobuf messages through a ProtoOutputStream which hides the internal

[gem5-dev] changeset in gem5: mem: Add tracing support in the communication...

changeset 6a348f61220c in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=6a348f61220c description: mem: Add tracing support in the communication monitor This patch adds packet tracing to the communication monitor using a protobuf as the mechanism for

[gem5-dev] changeset in gem5: base: Add wrapped protobuf input stream

changeset f7582cce2459 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=f7582cce2459 description: base: Add wrapped protobuf input stream This patch adds support for inputting protobuf messages through a ProtoInputStream which hides the internal

[gem5-dev] changeset in gem5: cpu: Encapsulate traffic generator input in a...

changeset b4a3d0953757 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=b4a3d0953757 description: cpu: Encapsulate traffic generator input in a stream This patch encapsulates the traffic generator input in a stream class such that the parsing is not

[gem5-dev] changeset in gem5: tests: Add support for skipping tests, skip E...

changeset 9f0918fbb07f in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=9f0918fbb07f description: tests: Add support for skipping tests, skip EIO tests if not enabled The EIO tests depend on the EIO support from the encumbered repository, which means

[gem5-dev] changeset in gem5: cpu: Share the send functionality between tra...

changeset af9066bc088c in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=af9066bc088c description: cpu: Share the send functionality between traffic generators This patch moves the packet creating and sending to a member function in the shared base

[gem5-dev] changeset in gem5: config: Traverse lists when visiting children...

changeset f329e7ec9786 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=f329e7ec9786 description: config: Traverse lists when visiting children in all proxy This patch makes the all proxy traverse any potential list that is encountered in the object

[gem5-dev] changeset in gem5: scons: Enforce gcc = 4.4 or clang = 2.9 and...

changeset 965d857ac791 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=965d857ac791 description: scons: Enforce gcc = 4.4 or clang = 2.9 and c++0x support This patch checks that the compiler in use is either gcc = 4.4 or clang = 2.9. and enables

[gem5-dev] changeset in gem5: dev: Do not serialize timer parameters

changeset b43a56850757 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=b43a56850757 description: dev: Do not serialize timer parameters This patch removes the intNum and clock from the serialized scalars as these are set by the Python parameters and

[gem5-dev] changeset in gem5: mem: Remove the IIC replacement policy

changeset 34d2e8082912 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=34d2e8082912 description: mem: Remove the IIC replacement policy The IIC replacement policy seems to be unused and has probably gathered too much bit rot to be useful. This patch

[gem5-dev] changeset in gem5: arch: Add support for invalidating TLBs when ...

changeset 43caa4ca5979 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=43caa4ca5979 description: arch: Add support for invalidating TLBs when draining This patch adds support for the memInvalidate() drain method. TLB flushing is requested by calling

[gem5-dev] changeset in gem5: cpu: Check that the memory system is in the c...

changeset d631aac65246 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=d631aac65246 description: cpu: Check that the memory system is in the correct mode This patch adds checks to all CPU models to make sure that the memory system is in the correct

[gem5-dev] changeset in gem5: arch: Move the ISA object to a separate section

changeset a24092160ec7 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=a24092160ec7 description: arch: Move the ISA object to a separate section After making the ISA an independent SimObject, it is serialized automatically by the Python world.

[gem5-dev] changeset in gem5: cpu: Implement a flat register interface in t...

changeset 0548b3e9734d in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=0548b3e9734d description: cpu: Implement a flat register interface in thread contexts Some architectures map registers differently depending on their mode of operations. There is

[gem5-dev] changeset in gem5: cpu: Initialize the O3 pipeline from startup()

changeset ddf45c1d54d4 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=ddf45c1d54d4 description: cpu: Initialize the O3 pipeline from startup() The entire O3 pipeline used to be initialized from init(), which is called before initState() or

[gem5-dev] changeset in gem5: cpu: Unify SimpleCPU and O3 CPU serialization...

changeset 029dfe6324d3 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=029dfe6324d3 description: cpu: Unify SimpleCPU and O3 CPU serialization code The O3 CPU used to copy its thread context to a SimpleThread in order to do serialization. This was a

[gem5-dev] changeset in gem5: cpu: Correctly call parent on switchOut() and...

changeset 7c787b8030c6 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=7c787b8030c6 description: cpu: Correctly call parent on switchOut() and takeOverFrom() This patch cleans up the CPU switching functionality by making sure that CPU models

[gem5-dev] changeset in gem5: cpu: Introduce sanity checks when switching b...

changeset a113f27b68bd in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=a113f27b68bd description: cpu: Introduce sanity checks when switching between CPUs This patch introduces the following sanity checks when switching between CPUs: * Check

[gem5-dev] changeset in gem5: arm: Remove the register mapping hack used wh...

changeset 8bb372a49e1b in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=8bb372a49e1b description: arm: Remove the register mapping hack used when copying TCs In order to see all registers independent of the current CPU mode, the ARM architecture model

[gem5-dev] changeset in gem5: cpu: Remove unused params.hh header file in i...

changeset f902aa5773a8 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=f902aa5773a8 description: cpu: Remove unused params.hh header file in inorder CPU diffstat: src/cpu/inorder/first_stage.hh |1 - src/cpu/inorder/params.hh

[gem5-dev] changeset in gem5: cpu: Rename defer_registration-switched_out

changeset 34971d2e0019 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=34971d2e0019 description: cpu: Rename defer_registration-switched_out The defer_registration parameter is used to prevent a CPU from initializing at startup, leaving it in the

[gem5-dev] changeset in gem5: sim: Remove unused variables

changeset 987d04d37a77 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=987d04d37a77 description: sim: Remove unused variables diffstat: src/sim/pseudo_inst.hh | 7 --- 1 files changed, 0 insertions(+), 7 deletions(-) diffs (17 lines): diff -r 34971d2e0019 -r

[gem5-dev] changeset in gem5: tests: Update the ignore regexps to reflect t...

changeset e7c4f86ffa40 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=e7c4f86ffa40 description: tests: Update the ignore regexps to reflect the M5-gem5 name change diffstat: tests/SConscript | 6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-) diffs (16

[gem5-dev] changeset in gem5: o3 cpu: Remove unused variables

changeset 4a0223da4924 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=4a0223da4924 description: o3 cpu: Remove unused variables diffstat: src/cpu/o3/cpu.cc | 3 --- src/cpu/o3/cpu.hh | 8 src/cpu/o3/thread_context_impl.hh

[gem5-dev] changeset in gem5: cpu: Fix broken squashAfter implementation in...

changeset 8088e94a9de0 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=8088e94a9de0 description: cpu: Fix broken squashAfter implementation in O3 CPU Commit can currently both commit and squash in the same cycle. This confuses other stages since the

[gem5-dev] changeset in gem5: arm: Fix draining of the pagetable walker whe...

changeset ef92e4f00551 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=ef92e4f00551 description: arm: Fix draining of the pagetable walker when squashing Since the page table walker only checks if a drain has completed in doL1DescriptorWrapper() and

[gem5-dev] changeset in gem5: cpu: Rewrite O3 draining to avoid stopping in...

changeset ab47fe7f03f0 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=ab47fe7f03f0 description: cpu: Rewrite O3 draining to avoid stopping in microcode Previously, the O3 CPU could stop in the middle of a microcode sequence. This patch makes sure

[gem5-dev] changeset in gem5: mem: Fix guest corruption when caches handle ...

changeset 5963165c00cb in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=5963165c00cb description: mem: Fix guest corruption when caches handle uncacheable accesses When the classic gem5 cache sees an uncacheable memory access, it used to ignore it or

[gem5-dev] changeset in gem5: cpu: Flush TLBs on switchOut()

changeset 644f2a2c9bfc in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=644f2a2c9bfc description: cpu: Flush TLBs on switchOut() This changeset inserts a TLB flush in BaseCPU::switchOut to prevent stale translations when doing repeated switching.

[gem5-dev] changeset in gem5: tests: Add CPU switching tests

changeset 156f74caf0d4 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=156f74caf0d4 description: tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations:

[gem5-dev] changeset in gem5: cpu: Unify the serialization code for all of ...

changeset 569d1e8f74e4 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=569d1e8f74e4 description: cpu: Unify the serialization code for all of the CPU models Cleanup the serialization code for the simple CPUs and the O3 CPU. The CPU-specific code has

[gem5-dev] changeset in gem5: stats: update stats for previous changes.

changeset 56610ab73040 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=56610ab73040 description: stats: update stats for previous changes. diffstat: tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini |57 +-

Re: [gem5-dev] Review Request: Let the user execute a file just before 'Simulation.run'

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/1455/#review3783 --- Ship it! this seems fine to me, anyone else have some input? - Ali

Re: [gem5-dev] Review Request: Let the user execute a file just before 'Simulation.run'

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/1455/#review3784 --- In general I would prefer an approach where unique simulation

[gem5-dev] Review Request: cpu: Add CPU metadata om the Python classes

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/1604/ --- Review request for Default. Description --- Changeset 9453:cda2b4ac704d

[gem5-dev] Review Request: cpu: Make checker CPUs inherit from CheckerCPU in the Python hierarchy

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/1605/ --- Review request for Default. Description --- Changeset 9454:9d423ab04d93

[gem5-dev] Review Request: config: Cleanup CPU configuration

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/1606/ --- Review request for Default. Description --- Changeset 9455:969ab2ed5cfa

[gem5-dev] Review Request: config: Move CPU handover logic to m5.switchCpus()

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/1607/ --- Review request for Default. Description --- Changeset 9456:49f2f54ed9ba

[gem5-dev] Review Request: config: Remove O3 dependencies

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/1608/ --- Review request for Default. Description --- Changeset 9457:fd01ef3f4a58

[gem5-dev] Review Request: cpu: Refactor memory system checks

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/1609/ --- Review request for Default. Description --- Changeset 9458:1a12feac8b2a

[gem5-dev] Review Request: sim: Add a system-global option to bypass caches

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/1611/ --- Review request for Default. Description --- Changeset 9460:7faa52ccf81f

[gem5-dev] Review Request: arm: Create a GIC base class and make the PL390 derive from it

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/1612/ --- Review request for Default. Description --- Changeset 9461:fc7fba1ec66f

[gem5-dev] Review Request: arm: Don't export private GIC methods

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/1613/ --- Review request for Default. Description --- Changeset 9462:4a0b2948e930

Re: [gem5-dev] Review Request: Let the user execute a file just before 'Simulation.run'

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/1455/#review3787 --- I agree with Steve. I'm not at all a fan of adding more cruft to the

[gem5-dev] changeset in gem5: stats: Fix swig wrapping for Tick in stats

changeset 35d4879ad7c2 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=35d4879ad7c2 description: stats: Fix swig wrapping for Tick in stats Tick was not correctly wrapped for the stats system, and therefore it was not possible to configure the stats

[gem5-dev] changeset in gem5: dev: Fix infinite recursion in DMA devices

changeset b41dac174706 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=b41dac174706 description: dev: Fix infinite recursion in DMA devices The DMA device sometimes calls the process() method on a completion event directly instead of scheduling it on

[gem5-dev] changeset in gem5: util: Fix stack corruption in the m5 util

changeset f56816facd25 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=f56816facd25 description: util: Fix stack corruption in the m5 util The number of arguments specified when calling parse_int_args() in do_exit() is incorrect. This leads to stack