Andreas, in the file src/mem/protocol/MOESI_hammer-dir.sm, set the access
permission for state WB_E_W to Read_Write, instead of Busy, the current
set permission. See if this helps in removing the error.
--
Nilay
On Mon, January 9, 2012 7:58 am, Andreas Hansson wrote:
Is your suggestion to live
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Congrats on getting MIPS_FS to work and taking the next step in the
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Ship it!
- Brad
On 2012-01-07 08:11:56, Nilay Vaish wrote:
On 2012-01-09 11:38:49, Brad Beckmann wrote:
Brad,
would you be against enabling TSO through a CPU parameter option rather then an
ISA characteristic?
- Korey
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On 2012-01-06 17:49:56, Brad Beckmann wrote:
src/mem/ruby/system/Sequencer.cc, line 526
http://reviews.m5sim.org/r/927/diff/2/?file=16851#file16851line526
I like the term cooldown, but I think it is a little bit confusing in
this situation. If I understand this code correctly,
If it doesn’t impact the lsq design much, would prefer a new command so that
the code is more clear. At the very least, there should be a comment better
explaining what is going on and what makes the packet a snoop packet.
Brad
From: Nilay Vaish [mailto:ni...@cs.wisc.edu]
Sent: Friday,
On 2012-01-07 08:43:59, Korey Sewell wrote:
src/arch/alpha/isa_traits.hh, line 133
http://reviews.m5sim.org/r/908/diff/3/?file=17419#file17419line133
Guys, I dont think this should be enabled/disabled through the ISA
TRAITS.
Then, if you are doing any architectural
On 2012-01-07 08:43:59, Korey Sewell wrote:
src/arch/alpha/isa_traits.hh, line 133
http://reviews.m5sim.org/r/908/diff/3/?file=17419#file17419line133
Guys, I dont think this should be enabled/disabled through the ISA
TRAITS.
Then, if you are doing any architectural
I think a new thread and a new event queue are independent. I don't
like how we're already adding something to run time forward and then
throw things away and roll back time. Time should be monotonically
increasing.
Gabe
Quoting Beckmann, Brad brad.beckm...@amd.com:
Make it a separate
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Review request for Default.
Summary
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Stats: Add stats for instructions and
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(Updated 2012-01-09 13:53:20.362595)
Review request for Default.
Summary
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(Updated 2012-01-09 13:54:02.889166)
Review request for Default.
Summary
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(Updated 2012-01-09 13:54:23.085169)
Review request for Default.
Summary
changeset 44203702a57a in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=44203702a57a
description:
SWIG: Make gem5 compile and link with swig 2.0.4
To make gem5 compile and run with swig 2.0.4 a few minor fixes are
necessary, the fail label issues by
changeset e4001326a5ba in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=e4001326a5ba
description:
MAC: Make gem5 compile and run on MacOSX 10.7.2
Adaptations to make gem5 compile and run on OSX 10.7.2, with a stock
gcc 4.2.1 and the remaining
changeset f1a69b7246f7 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=f1a69b7246f7
description:
Base: Fixed shift amount in genrand() to work with large numbers
The previous version didn't work correctly with max integer values
(2^31-1 for
32-bit,
changeset 78f27ef5e919 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=78f27ef5e919
description:
ARM: Add support for initparam m5 op
diffstat:
configs/common/Options.py| 3 ++-
configs/example/fs.py| 3 +++
src/arch/arm/isa/insts/m5ops.isa
changeset b68ae43bc806 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=b68ae43bc806
description:
stats: Update stats for ARM init param changes.
diffstat:
tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini |8
+-
changeset d4548b381e87 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=d4548b381e87
description:
O3: Add support of function tracing with O3 CPU.
diffstat:
src/cpu/base.hh | 9 -
src/cpu/o3/commit_impl.hh | 3 +++
2 files changed, 7
changeset 42052d5bb793 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=42052d5bb793
description:
config: support outputing a pickle of the configuration tree
diffstat:
src/python/m5/SimObject.py | 45 +++--
changeset 97d873b8b13e in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=97d873b8b13e
description:
sim: Enable sampling of run-time for code-sections marked using pseudo
insts.
This patch adds a mechanism to collect run time samples for specific
portions
changeset 62372a8d4ef2 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=62372a8d4ef2
description:
stats: fix Vector2d to display stats correctly when y_subname is not
specified.
Vector2d stats with no y_subname were not displayed as the VectorPrint
subname
changeset be72c2a127b2 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=be72c2a127b2
description:
Packet: Add derived class FunctionalPacket to enable partial functional
reads
This adds the derived class FunctionalPacket to fix a long standing
On 2012-01-09 11:38:49, Brad Beckmann wrote:
Korey Sewell wrote:
Brad,
would you be against enabling TSO through a CPU parameter option rather
then an ISA characteristic?
I'm neutral on this, either way is fine, but I think the name HasTSO isn't
ideal. An ISA is TSO, but I
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Thanks for taking the time to do this Tony!
It's pretty much looks
On 2012-01-09 16:30:29, Ali Saidi wrote:
Thanks for taking the time to do this Tony!
It's pretty much looks great, however, the style guide says that member
variables should be mixed case and not contain underscores (e.g.
instructionsExecuted instead of instructions_executed).
That is fine. I can see arguments both ways, but go for it.
Ali
On 09.01.2012 18:30, Nilay Vaish wrote:
Ali, are you sure that 'an
ISA is total store order' is grammatically
correct? I chose hasTSO on
purpose, since I feel 'an ISA has total store
order' is correct.
--
Nilay
On
HasTSO is acceptable to me, but if we're looking for alternatives, we could
do NeedsTSO instead (since in a sense the consistency model is a
requirement the ISA puts on the memory system).
Steve
On Mon, Jan 9, 2012 at 4:34 PM, Ali Saidi sa...@umich.edu wrote:
That is fine. I can see
I declare Steve to be the winner!
--
Nilay
On Mon, 9 Jan 2012, Steve Reinhardt wrote:
HasTSO is acceptable to me, but if we're looking for alternatives, we could
do NeedsTSO instead (since in a sense the consistency model is a
requirement the ISA puts on the memory system).
Steve
On Mon,
This is mostly true and I wouldn't be apposed to (re)implementing code
like that, but there are other uses of functional access like
verification by the checker, binary loading, pseudo instructions,
remote gdb, address translation done by the simulator itself, etc.
While that would make it
changeset aae12ce9f34c in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=aae12ce9f34c
description:
CPU: Remove Alpha-specific PC alignment check.
diffstat:
src/cpu/pc_event.cc | 6 --
1 files changed, 4 insertions(+), 2 deletions(-)
diffs (23 lines):
diff -r
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Review request for Default.
Summary
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util: implement writefile gem5 op to
I think HasTSO, NeedsTSO, IsTSO, TSOsBFF, whatever, is fine, since all
of them indicate TSO is being turned on.
The idea that when I want generalization it's for generalization's
sake implies that I have no justification other than it's just what
trips my trigger is nonsense and extremely
Hi Gabe,
that comment about generalization was not directed at you personally, I was
just trying to be funny that the conversation seems to always be a
balancing act between practicality and generality... bad joke if you took
that comment to be for you (I was the one suggesting not to put it in
On Fri, 6 Jan 2012, nathan binkert wrote:
I followed the second approach for updating the repo. The tests directory is
half the size now. I also checked the diff between e66a566f2cfa and
8b532495bf80. It is only 4882 lines now, compared to 1.8 million lines
earlier.
Great. Repo is back on
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