[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: RISC-V HiFive Platform implementation

[Peter Yuen (Gerrit) via gem5-dev]

Peter Yuen has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/40599 )



Change subject: arch-riscv: RISC-V HiFive Platform implementation
..

arch-riscv: RISC-V HiFive Platform implementation

This patch implements the RISC-V HiFive Platform
(based on the SiFive HiFive series). The HiFive
platform requires a PLIC and CLINT device (based on
current HiFive boards).

The optional uart_int_id field redirects Console interrupts
to the PLIC interrupt controller.\

PlicDevice is a wrapper around BasicPioDevice that
requires an interrupt ID. Interrupts are expected to
be raised via platform->postPciInterrupt(id).

VirtIOMMIO is a slight modification from the ARM
implementation such that interrupts are posted through
PLIC\

PlicDevice is a wrapper around BasicPioDevice that
requires an interrupt ID. Interrupts are expected to
be raised via platform->postPciInterrupt(id).

VirtIOMMIO is a slight modification from the ARM
implementation such that interrupts are posted through
PLIC.

Change-Id: I4bbdb5f903b52a41d1b7e0ccc44877c46cd30d56
---
A src/dev/riscv/HiFive.py
A src/dev/riscv/PlicDevice.py
M src/dev/riscv/SConscript
A src/dev/riscv/VirtIOMMIO.py
A src/dev/riscv/hifive.cc
A src/dev/riscv/hifive.hh
A src/dev/riscv/plic_device.cc
A src/dev/riscv/plic_device.hh
A src/dev/riscv/vio_mmio.cc
A src/dev/riscv/vio_mmio.hh
10 files changed, 832 insertions(+), 0 deletions(-)



diff --git a/src/dev/riscv/HiFive.py b/src/dev/riscv/HiFive.py
new file mode 100755
index 000..f1b12fc
--- /dev/null
+++ b/src/dev/riscv/HiFive.py
@@ -0,0 +1,50 @@
+# -*- mode:python -*-
+
+# Copyright (c) 2021 Huawei International
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder.  You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+from m5.objects.Platform import Platform
+from m5.params import *
+from m5.proxy import *
+
+class HiFive(Platform):
+type = 'HiFive'
+cxx_header = "dev/riscv/hifive.hh"
+system = Param.System(Parent.any, "system")
+clint = Param.Clint("CLINT")
+plic = Param.Plic("PLIC")
+# Int source ID to redirect console interrupts to
+# Set to 0 if using a pci interrupt for Uart instead
+uart_int_id = Param.Int(0, "PLIC Uart interrupt ID")
\ No newline at end of file
diff --git a/src/dev/riscv/PlicDevice.py b/src/dev/riscv/PlicDevice.py
new file mode 100644
index 000..f94b04b
--- /dev/null
+++ b/src/dev/riscv/PlicDevice.py
@@ -0,0 +1,48 @@
+# -*- mode:python -*-
+
+# Copyright (c) 2021 Huawei International
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder.  You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# 

[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: PLIC Implementation

[Peter Yuen (Gerrit) via gem5-dev]

Peter Yuen has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/40598 )



Change subject: arch-riscv: PLIC Implementation
..

arch-riscv: PLIC Implementation

This patch contains the implementation for the RISC-V PLIC.
The PLIC Memory Map is based on the SiFive U54MC datasheet.
The PLIC models a 3-cycle latency as stated in the RISC-V
specs.

Change-Id: I571c7bd3bd2918c92e4f207a1b57cf9d06e9c72f
---
A src/dev/riscv/Plic.py
M src/dev/riscv/SConscript
A src/dev/riscv/plic.cc
A src/dev/riscv/plic.hh
4 files changed, 884 insertions(+), 0 deletions(-)



diff --git a/src/dev/riscv/Plic.py b/src/dev/riscv/Plic.py
new file mode 100644
index 000..9650ff3
--- /dev/null
+++ b/src/dev/riscv/Plic.py
@@ -0,0 +1,47 @@
+# -*- mode:python -*-
+
+# Copyright (c) 2021 Huawei International
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder.  You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+from m5.objects.Device import BasicPioDevice
+from m5.params import *
+from m5.proxy import *
+
+class Plic(BasicPioDevice):
+type = 'Plic'
+cxx_header = 'dev/riscv/plic.hh'
+intrctrl = Param.IntrControl(Parent.any, "interrupt controller")
+pio_size = Param.Addr(0x400, "PIO Size")
+n_src = Param.Int("Number of interrupt sources")
diff --git a/src/dev/riscv/SConscript b/src/dev/riscv/SConscript
index b2092ca..300c099 100755
--- a/src/dev/riscv/SConscript
+++ b/src/dev/riscv/SConscript
@@ -30,7 +30,10 @@

 if env['TARGET_ISA'] == 'riscv':
 SimObject('Clint.py')
+SimObject('Plic.py')

 DebugFlag('RiscvClint')
+DebugFlag('RiscvPlic')

 Source('clint.cc')
+Source('plic.cc')
diff --git a/src/dev/riscv/plic.cc b/src/dev/riscv/plic.cc
new file mode 100644
index 000..fbea925
--- /dev/null
+++ b/src/dev/riscv/plic.cc
@@ -0,0 +1,535 @@
+/*
+ * Copyright (c) 2021 Huawei International
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the 

[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: Implementation of CLINT

[Peter Yuen (Gerrit) via gem5-dev]

Peter Yuen has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/40597 )



Change subject: arch-riscv: Implementation of CLINT
..

arch-riscv: Implementation of CLINT

This patch implements the CLINT device model based
on the SiFive U54MC datasheet. Currently, the RTC
is included in the CLINT device model. This will be
moved out in future patches. Instead, CLINT will receive
the clock signal via an InterruptPin.

isa.cc is also modified to provide a correct implementation
of the rdtime instruction. It will read from the miscreg
file (which is updated by CLINT every time mtime is
incremented).

Change-Id: I6f5393f3a8fdbd059f25df51d3d74bcb28da09f1
---
M src/arch/riscv/isa.cc
A src/dev/riscv/Clint.py
A src/dev/riscv/SConscript
A src/dev/riscv/clint.cc
A src/dev/riscv/clint.hh
5 files changed, 484 insertions(+), 1 deletion(-)



diff --git a/src/arch/riscv/isa.cc b/src/arch/riscv/isa.cc
index 8401310..2251f9f 100644
--- a/src/arch/riscv/isa.cc
+++ b/src/arch/riscv/isa.cc
@@ -261,7 +261,7 @@
 if (hpmCounterEnabled(MISCREG_TIME)) {
 DPRINTF(RiscvMisc, "Wall-clock counter at: %llu.\n",
 std::time(nullptr));
-return std::time(nullptr);
+return readMiscRegNoEffect(MISCREG_TIME);
 } else {
 warn("Wall clock disabled.\n");
 return 0;
diff --git a/src/dev/riscv/Clint.py b/src/dev/riscv/Clint.py
new file mode 100644
index 000..8d527f7
--- /dev/null
+++ b/src/dev/riscv/Clint.py
@@ -0,0 +1,49 @@
+# -*- mode:python -*-
+
+# Copyright (c) 2021 Huawei International
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder.  You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+from m5.objects.Device import BasicPioDevice
+from m5.params import *
+from m5.proxy import *
+
+
+class Clint(BasicPioDevice):
+type = 'Clint'
+cxx_header = 'dev/riscv/clint.hh'
+intrctrl = Param.IntrControl(Parent.any, "interrupt controller")
+time = Param.Time('01/01/2009', "System time ('Now' for actual time)")
+frequency = Param.Frequency("1MHz", "RTC Frequency")
+pio_size = Param.Addr(0xC000, "PIO Size")
diff --git a/src/dev/riscv/SConscript b/src/dev/riscv/SConscript
new file mode 100755
index 000..b2092ca
--- /dev/null
+++ b/src/dev/riscv/SConscript
@@ -0,0 +1,36 @@
+# -*- mode:python -*-
+
+# Copyright (c) 2021 Huawei International
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor 

[gem5-dev] Change in gem5/gem5[develop]: arch-riscv,dev: Extended Register class to contain property

[Peter Yuen (Gerrit) via gem5-dev]

Peter Yuen has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/40595 )



Change subject: arch-riscv,dev: Extended Register class to contain property
..

arch-riscv,dev: Extended Register class to contain property

This is an extension of the templated Register class to
include an arbitrary property object associated with
the register. This allows for pre- and post-processing
before reads and after writes based on the register
property (using callbacks).

This register class is used in CLINT and PLIC to post
interrupts based on the register index.

Currently it is put under src/dev/riscv. If there are
more use cases in the future it might be useful to merge
it into the src/dev/reg_bank.hh file.

Change-Id: Ife58f4e89549e60c840a9e991e0041e83e479d4a
---
A src/dev/riscv/reg_bank.hh
1 file changed, 203 insertions(+), 0 deletions(-)



diff --git a/src/dev/riscv/reg_bank.hh b/src/dev/riscv/reg_bank.hh
new file mode 100644
index 000..8e72e37
--- /dev/null
+++ b/src/dev/riscv/reg_bank.hh
@@ -0,0 +1,203 @@
+/*
+ * Copyright (c) 2021 Huawei International
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __DEV_RISCV_REG_BANK_HH__
+#define __DEV_RISCV_REG_BANK_HH__
+#include "dev/reg_bank.hh"
+
+template 
+class PropRegisterBank : public RegisterBank {
+
+  public:
+
+constexpr PropRegisterBank(const std::string _name, Addr  
new_base) :

+RegisterBank(new_name, new_base)
+{}
+
+template 
+class PropRegister : public PropRegisterBank::RegisterBase
+{
+public:
+/**
+ * Type definitions for template deduction
+ */
+using This = PropRegister;
+typedef typename RegisterBank::template
+Register Register;
+typedef typename RegisterBank::RegisterBase  
RegisterBase;

+using CallBackFunc = std::function;
+
+/**
+ * Class variables
+ */
+Register reg;
+
+private:
+Prop _prop = {};
+CallBackFunc _readCallBack = emptyCallBack;
+CallBackFunc _writeCallBack = emptyCallBack;
+
+public:
+// Constructors
+constexpr PropRegister(const std::string _name,
+const Prop _prop, const Data _data) :
+RegisterBase(new_name, sizeof(new_data)),
+reg(new_name, new_data),
+_prop(new_prop) {}
+
+constexpr PropRegister(const std::string _name,
+const Prop &_prop, const Data &_data) :
+RegisterBase(new_name, sizeof(new_data)),
+reg(new_name, new_data),
+_prop(new_prop) {}
+
+// Callback functions
+static void emptyCallBack(This ) {}
+
+template 
+constexpr This &
+beforeRead(Parent *parent, void (Parent::*nr)(Args... args)) {
+auto wrapper = [parent, nr](Args &&... args) {
+   

[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: Modifications to Riscv FS Configuration

[Peter Yuen (Gerrit) via gem5-dev]

Peter Yuen has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/40600 )



Change subject: arch-riscv: Modifications to Riscv FS Configuration
..

arch-riscv: Modifications to Riscv FS Configuration

FSConfig is modified to connect necessary devices for
booting FS Linux. In future patches this will be organized
further. Devicetree generation feature might also be
added.

Change-Id: I94a07fc337f543f9a049ccac66689cfc50fdc8c8
---
M configs/common/FSConfig.py
M configs/example/fs.py
2 files changed, 54 insertions(+), 7 deletions(-)



diff --git a/configs/common/FSConfig.py b/configs/common/FSConfig.py
index 6665225..597fcf2 100644
--- a/configs/common/FSConfig.py
+++ b/configs/common/FSConfig.py
@@ -1,5 +1,6 @@
 # Copyright (c) 2010-2012, 2015-2019 ARM Limited
 # Copyright (c) 2020 Barkhausen Institut
+# Copyright (c) 2021 Huawei International
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -611,27 +612,72 @@
 self.workload.command_line = fillInCmdline(mdesc, cmdline)
 return self

-def makeBareMetalRiscvSystem(mem_mode, mdesc=None, cmdline=None):
+def makeLinuxRiscvSystem(mem_mode, mdesc=None, cmdline=None):
 self = System()
 if not mdesc:
 # generic system
 mdesc = SysConfig()
 self.mem_mode = mem_mode
-self.mem_ranges = [AddrRange(mdesc.mem())]
+self.mem_ranges = [AddrRange(start=0x8000, size=mdesc.mem())]

 self.workload = RiscvBareMetal()

 self.iobus = IOXBar()
 self.membus = MemBus()

+self.system_port = self.membus.slave
+
+self.intrctrl = IntrControl()
+
+# HiFive platform
+self.platform = HiFive()
+
+# CLNT
+self.platform.clint = Clint()
+self.platform.clint.frequency = Frequency("100MHz")
+self.platform.clint.pio = self.membus.master
+
+# PLIC
+self.platform.plic = Plic()
+self.platform.clint.pio_addr = 0x200
+self.platform.plic.pio_addr = 0xc00
+self.platform.plic.n_src = 11
+self.platform.plic.pio = self.membus.master
+
+# UART
+self.uart = Uart8250(pio_addr=0x1000)
+self.terminal = Terminal()
+self.platform.uart_int_id = 0xa
+self.uart.pio = self.iobus.master
+
+# VirtIOMMIO
+image = CowDiskImage(child=RawDiskImage(read_only=True),  
read_only=False)

+image.child.image_file = mdesc.disks()[0]
+self.platform.disk = MmioVirtIO(
+vio=VirtIOBlock(image=image),
+interrupt_id=0x8,
+pio_size = 4096
+)
+self.platform.disk.pio_addr = 0x10008000
+self.platform.disk.pio = self.iobus.master
+
+# PMA
+self.pma = PMA()
+self.pma.uncacheable = [
+AddrRange(0x1000, 0x1008),
+AddrRange(0x10008000, 0x10009000),
+AddrRange(0xc00, 0xc21),
+AddrRange(0x200, 0x201)
+]
+
 self.bridge = Bridge(delay='50ns')
 self.bridge.master = self.iobus.slave
 self.bridge.slave = self.membus.master
-# Sv39 has 56 bit physical addresses; use the upper 8 bit for the IO  
space

-IO_address_space_base = 0x00FF
-self.bridge.ranges = [AddrRange(IO_address_space_base, Addr.max)]
+self.bridge.ranges = [
+AddrRange(0x1000, 0x1080),
+AddrRange(0x10008000, 0x10009000)
+]

-self.system_port = self.membus.slave
 return self

 def makeDualRoot(full_system, testSystem, driveSystem, dumpfile):
diff --git a/configs/example/fs.py b/configs/example/fs.py
index f388503..f71912a 100644
--- a/configs/example/fs.py
+++ b/configs/example/fs.py
@@ -1,5 +1,6 @@
 # Copyright (c) 2010-2013, 2016, 2019-2020 ARM Limited
 # Copyright (c) 2020 Barkhausen Institut
+# Copyright (c) 2021 Huawei International
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -81,7 +82,7 @@
 elif buildEnv['TARGET_ISA'] == "sparc":
 test_sys = makeSparcSystem(test_mem_mode, bm[0], cmdline=cmdline)
 elif buildEnv['TARGET_ISA'] == "riscv":
-test_sys = makeBareMetalRiscvSystem(test_mem_mode, bm[0],
+test_sys = makeLinuxRiscvSystem(test_mem_mode, bm[0],
 cmdline=cmdline)
 elif buildEnv['TARGET_ISA'] == "x86":
 test_sys = makeLinuxX86System(test_mem_mode, np, bm[0],  
options.ruby,


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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I94a07fc337f543f9a049ccac66689cfc50fdc8c8
Gerrit-Change-Number: 40600
Gerrit-PatchSet: 1
Gerrit-Owner: Peter Yuen 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: Added PMA support for RiscvTLB

[Peter Yuen (Gerrit) via gem5-dev]

Peter Yuen has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/40596 )



Change subject: arch-riscv: Added PMA support for RiscvTLB
..

arch-riscv: Added PMA support for RiscvTLB

Since the RISC-V privileged specs V1.11 did not specify
an implementation of physical memory attributes (PMA), e.g.
cacheability, an abstract PMA class is created. This
class acts as a container storing the PMAs.

The TLB finds the PMA defined at the system level by
Parent.any.

Change-Id: I4400133895be44da67536d80b82422ec3a49d786
---
A src/arch/riscv/RiscvPMA.py
M src/arch/riscv/RiscvTLB.py
M src/arch/riscv/SConscript
A src/arch/riscv/pma.cc
A src/arch/riscv/pma.hh
M src/arch/riscv/tlb.cc
M src/arch/riscv/tlb.hh
7 files changed, 217 insertions(+), 2 deletions(-)



diff --git a/src/arch/riscv/RiscvPMA.py b/src/arch/riscv/RiscvPMA.py
new file mode 100644
index 000..8ab67ab
--- /dev/null
+++ b/src/arch/riscv/RiscvPMA.py
@@ -0,0 +1,46 @@
+# -*- mode:python -*-
+
+# Copyright (c) 2021 Huawei International
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder.  You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+from m5.SimObject import SimObject
+from m5.params import *
+from m5.proxy import *
+
+
+class PMA(SimObject):
+type = 'PMA'
+cxx_header = 'arch/riscv/pma.hh'
+uncacheable = VectorParam.AddrRange([], "Uncacheable address ranges")
diff --git a/src/arch/riscv/RiscvTLB.py b/src/arch/riscv/RiscvTLB.py
index 4844feb..a1f7e03 100644
--- a/src/arch/riscv/RiscvTLB.py
+++ b/src/arch/riscv/RiscvTLB.py
@@ -2,6 +2,7 @@

 # Copyright (c) 2007 MIPS Technologies, Inc.
 # Copyright (c) 2020 Barkhausen Institut
+# Copyright (c) 2021 Huawei International
 # All rights reserved.
 #
 # Redistribution and use in source and binary forms, with or without
@@ -49,3 +50,7 @@
 size = Param.Int(64, "TLB size")
 walker = Param.RiscvPagetableWalker(\
 RiscvPagetableWalker(), "page table walker")
+# The pma is found under the System object
+# defining PMA under the Platform object might not work
+# as the CPU and MMU are not children of the Platform
+pma = Param.PMA(Parent.any, "Physical Memory Attributes")
diff --git a/src/arch/riscv/SConscript b/src/arch/riscv/SConscript
index 472264f..ae0b438 100644
--- a/src/arch/riscv/SConscript
+++ b/src/arch/riscv/SConscript
@@ -54,6 +54,7 @@
 Source('reg_abi.cc')
 Source('remote_gdb.cc')
 Source('tlb.cc')
+Source('pma.cc')

 Source('linux/se_workload.cc')
 Source('linux/linux.cc')
@@ -64,6 +65,7 @@
 SimObject('RiscvInterrupts.py')
 SimObject('RiscvISA.py')
 SimObject('RiscvMMU.py')
+SimObject('RiscvPMA.py')
 SimObject('RiscvSeWorkload.py')
 SimObject('RiscvTLB.py')

diff --git a/src/arch/riscv/pma.cc b/src/arch/riscv/pma.cc
new file mode 100644
index 000..a41e912
--- /dev/null
+++ b/src/arch/riscv/pma.cc
@@ -0,0 +1,73 @@
+/*
+ * Copyright (c) 2021 Huawei International
+ * All 

[gem5-dev] Change in gem5/gem5[develop]: misc: Merge branch v20.1.0.3 hotfix into develop

[Bobby R. Bruce (Gerrit) via gem5-dev]

Bobby R. Bruce has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/40535 )


Change subject: misc: Merge branch v20.1.0.3 hotfix into develop
..

misc: Merge branch v20.1.0.3 hotfix into develop

Change-Id: I12cca586627718bf41fe24f0fcd3f10c4fe48b2d
---
M src/Doxyfile
M src/arch/arm/system.cc
M src/base/version.cc
4 files changed, 1 insertion(+), 27 deletions(-)

Approvals:
  Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/Doxyfile b/src/Doxyfile
index 60ca662..ddc3933 100644
--- a/src/Doxyfile
+++ b/src/Doxyfile
@@ -31,11 +31,7 @@
 # This could be handy for archiving the generated documentation or
 # if some version control system is used.

-<<< HEAD   (758011 scons,python: Fix `--without-python` flag)
-PROJECT_NUMBER = DEVELOP-FOR-V20.2
-===
 PROJECT_NUMBER = v20.1.0.3
->>> BRANCH (cd21b5 misc: Updated the RELEASE-NOTES and version number)

 # The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute)
 # base path where the generated documentation will be put.
diff --git a/src/arch/arm/system.cc b/src/arch/arm/system.cc
index 22121e1..783366d 100644
--- a/src/arch/arm/system.cc
+++ b/src/arch/arm/system.cc
@@ -63,7 +63,6 @@
   _genericTimer(nullptr),
   _gic(nullptr),
   _pwrCtrl(nullptr),
-<<< HEAD   (758011 scons,python: Fix `--without-python` flag)
   _highestELIs64(p.highest_el_is_64),
   _physAddrRange64(p.phys_addr_range_64),
   _haveLargeAsid64(p.have_large_asid_64),
@@ -71,30 +70,13 @@
   _haveSVE(p.have_sve),
   _sveVL(p.sve_vl),
   _haveLSE(p.have_lse),
+  _haveVHE(p.have_vhe),
   _havePAN(p.have_pan),
   _haveSecEL2(p.have_secel2),
   semihosting(p.semihosting),
   multiProc(p.multi_proc)
-===
-  _highestELIs64(p->highest_el_is_64),
-  _physAddrRange64(p->phys_addr_range_64),
-  _haveLargeAsid64(p->have_large_asid_64),
-  _haveTME(p->have_tme),
-  _haveSVE(p->have_sve),
-  _sveVL(p->sve_vl),
-  _haveLSE(p->have_lse),
-  _haveVHE(p->have_vhe),
-  _havePAN(p->have_pan),
-  _haveSecEL2(p->have_secel2),
-  semihosting(p->semihosting),
-  multiProc(p->multi_proc)
->>> BRANCH (cd21b5 misc: Updated the RELEASE-NOTES and version number)
 {
-<<< HEAD   (758011 scons,python: Fix `--without-python` flag)
 if (p.auto_reset_addr) {
-===
-  if (p->auto_reset_addr) {
->>> BRANCH (cd21b5 misc: Updated the RELEASE-NOTES and version number)
 _resetAddr = workload->getEntry();
 } else {
 _resetAddr = p.reset_addr;
diff --git a/src/base/version.cc b/src/base/version.cc
index 59554d3..d30ddd1 100644
--- a/src/base/version.cc
+++ b/src/base/version.cc
@@ -29,8 +29,4 @@
 /**
  * @ingroup api_base_utils
  */
-<<< HEAD   (758011 scons,python: Fix `--without-python` flag)
-const char *gem5Version = "[DEVELOP-FOR-V20.2]";
-===
 const char *gem5Version = "20.1.0.3";
->>> BRANCH (cd21b5 misc: Updated the RELEASE-NOTES and version number)

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I12cca586627718bf41fe24f0fcd3f10c4fe48b2d
Gerrit-Change-Number: 40535
Gerrit-PatchSet: 1
Gerrit-Owner: Bobby R. Bruce 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: misc: Revert version info for develop branch

[Bobby R. Bruce (Gerrit) via gem5-dev]

Bobby R. Bruce has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/40536 )


Change subject: misc: Revert version info for develop branch
..

misc: Revert version info for develop branch

Change-Id: Ie01f41cb40b025ef31028bff4d59023e380fcf07
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40536
Reviewed-by: Bobby R. Bruce 
Maintainer: Bobby R. Bruce 
Tested-by: kokoro 
---
M src/Doxyfile
M src/base/version.cc
2 files changed, 2 insertions(+), 2 deletions(-)

Approvals:
  Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/Doxyfile b/src/Doxyfile
index ddc3933..d453314 100644
--- a/src/Doxyfile
+++ b/src/Doxyfile
@@ -31,7 +31,7 @@
 # This could be handy for archiving the generated documentation or
 # if some version control system is used.

-PROJECT_NUMBER = v20.1.0.3
+PROJECT_NUMBER = DEVELOP-FOR-V20.2

 # The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute)
 # base path where the generated documentation will be put.
diff --git a/src/base/version.cc b/src/base/version.cc
index d30ddd1..cfa98f9 100644
--- a/src/base/version.cc
+++ b/src/base/version.cc
@@ -29,4 +29,4 @@
 /**
  * @ingroup api_base_utils
  */
-const char *gem5Version = "20.1.0.3";
+const char *gem5Version = "[DEVELOP-FOR-V20.2]";

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ie01f41cb40b025ef31028bff4d59023e380fcf07
Gerrit-Change-Number: 40536
Gerrit-PatchSet: 2
Gerrit-Owner: Bobby R. Bruce 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: fastmodel: fix cntfrq in A76

[Earl Ou (Gerrit) via gem5-dev]

Earl Ou has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/40355 )


Change subject: fastmodel: fix cntfrq in A76
..

fastmodel: fix cntfrq in A76

Change-Id: I7d1167e8b61d6768039c34fe1ee54560f7845dfa
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40355
Reviewed-by: Ahbong Chang 
Maintainer: Gabe Black 
Tested-by: kokoro 
---
M src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
1 file changed, 1 insertion(+), 1 deletion(-)

Approvals:
  Ahbong Chang: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc  
b/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc

index 11e8c98..5da724b 100644
--- a/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
+++ b/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
@@ -42,7 +42,7 @@
 for (auto *tc : threadContexts)
 tc->setMiscRegNoEffect(ArmISA::MISCREG_CNTFRQ_EL0,  
params().cntfrq);


-evs_base_cpu->setSysCounterFrq(cluster->params().cntfrq);
+evs_base_cpu->setSysCounterFrq(params().cntfrq);
 }

 void

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I7d1167e8b61d6768039c34fe1ee54560f7845dfa
Gerrit-Change-Number: 40355
Gerrit-PatchSet: 2
Gerrit-Owner: Earl Ou 
Gerrit-Reviewer: Ahbong Chang 
Gerrit-Reviewer: Earl Ou 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-gcn3: Implementation of s_sleep

[Matt Sinclair (Gerrit) via gem5-dev]

Matt Sinclair has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39115 )


Change subject: arch-gcn3: Implementation of s_sleep
..

arch-gcn3: Implementation of s_sleep

This changeset implements the s_sleep instruction in a similar
way to s_waitcnt.

Change-Id: I4811c318ac2c76c485e2bfd9d93baa1205ecf183
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39115
Maintainer: Matthew Poremba 
Maintainer: Matt Sinclair 
Reviewed-by: Matt Sinclair 
Tested-by: kokoro 
---
M src/arch/gcn3/insts/instructions.cc
M src/gpu-compute/GPUStaticInstFlags.py
M src/gpu-compute/gpu_dyn_inst.cc
M src/gpu-compute/gpu_dyn_inst.hh
M src/gpu-compute/gpu_static_inst.hh
M src/gpu-compute/schedule_stage.cc
M src/gpu-compute/scoreboard_check_stage.cc
M src/gpu-compute/scoreboard_check_stage.hh
M src/gpu-compute/wavefront.cc
M src/gpu-compute/wavefront.hh
10 files changed, 81 insertions(+), 4 deletions(-)

Approvals:
  Matt Sinclair: Looks good to me, approved; Looks good to me, approved
  Matthew Poremba: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/gcn3/insts/instructions.cc  
b/src/arch/gcn3/insts/instructions.cc

index 8c02951..03b11ab 100644
--- a/src/arch/gcn3/insts/instructions.cc
+++ b/src/arch/gcn3/insts/instructions.cc
@@ -4187,6 +4187,8 @@
 Inst_SOPP__S_SLEEP::Inst_SOPP__S_SLEEP(InFmt_SOPP *iFmt)
 : Inst_SOPP(iFmt, "s_sleep")
 {
+setFlag(ALU);
+setFlag(Sleep);
 } // Inst_SOPP__S_SLEEP

 Inst_SOPP__S_SLEEP::~Inst_SOPP__S_SLEEP()
@@ -4197,8 +4199,12 @@
 void
 Inst_SOPP__S_SLEEP::execute(GPUDynInstPtr gpuDynInst)
 {
-panicUnimplemented();
-}
+ScalarRegI32 simm16 = (ScalarRegI32)instData.SIMM16;
+gpuDynInst->wavefront()->setStatus(Wavefront::S_STALLED_SLEEP);
+// sleep duration is specified in multiples of 64 cycles
+gpuDynInst->wavefront()->setSleepTime(64 * simm16);
+} // execute
+// --- Inst_SOPP__S_SETPRIO class methods ---

 Inst_SOPP__S_SETPRIO::Inst_SOPP__S_SETPRIO(InFmt_SOPP *iFmt)
 : Inst_SOPP(iFmt, "s_setprio")
diff --git a/src/gpu-compute/GPUStaticInstFlags.py  
b/src/gpu-compute/GPUStaticInstFlags.py

index ad4c6c3..1dc143c 100644
--- a/src/gpu-compute/GPUStaticInstFlags.py
+++ b/src/gpu-compute/GPUStaticInstFlags.py
@@ -48,6 +48,7 @@
 'UnconditionalJump', #
 'SpecialOp', # Special op
 'Waitcnt',   # Is a waitcnt instruction
+'Sleep', # Is a sleep instruction

 # Memory ops
 'MemBarrier',# Barrier instruction
diff --git a/src/gpu-compute/gpu_dyn_inst.cc  
b/src/gpu-compute/gpu_dyn_inst.cc

index a17a93f..b827632 100644
--- a/src/gpu-compute/gpu_dyn_inst.cc
+++ b/src/gpu-compute/gpu_dyn_inst.cc
@@ -399,6 +399,12 @@
 }

 bool
+GPUDynInst::isSleep() const
+{
+return _staticInst->isSleep();
+}
+
+bool
 GPUDynInst::isBarrier() const
 {
 return _staticInst->isBarrier();
diff --git a/src/gpu-compute/gpu_dyn_inst.hh  
b/src/gpu-compute/gpu_dyn_inst.hh

index 8c7cf87..851a46a 100644
--- a/src/gpu-compute/gpu_dyn_inst.hh
+++ b/src/gpu-compute/gpu_dyn_inst.hh
@@ -180,6 +180,7 @@
 bool isUnconditionalJump() const;
 bool isSpecialOp() const;
 bool isWaitcnt() const;
+bool isSleep() const;

 bool isBarrier() const;
 bool isMemSync() const;
diff --git a/src/gpu-compute/gpu_static_inst.hh  
b/src/gpu-compute/gpu_static_inst.hh

index 88fd9f9..f973f2f 100644
--- a/src/gpu-compute/gpu_static_inst.hh
+++ b/src/gpu-compute/gpu_static_inst.hh
@@ -119,6 +119,7 @@

 bool isSpecialOp() const { return _flags[SpecialOp]; }
 bool isWaitcnt() const { return _flags[Waitcnt]; }
+bool isSleep() const { return _flags[Sleep]; }

 bool isBarrier() const { return _flags[MemBarrier]; }
 bool isMemSync() const { return _flags[MemSync]; }
diff --git a/src/gpu-compute/schedule_stage.cc  
b/src/gpu-compute/schedule_stage.cc

index 02580fe..8a2ea18 100644
--- a/src/gpu-compute/schedule_stage.cc
+++ b/src/gpu-compute/schedule_stage.cc
@@ -317,6 +317,9 @@
 if (wf->isOldestInstWaitcnt()) {
 wf->setStatus(Wavefront::S_WAITCNT);
 }
+if (wf->isOldestInstSleep()) {
+wf->setStatus(Wavefront::S_STALLED_SLEEP);
+}
 if (!gpu_dyn_inst->isScalar()) {
 computeUnit.vrf[wf->simdId]
 ->scheduleReadOperands(wf, gpu_dyn_inst);
diff --git a/src/gpu-compute/scoreboard_check_stage.cc  
b/src/gpu-compute/scoreboard_check_stage.cc

index c246279..08ce6a1 100644
--- a/src/gpu-compute/scoreboard_check_stage.cc
+++ b/src/gpu-compute/scoreboard_check_stage.cc
@@ -92,6 +92,15 @@
 }
 }

+// sleep instruction has been dispatched or executed: next
+// instruction should be blocked until the sleep period expires.
+if (w->getStatus() == Wavefront::S_STALLED_SLEEP) {
+if 

[gem5-dev] Change in gem5/gem5[develop]: arch-x86: Make JRCXZ instruction do 64-bit jump

[Matt Sinclair (Gerrit) via gem5-dev]

Matt Sinclair has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/40195 )


Change subject: arch-x86: Make JRCXZ instruction do 64-bit jump
..

arch-x86: Make JRCXZ instruction do 64-bit jump

Per the AMD64 Architecture Programming Manual:

The size of the count register (CX, ECX, or RCX) depends on the
address-size attribute of the JrCXZ instruction. Therefore, JRCXZ can
only be executed in 64-bit mode

and

In 64-bit mode, the operand size defaults to 64 bits. The processor
sign-extends the 8-bit displacement value to 64 bits before adding it
to the RIP.

This patch also renames the instruction from JRCX to JRCXZ to match the
language in the programming manual.

Change-Id: Id55147d0602ff41ad6aaef483bef722ff56cae62
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40195
Reviewed-by: Matt Sinclair 
Maintainer: Matt Sinclair 
Tested-by: kokoro 
---
M src/arch/x86/isa/decoder/one_byte_opcodes.isa
M  
src/arch/x86/isa/insts/general_purpose/control_transfer/conditional_jump.py

2 files changed, 4 insertions(+), 2 deletions(-)

Approvals:
  Matt Sinclair: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/x86/isa/decoder/one_byte_opcodes.isa  
b/src/arch/x86/isa/decoder/one_byte_opcodes.isa

index b5f77cd..04b3adc 100644
--- a/src/arch/x86/isa/decoder/one_byte_opcodes.isa
+++ b/src/arch/x86/isa/decoder/one_byte_opcodes.isa
@@ -483,7 +483,7 @@
 0x0: LOOPNE(Jb);
 0x1: LOOPE(Jb);
 0x2: LOOP(Jb);
-0x3: JRCX(Jb);
+0x3: JRCXZ(Jb);
 0x4: IN(rAb,Ib);
 0x5: IN(rAv,Iv);
 0x6: OUT(Ib,rAb);
diff --git  
a/src/arch/x86/isa/insts/general_purpose/control_transfer/conditional_jump.py  
b/src/arch/x86/isa/insts/general_purpose/control_transfer/conditional_jump.py

index 390a08b..d0fa31a 100644
---  
a/src/arch/x86/isa/insts/general_purpose/control_transfer/conditional_jump.py
+++  
b/src/arch/x86/isa/insts/general_purpose/control_transfer/conditional_jump.py

@@ -210,8 +210,10 @@
 wrip t1, t2, flags=(nCOF,)
 };

-def macroop JRCX_I
+def macroop JRCXZ_I
 {
+# Make the default data size of jumps 64 bits in 64 bit mode
+.adjust_env oszIn64Override
 .control_direct

 rdip t1

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Id55147d0602ff41ad6aaef483bef722ff56cae62
Gerrit-Change-Number: 40195
Gerrit-PatchSet: 3
Gerrit-Owner: Kyle Roarty 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Matt Sinclair 
Gerrit-Reviewer: kokoro 
Gerrit-CC: Alexandru Duțu 
Gerrit-CC: Jason Lowe-Power 
Gerrit-CC: Matthew Poremba 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: mem: Change warmupCycle stat to warmupTick

[Hoa Nguyen (Gerrit) via gem5-dev]

Hoa Nguyen has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/40575 )



Change subject: mem: Change warmupCycle stat to warmupTick
..

mem: Change warmupCycle stat to warmupTick

Change-Id: I96399dc5c062479049e7bf0de91d9f4f97903c43
Signed-off-by: Hoa Nguyen 
---
M src/mem/cache/tags/base.cc
M src/mem/cache/tags/base.hh
2 files changed, 5 insertions(+), 5 deletions(-)



diff --git a/src/mem/cache/tags/base.cc b/src/mem/cache/tags/base.cc
index f2c35c1..62fec36 100644
--- a/src/mem/cache/tags/base.cc
+++ b/src/mem/cache/tags/base.cc
@@ -115,7 +115,7 @@
 // Check if cache warm up is done
 if (!warmedUp && stats.tagsInUse.value() >= warmupBound) {
 warmedUp = true;
-stats.warmupCycle = ticksToCycles(curTick());
+stats.warmupTick = curTick();
 }

 // We only need to write into one tag and one data block.
@@ -224,8 +224,8 @@
  "Sample count of references to valid blocks."),
 ADD_STAT(avgRefs, UNIT_RATE(Stats::Units::Count, Stats::Units::Count),
  "Average number of references to valid blocks."),
-ADD_STAT(warmupCycle, UNIT_CYCLE,
- "Cycle when the warmup percentage was hit."),
+ADD_STAT(warmupTick, UNIT_TICK,
+ "The tick when the warmup percentage was hit."),
 ADD_STAT(occupancies, UNIT_RATE(Stats::Units::Ratio,  
Stats::Units::Tick),

  "Average occupied blocks per tick, per requestor"),
 ADD_STAT(avgOccs, UNIT_RATIO, "Average percentage of cache occupancy"),
diff --git a/src/mem/cache/tags/base.hh b/src/mem/cache/tags/base.hh
index 5a407a6..040986c 100644
--- a/src/mem/cache/tags/base.hh
+++ b/src/mem/cache/tags/base.hh
@@ -130,8 +130,8 @@
  */
 Stats::Formula avgRefs;

-/** The cycle that the warmup percentage was hit. 0 on failure. */
-Stats::Scalar warmupCycle;
+/** The tick that the warmup percentage was hit. 0 on failure. */
+Stats::Scalar warmupTick;

 /** Average occupancy of each requestor using the cache */
 Stats::AverageVector occupancies;

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I96399dc5c062479049e7bf0de91d9f4f97903c43
Gerrit-Change-Number: 40575
Gerrit-PatchSet: 1
Gerrit-Owner: Hoa Nguyen 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: tests: Changed 'long' boot tests to X86 from GCN3_X86

[Bobby R. Bruce (Gerrit) via gem5-dev]

Bobby R. Bruce has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/40415 )


Change subject: tests: Changed 'long' boot tests to X86 from GCN3_X86
..

tests: Changed 'long' boot tests to X86 from GCN3_X86

We compile GCN3_X86 for the 'quick' tests, as a substitute for X86. We
compile X86 as part of our nightly tests, along with the running of the
'long' tests. This leads to a needless duplicate compilation of the X86
isa during our nightly tests. Therefore, this commit removes GCN3_X86
for the 'long' tests (only the x86 boot tests are affected).

Change-Id: Ifd8aaf0e7b8178c588ace33b27671d4ba9b353ed
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40415
Reviewed-by: Jason Lowe-Power 
Reviewed-by: Matt Sinclair 
Maintainer: Jason Lowe-Power 
Maintainer: Matt Sinclair 
Tested-by: kokoro 
---
M tests/gem5/x86-boot-tests/test_linux_boot.py
1 file changed, 1 insertion(+), 1 deletion(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  Matt Sinclair: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/tests/gem5/x86-boot-tests/test_linux_boot.py  
b/tests/gem5/x86-boot-tests/test_linux_boot.py

index 62f82f9..5422425 100644
--- a/tests/gem5/x86-boot-tests/test_linux_boot.py
+++ b/tests/gem5/x86-boot-tests/test_linux_boot.py
@@ -60,7 +60,7 @@
 '--num-cpus', num_cpus,
 '--boot-type', boot_type,
 ],
-valid_isas = (constants.gcn3_x86_tag,),
+valid_isas = (constants.x86_tag,),
 valid_hosts = host,
 length = constants.long_tag,
 )

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/40415
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ifd8aaf0e7b8178c588ace33b27671d4ba9b353ed
Gerrit-Change-Number: 40415
Gerrit-PatchSet: 2
Gerrit-Owner: Bobby R. Bruce 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Matt Sinclair 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] gem5 21.0 to be released March 2021; 2 weeks to get in your changes!

[Bobby Bruce via gem5-dev]

Dear all,

We plan to release gem5 v21.0.0.0 next month. As such, we will be creating
our release-staging branch from the develop branch on February 16th.
Anything fully submitted on the develop branch by this date will be
included in the gem5 21.0 release.

Submitting patches to the release-staging branch will be possible, though
only changes that improve the stability of the release will be permitted
(normal development may continue on the develop branch during this time).
The primary purpose of the staging branch period is to test the release and
ensure overall quality for wide community usage. The branch shall exist
until we are satisfied with the stability of the release. We predict this
should take no less than 2 weeks. After this, we will merge the staging
branch into the develop and stable branches. Once merged, the release of
gem5 version 21.0.0.0 will be complete.

Kind regards,
Bobby
--
Dr. Bobby R. Bruce
Room 2235,
Kemper Hall, UC Davis
Davis,
CA, 95616

web: https://www.bobbybruce.net
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[gem5-dev] Re: Build failed in Jenkins: Nightly #208

[Daniel Carvalho via gem5-dev]

 Fix here: https://gem5-review.googlesource.com/c/public/gem5/+/40555Em 
quarta-feira, 3 de fevereiro de 2021 17:18:14 BRT, jenkins-no-reply--- via 
gem5-dev  escreveu:  
 
 See 

Changes:

[gabe.black] ext: Update pybind11 to version 2.6.2.

[shunhsingou] systemc: remove boost header dependency

[Giacomo Travaglini] ext: testlib loading tests from multiple directories

[Bobby R. Bruce] util,python: Fix Pre-commit hooks to ignore non-source files

[Bobby R. Bruce] util,python: Add check to ensure files are utf-8 in pre-commit

[odanrc] scons: Separate debug flags from debug-format flags

[odanrc] sim: Move cur tick to its own files

[odanrc] base,tests: Add a basic fake class to handle curTick

[odanrc] base: Move Stats::Info functions to its own source file

[odanrc] base,tests: Create unit tests for Stats::Stor

[gabe.black] arch: Templatize the BasicDecodeCache.


--
[...truncated 532.91 KB...]
[--] 4 tests from TypesTest
[ RUN      ] TypesTest.FloatToBits32
[      OK ] TypesTest.FloatToBits32 (0 ms)
[ RUN      ] TypesTest.floatToBits64
[      OK ] TypesTest.floatToBits64 (0 ms)
[ RUN      ] TypesTest.floatsToBitsDoubleInput
[      OK ] TypesTest.floatsToBitsDoubleInput (0 ms)
[ RUN      ] TypesTest.floatsToBitsFloatInput
[      OK ] TypesTest.floatsToBitsFloatInput (0 ms)
[--] 4 tests from TypesTest (0 ms total)

[--] Global test environment tear-down
[==] 19 tests from 3 test suites ran. (6 ms total)
[  PASSED  ] 19 tests.
build/NULL/sim/byteswap.test.debug 
--gtest_output=xml:build/NULL/unittests.debug/sim/byteswap.test.xml
Running main() from build/googletest/googletest/src/gtest_main.cc
[==] Running 2 tests from 1 test suite.
[--] Global test environment set-up.
[--] 2 tests from UncontendedMutex
[ RUN      ] UncontendedMutex.Lock
build/NULL/base/debug.test.debug 
--gtest_output=xml:build/NULL/unittests.debug/base/debug.test.xml
Running main() from build/googletest/googletest/src/gtest_main.cc
[==] Running 12 tests from 4 test suites.
[--] Global test environment set-up.
[--] 1 test from DebugFlagDeathTest
[ RUN      ] DebugFlagDeathTest.UniqueNames
[      OK ] DebugFlagDeathTest.UniqueNames (1 ms)
[--] 1 test from DebugFlagDeathTest (1 ms total)

[--] 8 tests from DebugFlagTest
[ RUN      ] DebugFlagTest.NameDesc
[      OK ] DebugFlagTest.NameDesc (0 ms)
[ RUN      ] DebugFlagTest.IsFormat
[      OK ] DebugFlagTest.IsFormat (0 ms)
[ RUN      ] DebugFlagTest.ConversionOperator
[      OK ] DebugFlagTest.ConversionOperator (0 ms)
[ RUN      ] DebugFlagTest.FindFlag
[      OK ] DebugFlagTest.FindFlag (0 ms)
[ RUN      ] DebugFlagTest.ChangeFlag
[      OK ] DebugFlagTest.ChangeFlag (0 ms)
[ RUN      ] DebugFlagTest.SetClearDebugFlag
[      OK ] DebugFlagTest.SetClearDebugFlag (0 ms)
[ RUN      ] DebugFlagTest.NoDumpDebugFlags
[      OK ] DebugFlagTest.NoDumpDebugFlags (0 ms)
[ RUN      ] DebugFlagTest.DumpDebugFlags
[      OK ] DebugFlagTest.DumpDebugFlags (0 ms)
[--] 8 tests from DebugFlagTest (0 ms total)

[--] 1 test from DebugSimpleFlagTest
[ RUN      ] DebugSimpleFlagTest.Enabled
[      OK ] DebugSimpleFlagTest.Enabled (0 ms)
[--] 1 test from DebugSimpleFlagTest (0 ms total)

[--] 2 tests from DebugCompoundFlagTest
[ RUN      ] DebugCompoundFlagTest.Enabled
[      OK ] DebugCompoundFlagTest.Enabled (0 ms)
[ RUN      ] DebugCompoundFlagTest.EnabledKids
[      OK ] DebugCompoundFlagTest.EnabledKids (0 ms)
[--] 2 tests from DebugCompoundFlagTest (0 ms total)

[--] Global test environment tear-down
Running main() from build/googletest/googletest/src/gtest_main.cc
[==] Running 8 tests from 1 test suite.
[--] Global test environment set-up.
[==] 12 tests from 4 test suites ran. (1 ms total)
[  PASSED  ] 12 tests.
[--] 8 tests from ByteswapTest
[ RUN      ] ByteswapTest.swap_byte64
[      OK ] ByteswapTest.swap_byte64 (0 ms)
[ RUN      ] ByteswapTest.swap_byte32
[      OK ] ByteswapTest.swap_byte32 (0 ms)
[ RUN      ] ByteswapTest.swap_byte16
[      OK ] ByteswapTest.swap_byte16 (0 ms)
[ RUN      ] ByteswapTest.swap_byte
[      OK ] ByteswapTest.swap_byte (0 ms)
[ RUN      ] ByteswapTest.htog
[      OK ] ByteswapTest.htog (0 ms)
[ RUN      ] ByteswapTest.gtoh
[      OK ] ByteswapTest.gtoh (0 ms)
[ RUN      ] ByteswapTest.betole
[      OK ] ByteswapTest.betole (0 ms)
[ RUN      ] ByteswapTest.letobe
[      OK ] ByteswapTest.letobe (0 ms)
[--] 8 tests from ByteswapTest (21 ms total)

[--] Global test environment tear-down
[==] 8 tests from 1 test suite ran. (23 ms total)
[  PASSED  ] 8 tests.
[      OK ] UncontendedMutex.Lock (213 ms)
[ RUN      ] UncontendedMutex.HeavyContention
build/NULL/sim/guest_abi.test.debug 
--gtest_output=xml:build/NULL/unittests.debug/sim/guest_abi.test.xml

[gem5-dev] Change in gem5/gem5[develop]: base: Fix storage params safe_cast

[Daniel Carvalho (Gerrit) via gem5-dev]

Daniel Carvalho has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/40555 )



Change subject: base: Fix storage params safe_cast
..

base: Fix storage params safe_cast

Although they provide the exact same behavior, the params
created in the tests did not have the type expected by the
internal safe cast.

The following error was triggered:

storage.test.debug: build/NULL/base/cast.hh:47: T safe_cast(U)
 [with T = const Stats::SampleStor::Params*;
  U = const Stats::StorageParams*]:
 Assertion `ret' failed.

Change-Id: I4f2ba51f3ccdb44589e61f235997245e7d9bf3c9
Signed-off-by: Daniel R. Carvalho 
---
M src/base/stats/storage.test.cc
1 file changed, 4 insertions(+), 4 deletions(-)



diff --git a/src/base/stats/storage.test.cc b/src/base/stats/storage.test.cc
index 717c881..8a4f6ed 100644
--- a/src/base/stats/storage.test.cc
+++ b/src/base/stats/storage.test.cc
@@ -1083,7 +1083,7 @@
 Stats::Counter val;
 Stats::DistData data;
 Stats::DistData expected_data;
-Stats::DistParams params(Stats::Deviation);
+Stats::SampleStor::Params params;
 MockInfo info();

 // Simple test with one value being sampled
@@ -1133,7 +1133,7 @@
 Stats::Counter val = 10;
 Stats::Counter num_samples = 5;
 Stats::DistData data;
-Stats::DistParams params(Stats::Deviation);
+Stats::SampleStor::Params params;
 MockInfo info();

 ASSERT_EQ(stor.size(), 1);
@@ -1177,7 +1177,7 @@
 Stats::Counter val;
 Stats::DistData data;
 Stats::DistData expected_data;
-Stats::DistParams params(Stats::Deviation);
+Stats::AvgSampleStor::Params params;
 MockInfo info();

 // Simple test with one value being sampled
@@ -1228,7 +1228,7 @@
 Stats::Counter val = 10;
 Stats::Counter num_samples = 5;
 Stats::DistData data;
-Stats::DistParams params(Stats::Deviation);
+Stats::AvgSampleStor::Params params;
 MockInfo info();

 ASSERT_EQ(stor.size(), 1);

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/40555
To unsubscribe, or for help writing mail filters, visit  
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I4f2ba51f3ccdb44589e61f235997245e7d9bf3c9
Gerrit-Change-Number: 40555
Gerrit-PatchSet: 1
Gerrit-Owner: Daniel Carvalho 
Gerrit-MessageType: newchange
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[gem5-dev] Build failed in Jenkins: Nightly #208

[jenkins-no-reply--- via gem5-dev]

See 

Changes:

[gabe.black] ext: Update pybind11 to version 2.6.2.

[shunhsingou] systemc: remove boost header dependency

[Giacomo Travaglini] ext: testlib loading tests from multiple directories

[Bobby R. Bruce] util,python: Fix Pre-commit hooks to ignore non-source files

[Bobby R. Bruce] util,python: Add check to ensure files are utf-8 in pre-commit

[odanrc] scons: Separate debug flags from debug-format flags

[odanrc] sim: Move cur tick to its own files

[odanrc] base,tests: Add a basic fake class to handle curTick

[odanrc] base: Move Stats::Info functions to its own source file

[odanrc] base,tests: Create unit tests for Stats::Stor

[gabe.black] arch: Templatize the BasicDecodeCache.


--
[...truncated 532.91 KB...]
[--] 4 tests from TypesTest
[ RUN  ] TypesTest.FloatToBits32
[   OK ] TypesTest.FloatToBits32 (0 ms)
[ RUN  ] TypesTest.floatToBits64
[   OK ] TypesTest.floatToBits64 (0 ms)
[ RUN  ] TypesTest.floatsToBitsDoubleInput
[   OK ] TypesTest.floatsToBitsDoubleInput (0 ms)
[ RUN  ] TypesTest.floatsToBitsFloatInput
[   OK ] TypesTest.floatsToBitsFloatInput (0 ms)
[--] 4 tests from TypesTest (0 ms total)

[--] Global test environment tear-down
[==] 19 tests from 3 test suites ran. (6 ms total)
[  PASSED  ] 19 tests.
build/NULL/sim/byteswap.test.debug 
--gtest_output=xml:build/NULL/unittests.debug/sim/byteswap.test.xml
Running main() from build/googletest/googletest/src/gtest_main.cc
[==] Running 2 tests from 1 test suite.
[--] Global test environment set-up.
[--] 2 tests from UncontendedMutex
[ RUN  ] UncontendedMutex.Lock
build/NULL/base/debug.test.debug 
--gtest_output=xml:build/NULL/unittests.debug/base/debug.test.xml
Running main() from build/googletest/googletest/src/gtest_main.cc
[==] Running 12 tests from 4 test suites.
[--] Global test environment set-up.
[--] 1 test from DebugFlagDeathTest
[ RUN  ] DebugFlagDeathTest.UniqueNames
[   OK ] DebugFlagDeathTest.UniqueNames (1 ms)
[--] 1 test from DebugFlagDeathTest (1 ms total)

[--] 8 tests from DebugFlagTest
[ RUN  ] DebugFlagTest.NameDesc
[   OK ] DebugFlagTest.NameDesc (0 ms)
[ RUN  ] DebugFlagTest.IsFormat
[   OK ] DebugFlagTest.IsFormat (0 ms)
[ RUN  ] DebugFlagTest.ConversionOperator
[   OK ] DebugFlagTest.ConversionOperator (0 ms)
[ RUN  ] DebugFlagTest.FindFlag
[   OK ] DebugFlagTest.FindFlag (0 ms)
[ RUN  ] DebugFlagTest.ChangeFlag
[   OK ] DebugFlagTest.ChangeFlag (0 ms)
[ RUN  ] DebugFlagTest.SetClearDebugFlag
[   OK ] DebugFlagTest.SetClearDebugFlag (0 ms)
[ RUN  ] DebugFlagTest.NoDumpDebugFlags
[   OK ] DebugFlagTest.NoDumpDebugFlags (0 ms)
[ RUN  ] DebugFlagTest.DumpDebugFlags
[   OK ] DebugFlagTest.DumpDebugFlags (0 ms)
[--] 8 tests from DebugFlagTest (0 ms total)

[--] 1 test from DebugSimpleFlagTest
[ RUN  ] DebugSimpleFlagTest.Enabled
[   OK ] DebugSimpleFlagTest.Enabled (0 ms)
[--] 1 test from DebugSimpleFlagTest (0 ms total)

[--] 2 tests from DebugCompoundFlagTest
[ RUN  ] DebugCompoundFlagTest.Enabled
[   OK ] DebugCompoundFlagTest.Enabled (0 ms)
[ RUN  ] DebugCompoundFlagTest.EnabledKids
[   OK ] DebugCompoundFlagTest.EnabledKids (0 ms)
[--] 2 tests from DebugCompoundFlagTest (0 ms total)

[--] Global test environment tear-down
Running main() from build/googletest/googletest/src/gtest_main.cc
[==] Running 8 tests from 1 test suite.
[--] Global test environment set-up.
[==] 12 tests from 4 test suites ran. (1 ms total)
[  PASSED  ] 12 tests.
[--] 8 tests from ByteswapTest
[ RUN  ] ByteswapTest.swap_byte64
[   OK ] ByteswapTest.swap_byte64 (0 ms)
[ RUN  ] ByteswapTest.swap_byte32
[   OK ] ByteswapTest.swap_byte32 (0 ms)
[ RUN  ] ByteswapTest.swap_byte16
[   OK ] ByteswapTest.swap_byte16 (0 ms)
[ RUN  ] ByteswapTest.swap_byte
[   OK ] ByteswapTest.swap_byte (0 ms)
[ RUN  ] ByteswapTest.htog
[   OK ] ByteswapTest.htog (0 ms)
[ RUN  ] ByteswapTest.gtoh
[   OK ] ByteswapTest.gtoh (0 ms)
[ RUN  ] ByteswapTest.betole
[   OK ] ByteswapTest.betole (0 ms)
[ RUN  ] ByteswapTest.letobe
[   OK ] ByteswapTest.letobe (0 ms)
[--] 8 tests from ByteswapTest (21 ms total)

[--] Global test environment tear-down
[==] 8 tests from 1 test suite ran. (23 ms total)
[  PASSED  ] 8 tests.
[   OK ] UncontendedMutex.Lock (213 ms)
[ RUN  ] UncontendedMutex.HeavyContention
build/NULL/sim/guest_abi.test.debug 
--gtest_output=xml:build/NULL/unittests.debug/sim/guest_abi.test.xml
build/NULL/sim/proxy_ptr.test.debug 
--gtest_output=xml:build/NULL/unittests.debug/sim/proxy_ptr.test.xml
Running main() from 

[gem5-dev] gem5 v20.1.0.3 Hotfix Release

[Bobby Bruce via gem5-dev]

Dear all,

Last month a bug was identified where booting Linux stalled under certain
circumstances when using the ARM ISA:
https://gem5.atlassian.net/browse/GEM5-901. A fix was found and has been
applied as a new hotfix release to v20.1. We would advise users to pull the
latest gem5 release to avoid any errors.

Special thanks to Adrian Herrera for bringing this bug to our attention and
developing a fix!

Kind regards,
Bobby
--
Dr. Bobby R. Bruce
Room 2235,
Kemper Hall, UC Davis
Davis,
CA, 95616

web: https://www.bobbybruce.net
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[gem5-dev] Change in gem5/gem5[develop]: misc: Merge branch v20.1.0.3 hotfix into develop

[Bobby R. Bruce (Gerrit) via gem5-dev]

Bobby R. Bruce has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/40535 )



Change subject: misc: Merge branch v20.1.0.3 hotfix into develop
..

misc: Merge branch v20.1.0.3 hotfix into develop

Change-Id: I12cca586627718bf41fe24f0fcd3f10c4fe48b2d
---
M src/Doxyfile
M src/arch/arm/system.cc
M src/base/version.cc
4 files changed, 1 insertion(+), 27 deletions(-)



diff --git a/src/Doxyfile b/src/Doxyfile
index 60ca662..ddc3933 100644
--- a/src/Doxyfile
+++ b/src/Doxyfile
@@ -31,11 +31,7 @@
 # This could be handy for archiving the generated documentation or
 # if some version control system is used.

-<<< HEAD   (758011 scons,python: Fix `--without-python` flag)
-PROJECT_NUMBER = DEVELOP-FOR-V20.2
-===
 PROJECT_NUMBER = v20.1.0.3
->>> BRANCH (cd21b5 misc: Updated the RELEASE-NOTES and version number)

 # The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute)
 # base path where the generated documentation will be put.
diff --git a/src/arch/arm/system.cc b/src/arch/arm/system.cc
index 22121e1..783366d 100644
--- a/src/arch/arm/system.cc
+++ b/src/arch/arm/system.cc
@@ -63,7 +63,6 @@
   _genericTimer(nullptr),
   _gic(nullptr),
   _pwrCtrl(nullptr),
-<<< HEAD   (758011 scons,python: Fix `--without-python` flag)
   _highestELIs64(p.highest_el_is_64),
   _physAddrRange64(p.phys_addr_range_64),
   _haveLargeAsid64(p.have_large_asid_64),
@@ -71,30 +70,13 @@
   _haveSVE(p.have_sve),
   _sveVL(p.sve_vl),
   _haveLSE(p.have_lse),
+  _haveVHE(p.have_vhe),
   _havePAN(p.have_pan),
   _haveSecEL2(p.have_secel2),
   semihosting(p.semihosting),
   multiProc(p.multi_proc)
-===
-  _highestELIs64(p->highest_el_is_64),
-  _physAddrRange64(p->phys_addr_range_64),
-  _haveLargeAsid64(p->have_large_asid_64),
-  _haveTME(p->have_tme),
-  _haveSVE(p->have_sve),
-  _sveVL(p->sve_vl),
-  _haveLSE(p->have_lse),
-  _haveVHE(p->have_vhe),
-  _havePAN(p->have_pan),
-  _haveSecEL2(p->have_secel2),
-  semihosting(p->semihosting),
-  multiProc(p->multi_proc)
->>> BRANCH (cd21b5 misc: Updated the RELEASE-NOTES and version number)
 {
-<<< HEAD   (758011 scons,python: Fix `--without-python` flag)
 if (p.auto_reset_addr) {
-===
-  if (p->auto_reset_addr) {
->>> BRANCH (cd21b5 misc: Updated the RELEASE-NOTES and version number)
 _resetAddr = workload->getEntry();
 } else {
 _resetAddr = p.reset_addr;
diff --git a/src/base/version.cc b/src/base/version.cc
index 59554d3..d30ddd1 100644
--- a/src/base/version.cc
+++ b/src/base/version.cc
@@ -29,8 +29,4 @@
 /**
  * @ingroup api_base_utils
  */
-<<< HEAD   (758011 scons,python: Fix `--without-python` flag)
-const char *gem5Version = "[DEVELOP-FOR-V20.2]";
-===
 const char *gem5Version = "20.1.0.3";
->>> BRANCH (cd21b5 misc: Updated the RELEASE-NOTES and version number)

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I12cca586627718bf41fe24f0fcd3f10c4fe48b2d
Gerrit-Change-Number: 40535
Gerrit-PatchSet: 1
Gerrit-Owner: Bobby R. Bruce 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: misc: Revert version info for develop branch

[Bobby R. Bruce (Gerrit) via gem5-dev]

Bobby R. Bruce has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/40536 )



Change subject: misc: Revert version info for develop branch
..

misc: Revert version info for develop branch

Change-Id: Ie01f41cb40b025ef31028bff4d59023e380fcf07
---
M src/Doxyfile
M src/base/version.cc
2 files changed, 2 insertions(+), 2 deletions(-)



diff --git a/src/Doxyfile b/src/Doxyfile
index ddc3933..d453314 100644
--- a/src/Doxyfile
+++ b/src/Doxyfile
@@ -31,7 +31,7 @@
 # This could be handy for archiving the generated documentation or
 # if some version control system is used.

-PROJECT_NUMBER = v20.1.0.3
+PROJECT_NUMBER = DEVELOP-FOR-V20.2

 # The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute)
 # base path where the generated documentation will be put.
diff --git a/src/base/version.cc b/src/base/version.cc
index d30ddd1..cfa98f9 100644
--- a/src/base/version.cc
+++ b/src/base/version.cc
@@ -29,4 +29,4 @@
 /**
  * @ingroup api_base_utils
  */
-const char *gem5Version = "20.1.0.3";
+const char *gem5Version = "[DEVELOP-FOR-V20.2]";

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Gerrit-Change-Id: Ie01f41cb40b025ef31028bff4d59023e380fcf07
Gerrit-Change-Number: 40536
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Gerrit-Owner: Bobby R. Bruce 
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[gem5-dev] Re: Upstreaming power-gem5

[Boris Shingarov via gem5-dev]

> I think I had come across that problem too but I am sure
> that one of my patches will fix that. Probably this one

Yes -- that's what I meant by "commits related to 3dd04381".
So, let's start with this small area.

> Yes, I can submit it via gerrit.
> As a kernel developer, I am more used to mailing list based reviews
> but feel free to let me know what works best for you.

Gerrit is the procedure currently used by the gem5 community.  Even though I 
personally find it non-ideal, it is kind of a given for the foreseeable future, 
and I think the optimal scenario (within the realistic choices) would be if you 
started upstreaming using that procedure.  The other alternative, of which I 
was afraid before I initially wrote to you, would have been if you had 
abandoned the project or had no time/energy to do the rebasing / pushing / 
working with the review, in that case I was thinking about just taking your 
patches and putting them on Gerrit myself but I can see a whole number of 
reasons to avoid this.


-"Sandipan Das"  wrote: -
To: "Boris Shingarov" 
From: "Sandipan Das" 
Date: 02/03/2021 01:30PM
Cc: basava...@nitk.edu.in, "Pratik Rajesh Sampat" , 
"Kajol Jain" , "Gautham R. Shenoy" 
, "gem5 Developer List" 
Subject: Re: [gem5-dev] Re: Upstreaming power-gem5

Hello Boris,

On 03/02/21 2:34 am, Boris Shingarov wrote:
> Hi Sandipan,
> 
>> This makes it possible
>> to run both 32-bit and 64-bit big and little endian PowerPC binaries
>> in SE mode. If its okay with you, we can start by working on trying to
>> get these changes reviewed and merged first.
> 
> Yes, yes!  This aligns very well with both what sequence I think is the most 
> realistic technically, and with my project's priorities.
> 

Great!

>> You can find them here: [develop-power]
> 
> Some of these commits just scream as the perfect first candidates, for 
> example 
> https://urldefense.proofpoint.com/v2/url?u=https-3A__github.com_sandip4n_gem5_commit_3dd0438159d67fe2b5bcc777b43046fdca90f6b9=DwICaQ=sPZ6DeHLiehUHQWKIrsNwWp3t7snrE-az24ztT0w7Jc=ecC5uu6ubGhPt6qQ8xWcSQh1QUJ8B1-CG4B9kRM0nd4=wgWrcP9-wt5oZuq9SWs5UbL4CH93tpVcax1mrsrf0hU=qRcEv2oabPve_Q2GdbmZOqMVBxL32Co3y4ROuJevXDA=
>  and related.  Because right now the Decoder is in a really sad state, 
> crashing even on simple, perfectly valid programs (and that's even within BE, 
> 32-bit SE), see for example 
> https://urldefense.proofpoint.com/v2/url?u=https-3A__gem5.atlassian.net_browse_GEM5-2D819=DwICaQ=sPZ6DeHLiehUHQWKIrsNwWp3t7snrE-az24ztT0w7Jc=ecC5uu6ubGhPt6qQ8xWcSQh1QUJ8B1-CG4B9kRM0nd4=wgWrcP9-wt5oZuq9SWs5UbL4CH93tpVcax1mrsrf0hU=ST81CURwY4zbSASQ6L3PKNAA0FC7ia8-GQTVzzunqEs=.
>   So, how about we start from that one?  How would you like to proceed -- do 
> you want to submit on Gerrit using the regular process a
 nd I will review it?
> 

I think I had come across that problem too but I am sure
that one of my patches will fix that. Probably this one:
https://urldefense.proofpoint.com/v2/url?u=https-3A__github.com_sandip4n_gem5_commit_3b0203e63d892c94fd0e67cfe79f5e6662504c4a=DwICaQ=sPZ6DeHLiehUHQWKIrsNwWp3t7snrE-az24ztT0w7Jc=ecC5uu6ubGhPt6qQ8xWcSQh1QUJ8B1-CG4B9kRM0nd4=wgWrcP9-wt5oZuq9SWs5UbL4CH93tpVcax1mrsrf0hU=GAbuvqL0DsFG6QcbNsVo4liY1x1U2DR8YE0ekWQDYE8=

>> this has been a hobby/side project and hence, the biggest
>> challenge for us has been finding spare cycles
> 
> At my day job at LabWare, I write JIT compilers, and the development 
> technology is centered around simulation -- so I can't draw a bright line 
> where gem5 stops being a "side" project and becomes part of the "main" 
> project because the latter depends on it.  But it does mean that I naturally 
> have more timeslices for some aspects of gem5 than for other aspects.
>>> So, in order for external UARTs like 8250 to be
>> used for console interactions, we currently use some hacks
>> which I am sure are not quite upstreamable
> 
> Yeah, we are in the same boat here.
> I, too, have a long queue of hacks to gem5 which I did just to enable some 
> experiments with the JIT compiler; they've been waiting *years* that I rework 
> them into "real" patches to go upstream -- but that stage of work is very 
> slow and painful labour.
> 

Sounds interesting. I have minimal experience with JIT
compilers having worked on the Linux kernel's in-built
eBPF JIT compilers. Have peeked into Qemu's TCG too.

On that note, are there any plans to add a JIT engine
to gem5? Since gem5 supports checkpoints, uninteresting
parts of a program can be run in JITed mode to speed
things up.

>> The FS mode changes depend on 64-bit support but aside from that,
>> it also needs a fair amount
> 
> What scares me every time I think about FS, is that it will need coordinating 
> across projects/communities (Kernel, OPAL, ...) where I don't have a lot of 
> background in.  Well, let's worry about FS when the time comes.
> 

The folks that I work with here at IBM LTC can assist us
with that. Besides, like we agreed, lets start with SE
mode.


- Sandipan

[gem5-dev] Change in gem5/gem5[develop]: scons,python: Fix `--without-python` flag

[Bobby R. Bruce (Gerrit) via gem5-dev]

Bobby R. Bruce has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39715 )


Change subject: scons,python: Fix `--without-python` flag
..

scons,python: Fix `--without-python` flag

Even with the `--without-python` flag, checks were still done to ensure
the correct version of Python was being used. This commit fixes this so
these checks are not performed when `--without-python` is enabled.

Change-Id: I2242f2971a49ef28cff229ad0337bce0a998413d
Issue-on: https://gem5.atlassian.net/browse/GEM5-880
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39715
Reviewed-by: Gabe Black 
Reviewed-by: Lukas Steiner 
Maintainer: Gabe Black 
Tested-by: kokoro 
---
M SConstruct
M src/SConscript
2 files changed, 32 insertions(+), 25 deletions(-)

Approvals:
  Gabe Black: Looks good to me, approved; Looks good to me, approved
  Lukas Steiner: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/SConstruct b/SConstruct
index 4cf2f10..f744c77 100755
--- a/SConstruct
+++ b/SConstruct
@@ -709,22 +709,25 @@
 if not conf.CheckLib(lib):
 error("Can't find library %s required by python." % lib)

-main.Prepend(CPPPATH=Dir('ext/pybind11/include/'))
-# Bare minimum environment that only includes python
-marshal_env = main.Clone()
-marshal_env.Append(CCFLAGS='$MARSHAL_CCFLAGS_EXTRA')
-marshal_env.Append(LINKFLAGS='$MARSHAL_LDFLAGS_EXTRA')
-py_version = conf.CheckPythonLib()
-if not py_version:
-error("Can't find a working Python installation")
+main.Prepend(CPPPATH=Dir('ext/pybind11/include/'))

-# Found a working Python installation. Check if it meets minimum
-# requirements.
-if py_version[0] < 3 or \
-   (py_version[0] == 3 and py_version[1] < 6):
-error('Python version too old. Version 3.6 or newer is required.')
-elif py_version[0] > 3:
-warning('Python version too new. Python 3 expected.')
+marshal_env = main.Clone()
+
+# Bare minimum environment that only includes python
+marshal_env.Append(CCFLAGS='$MARSHAL_CCFLAGS_EXTRA')
+marshal_env.Append(LINKFLAGS='$MARSHAL_LDFLAGS_EXTRA')
+
+py_version = conf.CheckPythonLib()
+if not py_version:
+error("Can't find a working Python installation")
+
+# Found a working Python installation. Check if it meets minimum
+# requirements.
+if py_version[0] < 3 or \
+(py_version[0] == 3 and py_version[1] < 6):
+error('Python version too old. Version 3.6 or newer is required.')
+elif py_version[0] > 3:
+warning('Python version too new. Python 3 expected.')

 # On Solaris you need to use libsocket for socket ops
 if not  
conf.CheckLibWithHeader(None, 'sys/socket.h', 'C++', 'accept(0,0,0);'):

@@ -1271,10 +1274,13 @@
 env.Append(CCFLAGS='$CCFLAGS_EXTRA')
 env.Append(LINKFLAGS='$LDFLAGS_EXTRA')

+exports=['env']
+if main['USE_PYTHON']:
+exports.append('marshal_env')
+
 # The src/SConscript file sets up the build rules in 'env' according
 # to the configured variables.  It returns a list of environments,
 # one for each variant build (debug, opt, etc.)
-SConscript('src/SConscript', variant_dir=variant_path,
-   exports=['env', 'marshal_env'])
+SConscript('src/SConscript', variant_dir=variant_path, exports=exports)

 atexit.register(summarize_warnings)
diff --git a/src/SConscript b/src/SConscript
index 81a1b4d..74b9516 100644
--- a/src/SConscript
+++ b/src/SConscript
@@ -1208,11 +1208,6 @@
Transform("VER TAGS")))
 env.AlwaysBuild(tags)

-# Build a small helper that marshals the Python code using the same
-# version of Python as gem5. This is in an unorthodox location to
-# avoid building it for every variant.
-py_marshal = marshal_env.Program('marshal', 'python/marshal.cc')[0]
-
 # Embed python files.  All .py files that have been indicated by a
 # PySource() call in a SConscript need to be embedded into the M5
 # library.  To do that, we compile the file to byte code, marshal the
@@ -1266,10 +1261,16 @@
 ''')
 code.write(str(target[0]))

-for source in PySource.all:
-marshal_env.Command(source.cpp, [ py_marshal, source.tnode ],
+if main['USE_PYTHON']:
+# Build a small helper that marshals the Python code using the same
+# version of Python as gem5. This is in an unorthodox location to
+# avoid building it for every variant.
+py_marshal = marshal_env.Program('marshal', 'python/marshal.cc')[0]
+
+for source in PySource.all:
+marshal_env.Command(source.cpp, [ py_marshal, source.tnode ],
 MakeAction(embedPyFile, Transform("EMBED PY")))
-Source(source.cpp, tags=source.tags, add_tags='python')
+Source(source.cpp, tags=source.tags, add_tags='python')

 
 #

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[gem5-dev] Change in gem5/gem5[hotfix-feat-vhe-fix]: misc: Updated the RELEASE-NOTES and version number

[Bobby R. Bruce (Gerrit) via gem5-dev]

Bobby R. Bruce has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/40435 )


Change subject: misc: Updated the RELEASE-NOTES and version number
..

misc: Updated the RELEASE-NOTES and version number

Updated the RELEASE-NOTES.md and version number for the v20.1.0.3
hotfix release.

Change-Id: I95ab84ea259f5e0529ebaa32be65d9a14370f219
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40435
Reviewed-by: Bobby R. Bruce 
Reviewed-by: Jason Lowe-Power 
Maintainer: Bobby R. Bruce 
Tested-by: kokoro 
---
M RELEASE-NOTES.md
M src/Doxyfile
M src/base/version.cc
3 files changed, 7 insertions(+), 2 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/RELEASE-NOTES.md b/RELEASE-NOTES.md
index 71934a7..c84d9b4 100644
--- a/RELEASE-NOTES.md
+++ b/RELEASE-NOTES.md
@@ -1,3 +1,8 @@
+# Version 20.1.0.3
+
+**[HOTFIX]** A patch was apply to fix an [error where booting Linux  
stalled when using the ARM ISA](https://gem5.atlassian.net/browse/GEM5-901).
+This fix adds the parameter `have_vhe` to enable FEAT_VHE on demand, and  
is disabled by default to resolve this issue.

+
 # Version 20.1.0.2

 **[HOTFIX]** This hotfix release fixes known two bugs:
diff --git a/src/Doxyfile b/src/Doxyfile
index b934639..ddc3933 100644
--- a/src/Doxyfile
+++ b/src/Doxyfile
@@ -31,7 +31,7 @@
 # This could be handy for archiving the generated documentation or
 # if some version control system is used.

-PROJECT_NUMBER = v20.1.0.2
+PROJECT_NUMBER = v20.1.0.3

 # The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute)
 # base path where the generated documentation will be put.
diff --git a/src/base/version.cc b/src/base/version.cc
index 304ccc1..d30ddd1 100644
--- a/src/base/version.cc
+++ b/src/base/version.cc
@@ -29,4 +29,4 @@
 /**
  * @ingroup api_base_utils
  */
-const char *gem5Version = "20.1.0.2";
+const char *gem5Version = "20.1.0.3";

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Gerrit-Project: public/gem5
Gerrit-Branch: hotfix-feat-vhe-fix
Gerrit-Change-Id: I95ab84ea259f5e0529ebaa32be65d9a14370f219
Gerrit-Change-Number: 40435
Gerrit-PatchSet: 2
Gerrit-Owner: Bobby R. Bruce 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: gpu-compute,misc: Fix Clang missing override errors

[Bobby R. Bruce (Gerrit) via gem5-dev]

Bobby R. Bruce has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/40396 )


Change subject: gpu-compute,misc: Fix Clang missing override errors
..

gpu-compute,misc: Fix Clang missing override errors

Clang fails to compile GCN3 due to missing overrides in
`src/gpu-compute/gpu_command_processor.hh`. This commit fixes this
errror.

Change-Id: I6da9fce7c3eb86a5418a931ee4f225cceda488a5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40396
Reviewed-by: Jason Lowe-Power 
Reviewed-by: Matt Sinclair 
Maintainer: Jason Lowe-Power 
Maintainer: Matt Sinclair 
Tested-by: kokoro 
---
M src/gpu-compute/gpu_command_processor.hh
1 file changed, 1 insertion(+), 1 deletion(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  Matt Sinclair: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/gpu-compute/gpu_command_processor.hh  
b/src/gpu-compute/gpu_command_processor.hh

index 8f6bfe2..ebdf9ae 100644
--- a/src/gpu-compute/gpu_command_processor.hh
+++ b/src/gpu-compute/gpu_command_processor.hh
@@ -87,7 +87,7 @@

 void updateHsaSignal(Addr signal_handle, uint64_t signal_value)  
override;


-uint64_t functionalReadHsaSignal(Addr signal_handle);
+uint64_t functionalReadHsaSignal(Addr signal_handle) override;

 Addr getHsaSignalValueAddr(Addr signal_handle)
 {

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I6da9fce7c3eb86a5418a931ee4f225cceda488a5
Gerrit-Change-Number: 40396
Gerrit-PatchSet: 2
Gerrit-Owner: Bobby R. Bruce 
Gerrit-Reviewer: Alexandru Duțu 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Matt Sinclair 
Gerrit-Reviewer: Matthew Poremba 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv,misc: Fix clang missing override errors

[Bobby R. Bruce (Gerrit) via gem5-dev]

Bobby R. Bruce has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/40395 )


Change subject: arch-riscv,misc: Fix clang missing override errors
..

arch-riscv,misc: Fix clang missing override errors

Clang 9 failed to compile RISC-V due to missing overrides in
`src/arch/riscv/remote_gdb.hh`. This commit adds these missing
overrides.

Change-Id: Id0bfc371ca3e3e1b91e9112a837e1862072bf9d2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40395
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/arch/riscv/remote_gdb.hh
1 file changed, 3 insertions(+), 2 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/riscv/remote_gdb.hh b/src/arch/riscv/remote_gdb.hh
index 545a43c..d66c30d 100644
--- a/src/arch/riscv/remote_gdb.hh
+++ b/src/arch/riscv/remote_gdb.hh
@@ -147,14 +147,15 @@
  * GDB then queries for xml blobs using qXfer:features:read:xxx.xml
  */
 std::vector
-availableFeatures() const
+availableFeatures() const override
 {
 return {"qXfer:features:read+"};
 };
 /**
  * Reply to qXfer:features:read:xxx.xml qeuries
  */
-bool getXferFeaturesRead(const std::string , std::string  
);

+bool getXferFeaturesRead(const std::string ,
+ std::string ) override;
 };

 } // namespace RiscvISA

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Gerrit-Branch: develop
Gerrit-Change-Id: Id0bfc371ca3e3e1b91e9112a837e1862072bf9d2
Gerrit-Change-Number: 40395
Gerrit-PatchSet: 2
Gerrit-Owner: Bobby R. Bruce 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: gpu-compute,misc: Remove unused private variable

[Bobby R. Bruce (Gerrit) via gem5-dev]

Bobby R. Bruce has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/40397 )


Change subject: gpu-compute,misc: Remove unused private variable
..

gpu-compute,misc: Remove unused private variable

Clang 9 fails to compile GCN3 due to the unused private variable,
`_nxtFreeIdx`, in `src/gpu-compute/dyn_pool_manager.hh`. This variable
has therefore been removed.

Change-Id: I33f2e9634bbf8d5cea7a42ae2ac9f3ea8298d406
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40397
Reviewed-by: Matt Sinclair 
Maintainer: Matt Sinclair 
Tested-by: kokoro 
---
M src/gpu-compute/dyn_pool_manager.hh
1 file changed, 1 insertion(+), 3 deletions(-)

Approvals:
  Matt Sinclair: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/gpu-compute/dyn_pool_manager.hh  
b/src/gpu-compute/dyn_pool_manager.hh

index dc8ffec..151a33f 100644
--- a/src/gpu-compute/dyn_pool_manager.hh
+++ b/src/gpu-compute/dyn_pool_manager.hh
@@ -46,7 +46,7 @@
 {
   public:
 DynPoolManager(const PoolManagerParams )
-: PoolManager(p), _regionSize(0), _nxtFreeIdx(0)
+: PoolManager(p), _regionSize(0)
 {
 _totRegSpaceAvailable = p.pool_size;
 }
@@ -63,8 +63,6 @@
 // actual size of a region (normalized to the minimum size that can
 // be reserved)
 uint32_t _regionSize;
-// next index to allocate a region
-int _nxtFreeIdx;
 // total registers available - across chunks
 uint32_t _totRegSpaceAvailable;
 // regIndex and freeSpace record

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Gerrit-Change-Id: I33f2e9634bbf8d5cea7a42ae2ac9f3ea8298d406
Gerrit-Change-Number: 40397
Gerrit-PatchSet: 2
Gerrit-Owner: Bobby R. Bruce 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Matt Sinclair 
Gerrit-Reviewer: Matthew Poremba 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: tests: Increase presubmit (Kokoro) timeout to 6 hours

[Bobby R. Bruce (Gerrit) via gem5-dev]

Bobby R. Bruce has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/40455 )


Change subject: tests: Increase presubmit (Kokoro) timeout to 6 hours
..

tests: Increase presubmit (Kokoro) timeout to 6 hours

Kokoro is now frequnetly timing out. This will increase the timeout from
5 hours to 6 hours.

Change-Id: I2124567142358ab183d962fcbd73ee9ea4e809a3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40455
Reviewed-by: Jason Lowe-Power 
Reviewed-by: Gabe Black 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M tests/jenkins/presubmit.cfg
1 file changed, 1 insertion(+), 1 deletion(-)

Approvals:
  Jason Lowe-Power: Looks good to me, but someone else must approve; Looks  
good to me, approved

  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/tests/jenkins/presubmit.cfg b/tests/jenkins/presubmit.cfg
index 76bdb04..a356c76 100644
--- a/tests/jenkins/presubmit.cfg
+++ b/tests/jenkins/presubmit.cfg
@@ -3,4 +3,4 @@
 # Location of the continuous batch script in repository.
 build_file: "jenkins-gem5-prod/tests/jenkins/presubmit.sh"

-timeout_mins: 300 # 5 hours
+timeout_mins: 360 # 6 hours

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I2124567142358ab183d962fcbd73ee9ea4e809a3
Gerrit-Change-Number: 40455
Gerrit-PatchSet: 2
Gerrit-Owner: Bobby R. Bruce 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-CC: Matt Sinclair 
Gerrit-MessageType: merged
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[gem5-dev] Re: Upstreaming power-gem5

[Sandipan Das via gem5-dev]

On 03/02/21 11:59 pm, Sandipan Das wrote:
> Hello Boris,
> 
> On 03/02/21 2:34 am, Boris Shingarov wrote:
>> Hi Sandipan,
>>
>>> This makes it possible
>>> to run both 32-bit and 64-bit big and little endian PowerPC binaries
>>> in SE mode. If its okay with you, we can start by working on trying to
>>> get these changes reviewed and merged first.
>>
>> Yes, yes!  This aligns very well with both what sequence I think is the most 
>> realistic technically, and with my project's priorities.
>>
> 
> Great!
> 
>>> You can find them here: [develop-power]
>>
>> Some of these commits just scream as the perfect first candidates, for 
>> example 
>> https://github.com/sandip4n/gem5/commit/3dd0438159d67fe2b5bcc777b43046fdca90f6b9
>>  and related.  Because right now the Decoder is in a really sad state, 
>> crashing even on simple, perfectly valid programs (and that's even within 
>> BE, 32-bit SE), see for example https://gem5.atlassian.net/browse/GEM5-819.  
>> So, how about we start from that one?  How would you like to proceed -- do 
>> you want to submit on Gerrit using the regular process and I will review it?
>>
> 
> I think I had come across that problem too but I am sure
> that one of my patches will fix that. Probably this one:
> https://github.com/sandip4n/gem5/commit/3b0203e63d892c94fd0e67cfe79f5e6662504c4a
> 

Sorry I missed the other question. Yes, I can submit it via gerrit.
As a kernel developer, I am more used to mailing list based reviews
but feel free to let me know what works best for you.

That reminds me, I'll also need to rebase my code against the latest
"develop" branch.


- Sandipan
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[gem5-dev] Re: Upstreaming power-gem5

[Sandipan Das via gem5-dev]

Hello Boris,

On 03/02/21 2:34 am, Boris Shingarov wrote:
> Hi Sandipan,
> 
>> This makes it possible
>> to run both 32-bit and 64-bit big and little endian PowerPC binaries
>> in SE mode. If its okay with you, we can start by working on trying to
>> get these changes reviewed and merged first.
> 
> Yes, yes!  This aligns very well with both what sequence I think is the most 
> realistic technically, and with my project's priorities.
> 

Great!

>> You can find them here: [develop-power]
> 
> Some of these commits just scream as the perfect first candidates, for 
> example 
> https://github.com/sandip4n/gem5/commit/3dd0438159d67fe2b5bcc777b43046fdca90f6b9
>  and related.  Because right now the Decoder is in a really sad state, 
> crashing even on simple, perfectly valid programs (and that's even within BE, 
> 32-bit SE), see for example https://gem5.atlassian.net/browse/GEM5-819.  So, 
> how about we start from that one?  How would you like to proceed -- do you 
> want to submit on Gerrit using the regular process and I will review it?
> 

I think I had come across that problem too but I am sure
that one of my patches will fix that. Probably this one:
https://github.com/sandip4n/gem5/commit/3b0203e63d892c94fd0e67cfe79f5e6662504c4a

>> this has been a hobby/side project and hence, the biggest
>> challenge for us has been finding spare cycles
> 
> At my day job at LabWare, I write JIT compilers, and the development 
> technology is centered around simulation -- so I can't draw a bright line 
> where gem5 stops being a "side" project and becomes part of the "main" 
> project because the latter depends on it.  But it does mean that I naturally 
> have more timeslices for some aspects of gem5 than for other aspects.
>>> So, in order for external UARTs like 8250 to be
>> used for console interactions, we currently use some hacks
>> which I am sure are not quite upstreamable
> 
> Yeah, we are in the same boat here.
> I, too, have a long queue of hacks to gem5 which I did just to enable some 
> experiments with the JIT compiler; they've been waiting *years* that I rework 
> them into "real" patches to go upstream -- but that stage of work is very 
> slow and painful labour.
> 

Sounds interesting. I have minimal experience with JIT
compilers having worked on the Linux kernel's in-built
eBPF JIT compilers. Have peeked into Qemu's TCG too.

On that note, are there any plans to add a JIT engine
to gem5? Since gem5 supports checkpoints, uninteresting
parts of a program can be run in JITed mode to speed
things up.

>> The FS mode changes depend on 64-bit support but aside from that,
>> it also needs a fair amount
> 
> What scares me every time I think about FS, is that it will need coordinating 
> across projects/communities (Kernel, OPAL, ...) where I don't have a lot of 
> background in.  Well, let's worry about FS when the time comes.
> 

The folks that I work with here at IBM LTC can assist us
with that. Besides, like we agreed, lets start with SE
mode.


- Sandipan
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Add destRegIdxArr arrays to TME instructions

[Giacomo Travaglini (Gerrit) via gem5-dev]

Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/40375 )


Change subject: arch-arm: Add destRegIdxArr arrays to TME instructions
..

arch-arm: Add destRegIdxArr arrays to TME instructions

This is needed as the base StaticInst class is no longer holding the
index array and it is up to the derived class to allocate the
storage depending on the number of registers used

Change-Id: I389e39a7e09d31f370d63a6e61fe6ee3faaac7db
Signed-off-by: Giacomo Travaglini 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40375
Reviewed-by: Gabe Black 
Tested-by: kokoro 
---
M src/arch/arm/insts/tme64.cc
M src/arch/arm/insts/tme64.hh
2 files changed, 20 insertions(+), 2 deletions(-)

Approvals:
  Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
  Gabe Black: Looks good to me, but someone else must approve
  kokoro: Regressions pass



diff --git a/src/arch/arm/insts/tme64.cc b/src/arch/arm/insts/tme64.cc
index d32e8c9..85ffd6d 100644
--- a/src/arch/arm/insts/tme64.cc
+++ b/src/arch/arm/insts/tme64.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020 ARM Limited
+ * Copyright (c) 2020-2021 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -116,6 +116,12 @@
 Tstart64::Tstart64(ExtMachInst machInst, IntRegIndex _dest)
 : TmeRegNone64("tstart", machInst, MemReadOp, _dest)
 {
+setRegIdxArrays(
+nullptr,
+reinterpret_cast(
+::remove_pointer_t::destRegIdxArr));
+;
+
 _numSrcRegs = 0;
 _numDestRegs = 0;
 _numFPDestRegs = 0;
@@ -144,6 +150,12 @@
 Ttest64::Ttest64(ExtMachInst machInst, IntRegIndex _dest)
 : TmeRegNone64("ttest", machInst, MemReadOp, _dest)
 {
+setRegIdxArrays(
+nullptr,
+reinterpret_cast(
+::remove_pointer_t::destRegIdxArr));
+;
+
 _numSrcRegs = 0;
 _numDestRegs = 0;
 _numFPDestRegs = 0;
diff --git a/src/arch/arm/insts/tme64.hh b/src/arch/arm/insts/tme64.hh
index b75adc1..0a1e02c 100644
--- a/src/arch/arm/insts/tme64.hh
+++ b/src/arch/arm/insts/tme64.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020 ARM Limited
+ * Copyright (c) 2020-2021 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -97,6 +97,9 @@

 class Tstart64 : public TmeRegNone64
 {
+  private:
+RegId destRegIdxArr[1];
+
   public:
 Tstart64(ArmISA::ExtMachInst, ArmISA::IntRegIndex);

@@ -107,6 +110,9 @@

 class Ttest64 : public TmeRegNone64
 {
+  private:
+RegId destRegIdxArr[1];
+
   public:
 Ttest64(ArmISA::ExtMachInst, ArmISA::IntRegIndex);


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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I389e39a7e09d31f370d63a6e61fe6ee3faaac7db
Gerrit-Change-Number: 40375
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: misc: Re-remove Authors lines from source files.

[Gabe Black (Gerrit) via gem5-dev]

Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/40335 )


Change subject: misc: Re-remove Authors lines from source files.
..

misc: Re-remove Authors lines from source files.

These were universally removed a while ago, but a bunch have crept back
in. Remove them.

Change-Id: I3cb5b9f40c9c19aafb5e39a51d1baeae60a591c0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40335
Tested-by: kokoro 
Reviewed-by: Daniel Carvalho 
Reviewed-by: Matthew Poremba 
Maintainer: Gabe Black 
---
M configs/nvm/sweep.py
M configs/nvm/sweep_hybrid.py
M src/arch/gcn3/SConscript
M src/arch/gcn3/SConsopts
M src/arch/gcn3/decoder.cc
M src/arch/gcn3/gpu_decoder.hh
M src/arch/gcn3/gpu_isa.hh
M src/arch/gcn3/gpu_mem_helpers.hh
M src/arch/gcn3/gpu_types.hh
M src/arch/gcn3/insts/gpu_static_inst.cc
M src/arch/gcn3/insts/gpu_static_inst.hh
M src/arch/gcn3/insts/inst_util.hh
M src/arch/gcn3/insts/instructions.cc
M src/arch/gcn3/insts/instructions.hh
M src/arch/gcn3/insts/op_encodings.cc
M src/arch/gcn3/insts/op_encodings.hh
M src/arch/gcn3/isa.cc
M src/arch/gcn3/operand.hh
M src/arch/gcn3/registers.cc
M src/arch/gcn3/registers.hh
M src/cpu/testers/traffic_gen/hybrid_gen.cc
M src/cpu/testers/traffic_gen/hybrid_gen.hh
M src/cpu/testers/traffic_gen/nvm_gen.cc
M src/cpu/testers/traffic_gen/nvm_gen.hh
M src/dev/hsa/HSADevice.py
M src/dev/hsa/HSADriver.py
M src/dev/hsa/SConscript
M src/dev/hsa/hsa_device.cc
M src/dev/hsa/hsa_device.hh
M src/dev/hsa/hsa_driver.cc
M src/dev/hsa/hsa_driver.hh
M src/dev/hsa/hsa_packet.hh
M src/dev/hsa/hsa_packet_processor.cc
M src/dev/hsa/hsa_packet_processor.hh
M src/dev/hsa/hsa_queue.hh
M src/dev/hsa/hw_scheduler.cc
M src/dev/hsa/hw_scheduler.hh
M src/gpu-compute/comm.cc
M src/gpu-compute/comm.hh
M src/gpu-compute/gpu_command_processor.cc
M src/gpu-compute/gpu_command_processor.hh
M src/gpu-compute/gpu_compute_driver.cc
M src/gpu-compute/gpu_compute_driver.hh
M src/gpu-compute/hsa_queue_entry.hh
M src/gpu-compute/kernel_code.hh
M src/gpu-compute/register_file.cc
M src/gpu-compute/register_file.hh
M src/gpu-compute/register_manager.hh
M src/gpu-compute/register_manager_policy.hh
M src/gpu-compute/scalar_memory_pipeline.cc
M src/gpu-compute/scalar_memory_pipeline.hh
M src/gpu-compute/scalar_register_file.cc
M src/gpu-compute/scalar_register_file.hh
M src/gpu-compute/shader.hh
M src/gpu-compute/static_register_manager_policy.cc
M src/gpu-compute/static_register_manager_policy.hh
M src/mem/DRAMsim3.py
M src/mem/dramsim3.cc
M src/mem/ruby/network/garnet/NetworkBridge.cc
M src/mem/ruby/network/garnet/NetworkBridge.hh
M src/mem/slicc/ast/DeferEnqueueingStatementAST.py
M src/mem/token_port.cc
62 files changed, 0 insertions(+), 143 deletions(-)

Approvals:
  Matthew Poremba: Looks good to me, approved
  Daniel Carvalho: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/configs/nvm/sweep.py b/configs/nvm/sweep.py
index 8dc137a..7ae8ded 100644
--- a/configs/nvm/sweep.py
+++ b/configs/nvm/sweep.py
@@ -32,8 +32,6 @@
 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Andreas Hansson

 import math
 import optparse
diff --git a/configs/nvm/sweep_hybrid.py b/configs/nvm/sweep_hybrid.py
index b7901cc..d2f51dd 100644
--- a/configs/nvm/sweep_hybrid.py
+++ b/configs/nvm/sweep_hybrid.py
@@ -32,8 +32,6 @@
 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Andreas Hansson

 import math
 import optparse
diff --git a/src/arch/gcn3/SConscript b/src/arch/gcn3/SConscript
index da57bf5..61c93c3 100644
--- a/src/arch/gcn3/SConscript
+++ b/src/arch/gcn3/SConscript
@@ -30,8 +30,6 @@
 # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF  
THE

 # POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Anthony Gutierrez

 import sys

diff --git a/src/arch/gcn3/SConsopts b/src/arch/gcn3/SConsopts
index b6bcc39..92bde97 100644
--- a/src/arch/gcn3/SConsopts
+++ b/src/arch/gcn3/SConsopts
@@ -30,8 +30,6 @@
 # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF  
THE

 # POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Anthony Gutierrez

 Import('*')

diff --git a/src/arch/gcn3/decoder.cc b/src/arch/gcn3/decoder.cc
index 87578f9..7062325 100644
--- a/src/arch/gcn3/decoder.cc
+++ b/src/arch/gcn3/decoder.cc
@@ -29,9 +29,6 @@
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS 

[gem5-dev] Change in gem5/gem5[develop]: scons: Add an "All" compound debug flag

[Daniel Carvalho (Gerrit) via gem5-dev]

Daniel Carvalho has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39077 )


Change subject: scons: Add an "All" compound debug flag
..

scons: Add an "All" compound debug flag

Add an "All" compound debug flag, which encapsulates all
debug flags.

Since this is the broadest compound flag, allowing users
to include it would imply in extremely generic includes.
Moreover, it is highly unlikely that any correct C++ code
would ever use all debug flags. Therefore, a header file
for this flag is not generated to force users to directly
include only the debug flags they need.

Change-Id: If40f2f708be1495fa2b2380266164d5d44d7cffa
Signed-off-by: Daniel R. Carvalho 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39077
Tested-by: kokoro 
Reviewed-by: Nathanael Premillieu 
Maintainer: Bobby R. Bruce 
---
M src/SConscript
M src/python/m5/debug.py
2 files changed, 20 insertions(+), 1 deletion(-)

Approvals:
  Nathanael Premillieu: Looks good to me, approved
  Bobby R. Bruce: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/SConscript b/src/SConscript
index 6637b1f..81a1b4d 100644
--- a/src/SConscript
+++ b/src/SConscript
@@ -633,6 +633,19 @@
 def DebugFormatFlag(name, desc=None):
 DebugFlag(name, desc, True)

+# Create a compound debug flag that encapsulates all flags: "All". This
+# flag should not be used within C++ code - it is a compound meta flag
+def _createAllDebugFlag():
+simple_flags = []
+for name,flag in sorted(debug_flags.items()):
+n, compound, desc, fmt = flag
+assert n == name
+if not compound and not fmt:
+simple_flags.append(n)
+
+CompoundFlag("All", simple_flags,
+"Controls all debug flags. It should not be used within C++ code.")
+
 Export('DebugFlag')
 Export('CompoundFlag')
 Export('DebugFormatFlag')
@@ -1174,6 +1187,8 @@

 code.write(str(target[0]))

+# Generate the files for the debug and debug-format flags
+_createAllDebugFlag()
 for name,flag in sorted(debug_flags.items()):
 n, compound, desc, fmt = flag
 assert n == name
diff --git a/src/python/m5/debug.py b/src/python/m5/debug.py
index fbcb624..d808850 100644
--- a/src/python/m5/debug.py
+++ b/src/python/m5/debug.py
@@ -43,7 +43,11 @@
 for name, flag in filter(lambda kv: isinstance(kv[1], CompoundFlag),
  sorted_flags):
 print("%s: %s" % (name, flag.desc))
-printList([ c.name for c in flag.kids() ], indent=8)
+# The list of kids for flag "All" is too long, so it is not printed
+if name != "All":
+printList([ c.name for c in flag.kids() ], indent=8)
+else:
+print("All Base Flags")
 print()
 print("Formatting Flags:")
 for name, flag in filter(lambda kv: isinstance(kv[1], SimpleFlag)



The change was submitted with unreviewed changes in the following files:

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: If40f2f708be1495fa2b2380266164d5d44d7cffa
Gerrit-Change-Number: 39077
Gerrit-PatchSet: 7
Gerrit-Owner: Daniel Carvalho 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Nathanael Premillieu 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch,sim: Use VPtr<> instead of Addr in system call signatures.

[Gabe Black (Gerrit) via gem5-dev]

Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/40498 )



Change subject: arch,sim: Use VPtr<> instead of Addr in system call  
signatures.

..

arch,sim: Use VPtr<> instead of Addr in system call signatures.

This tells the GuestABI mechanism that these are guest pointers and not
uint64_ts, and that they should be treated as 32 bit or 64 bit values
depending on the size of pointers in the target ABI.

Change-Id: Ia9b5447848c52668a975d8b07b11ad457e756b13
---
M src/arch/arm/freebsd/se_workload.cc
M src/arch/mips/linux/se_workload.cc
M src/arch/sparc/linux/syscalls.cc
M src/sim/syscall_emul.cc
M src/sim/syscall_emul.hh
5 files changed, 120 insertions(+), 112 deletions(-)



diff --git a/src/arch/arm/freebsd/se_workload.cc  
b/src/arch/arm/freebsd/se_workload.cc

index ab6b03e..661a4a9 100644
--- a/src/arch/arm/freebsd/se_workload.cc
+++ b/src/arch/arm/freebsd/se_workload.cc
@@ -83,8 +83,8 @@

 #if !defined ( __GNU_LIBRARY__ )
 static SyscallReturn
-sysctlFunc(SyscallDesc *desc, ThreadContext *tc, Addr namep, size_t  
nameLen,

-   Addr oldp, Addr oldlenp, Addr newp, size_t newlen)
+sysctlFunc(SyscallDesc *desc, ThreadContext *tc, VPtr<> namep, size_t  
nameLen,

+   VPtr<> oldp, VPtr<> oldlenp, VPtr<> newp, size_t newlen)
 {
 uint64_t ret;

diff --git a/src/arch/mips/linux/se_workload.cc  
b/src/arch/mips/linux/se_workload.cc

index 0abe263..ef12f4f 100644
--- a/src/arch/mips/linux/se_workload.cc
+++ b/src/arch/mips/linux/se_workload.cc
@@ -124,7 +124,7 @@
 /// Target sys_setsysinfo() handler.
 static SyscallReturn
 sys_setsysinfoFunc(SyscallDesc *desc, ThreadContext *tc, unsigned op,
-   Addr bufPtr, unsigned nbytes)
+   VPtr<> bufPtr, unsigned nbytes)
 {
 switch (op) {

@@ -147,7 +147,7 @@
 }

 static SyscallReturn
-setThreadAreaFunc(SyscallDesc *desc, ThreadContext *tc, Addr addr)
+setThreadAreaFunc(SyscallDesc *desc, ThreadContext *tc, VPtr<> addr)
 {
 tc->setMiscRegNoEffect(MISCREG_TP_VALUE, addr);
 return 0;
diff --git a/src/arch/sparc/linux/syscalls.cc  
b/src/arch/sparc/linux/syscalls.cc

index a00f60e..17cc705 100644
--- a/src/arch/sparc/linux/syscalls.cc
+++ b/src/arch/sparc/linux/syscalls.cc
@@ -54,7 +54,7 @@

 static SyscallReturn
 getresuidFunc(SyscallDesc *desc, ThreadContext *tc,
-  Addr ruid, Addr euid, Addr suid)
+  VPtr<> ruid, VPtr<> euid, VPtr<> suid)
 {
 const uint64_t id = htobe(100);
 // Handle the EFAULT case
diff --git a/src/sim/syscall_emul.cc b/src/sim/syscall_emul.cc
index 8f04cd5..4f6716b 100644
--- a/src/sim/syscall_emul.cc
+++ b/src/sim/syscall_emul.cc
@@ -89,7 +89,7 @@
 }

 static void
-exitFutexWake(ThreadContext *tc, Addr addr, uint64_t tgid)
+exitFutexWake(ThreadContext *tc, VPtr<> addr, uint64_t tgid)
 {
 // Clear value at address pointed to by thread's childClearTID field.
 BufferArg ctidBuf(addr, sizeof(long));
@@ -243,7 +243,7 @@


 SyscallReturn
-brkFunc(SyscallDesc *desc, ThreadContext *tc, Addr new_brk)
+brkFunc(SyscallDesc *desc, ThreadContext *tc, VPtr<> new_brk)
 {
 // change brk addr to first arg
 auto p = tc->getProcessPtr();
@@ -300,7 +300,7 @@
 SyscallReturn
 _llseekFunc(SyscallDesc *desc, ThreadContext *tc,
 int tgt_fd, uint64_t offset_high, uint32_t offset_low,
-Addr result_ptr, int whence)
+VPtr<> result_ptr, int whence)
 {
 auto p = tc->getProcessPtr();

@@ -325,7 +325,7 @@


 SyscallReturn
-munmapFunc(SyscallDesc *desc, ThreadContext *tc, Addr start, size_t length)
+munmapFunc(SyscallDesc *desc, ThreadContext *tc, VPtr<> start, size_t  
length)

 {
 // Even if the system is currently not capable of recycling physical
 // pages, there is no reason we can't unmap them so that we trigger
@@ -348,7 +348,7 @@

 SyscallReturn
 gethostnameFunc(SyscallDesc *desc, ThreadContext *tc,
-Addr buf_ptr, int name_len)
+VPtr<> buf_ptr, int name_len)
 {
 BufferArg name(buf_ptr, name_len);
 strncpy((char *)name.bufferPtr(), hostname, name_len);
@@ -358,7 +358,7 @@

 SyscallReturn
 getcwdFunc(SyscallDesc *desc, ThreadContext *tc,
-   Addr buf_ptr, unsigned long size)
+   VPtr<> buf_ptr, unsigned long size)
 {
 int result = 0;
 auto p = tc->getProcessPtr();
@@ -388,7 +388,7 @@

 SyscallReturn
 readlinkFunc(SyscallDesc *desc, ThreadContext *tc,
- Addr pathname, Addr buf_ptr, size_t bufsiz)
+ VPtr<> pathname, VPtr<> buf_ptr, size_t bufsiz)
 {
 std::string path;
 auto p = tc->getProcessPtr();
@@ -445,7 +445,7 @@
 }

 SyscallReturn
-unlinkFunc(SyscallDesc *desc, ThreadContext *tc, Addr pathname)
+unlinkFunc(SyscallDesc *desc, ThreadContext *tc, VPtr<> pathname)
 {
 std::string path;
 auto p = tc->getProcessPtr();
@@ -461,7 +461,7 @@

 SyscallReturn
 linkFunc(SyscallDesc *desc, ThreadContext *tc,

[gem5-dev] Change in gem5/gem5[develop]: sim: Get rid of the IsConforming type trait template.

[Gabe Black (Gerrit) via gem5-dev]

Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/40495 )



Change subject: sim: Get rid of the IsConforming type trait template.
..

sim: Get rid of the IsConforming type trait template.

The idea of this template was to distinguish types which should
grow/shrink based on the native size of the ABI in question. Or in other
words, if the ABI was 32 bit, the type should also be 32 bit, or 64 bit
and 64 bit.

Unfortunately, I had intended for Addr to be a conforming type (since
local pointers would be conforming), but uint64_t not to be. Since Addr
is defined as a typedef of uint64_t, the compiler would make *both*
types conforming, giving incorrect behavior on 32 bit systems.

Local pointers will need to be handled in a different way, likely with
the VPtr template, so that they will be treated correctly and not like
an explicitly 64 bit data type.

Change-Id: Idfdd5351260b48bb531a1926b93e0478a297826d
---
M src/arch/arm/aapcs32.hh
M src/sim/syscall_abi.hh
2 files changed, 6 insertions(+), 37 deletions(-)



diff --git a/src/arch/arm/aapcs32.hh b/src/arch/arm/aapcs32.hh
index a0f09b8..a1345bd 100644
--- a/src/arch/arm/aapcs32.hh
+++ b/src/arch/arm/aapcs32.hh
@@ -160,9 +160,7 @@
 static void
 store(ThreadContext *tc, const Integer )
 {
-if (std::is_same::value) {
-tc->setIntReg(ArmISA::INTREG_R0, (uint32_t)i);
-} else if (ArmISA::byteOrder(tc) == ByteOrder::little) {
+if (ArmISA::byteOrder(tc) == ByteOrder::little) {
 tc->setIntReg(ArmISA::INTREG_R0, (uint32_t)(i >> 0));
 tc->setIntReg(ArmISA::INTREG_R1, (uint32_t)(i >> 32));
 } else {
@@ -199,11 +197,6 @@
 static Integer
 get(ThreadContext *tc, Aapcs32::State )
 {
-if (std::is_same::value &&
-state.ncrn <= state.MAX_CRN) {
-return tc->readIntReg(state.ncrn++);
-}
-
 if (alignof(Integer) == 8 && (state.ncrn % 2))
 state.ncrn++;

diff --git a/src/sim/syscall_abi.hh b/src/sim/syscall_abi.hh
index 984f0e0..021e7b0 100644
--- a/src/sim/syscall_abi.hh
+++ b/src/sim/syscall_abi.hh
@@ -36,18 +36,6 @@

 class SyscallDesc;

-namespace GuestABI
-{
-
-// Does this normally 64 bit data type shrink down to 32 bits for 32 bit  
ABIs?

-template 
-struct IsConforming : public std::false_type {};
-
-template <>
-struct IsConforming : public std::true_type {};
-
-} // namespace GuestABI
-
 struct GenericSyscallABI
 {
 using State = int;
@@ -60,25 +48,13 @@
 {
 // Is this argument too big for a single register?
 template 
-struct IsWide;
+struct IsWide : public std::false_type {};

 template 
-struct IsWide::value &&
-(sizeof(T) < sizeof(uint64_t) ||
- GuestABI::IsConforming::value)>>
-{
-static const bool value = false;
-};
-
-template 
-struct IsWide::value &&
-sizeof(T) == sizeof(uint64_t) &&
-!GuestABI::IsConforming::value>>
-{
-static const bool value = true;
-};
+struct IsWide : public typename std::enable_if_t<
+std::is_integral::value && sizeof(T) > sizeof(uint32_t),
+std::true_type>
+{};

 // Read two registers and merge them into one value.
 static uint64_t

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Idfdd5351260b48bb531a1926b93e0478a297826d
Gerrit-Change-Number: 40495
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: arch,sim: Add a UintPtr type to the ABI types for GuestABI.

[Gabe Black (Gerrit) via gem5-dev]

Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/40496 )



Change subject: arch,sim: Add a UintPtr type to the ABI types for GuestABI.
..

arch,sim: Add a UintPtr type to the ABI types for GuestABI.

This type is primarily used to determine the size of a pointer when
using that ABI, similar to the uintptr_t type, but also less directly
to determine the "native" size of the ABI. For instance, for 32 bit ARM
ABIs, it should be defined as uint32_t since that's both the size of a
uintptr_t, and, less directly, the size of a 32 bit ARM register and
"naturally" sized types in that ABI.

This type can be used by the VPtr template to retrieve its actual value
from a simcall's parameters. In general, when accepting or returning a
pointer or address in a simcall, the VPtr template should be used so
that it's managed correctly by GuestABI. Addr will be treated as a
uint64_t allways which will be incorrect for 32 bit ABIs.

Change-Id: I3af046917387541d6faff96a21a1f1dbf7317e06
---
M src/arch/arm/aapcs64.hh
M src/arch/arm/reg_abi.hh
M src/arch/arm/semihosting.hh
M src/arch/sparc/se_workload.hh
M src/arch/x86/linux/se_workload.hh
M src/sim/proxy_ptr.hh
M src/sim/proxy_ptr.test.cc
M src/sim/syscall_abi.hh
8 files changed, 22 insertions(+), 8 deletions(-)



diff --git a/src/arch/arm/aapcs64.hh b/src/arch/arm/aapcs64.hh
index 8a5e437..fb7b8f8 100644
--- a/src/arch/arm/aapcs64.hh
+++ b/src/arch/arm/aapcs64.hh
@@ -44,6 +44,8 @@

 struct Aapcs64
 {
+using UintPtr = uint64_t;
+
 struct State
 {
 int ngrn=0; // Next general purpose register number.
diff --git a/src/arch/arm/reg_abi.hh b/src/arch/arm/reg_abi.hh
index eb87eff..94dea18 100644
--- a/src/arch/arm/reg_abi.hh
+++ b/src/arch/arm/reg_abi.hh
@@ -55,6 +55,7 @@
 struct Argument::value &&
+std::is_integral::value &&
 ABI::template IsWide::value>>
 {
 static Arg
diff --git a/src/arch/arm/semihosting.hh b/src/arch/arm/semihosting.hh
index 74697f4..7566887 100644
--- a/src/arch/arm/semihosting.hh
+++ b/src/arch/arm/semihosting.hh
@@ -133,6 +133,8 @@

 struct Abi64 : public AbiBase
 {
+using UintPtr = uint64_t;
+
 class State : public StateBase
 {
   public:
@@ -145,6 +147,8 @@

 struct Abi32 : public AbiBase
 {
+using UintPtr = uint32_t;
+
 class State : public StateBase
 {
   public:
diff --git a/src/arch/sparc/se_workload.hh b/src/arch/sparc/se_workload.hh
index e39261d..7303010 100644
--- a/src/arch/sparc/se_workload.hh
+++ b/src/arch/sparc/se_workload.hh
@@ -105,6 +105,7 @@
 template 
 struct Argument::value &&
 SparcISA::SEWorkload::SyscallABI32::IsWide::value>>
 {
 using ABI = SparcISA::SEWorkload::SyscallABI32;
diff --git a/src/arch/x86/linux/se_workload.hh  
b/src/arch/x86/linux/se_workload.hh

index c1cd234..cd26e04 100644
--- a/src/arch/x86/linux/se_workload.hh
+++ b/src/arch/x86/linux/se_workload.hh
@@ -93,7 +93,7 @@

 template 
 struct Argument::value &&
 X86ISA::EmuLinux::SyscallABI32::IsWide::value>>
 {
 using ABI = X86ISA::EmuLinux::SyscallABI32;
diff --git a/src/sim/proxy_ptr.hh b/src/sim/proxy_ptr.hh
index 02263ba..968c156 100644
--- a/src/sim/proxy_ptr.hh
+++ b/src/sim/proxy_ptr.hh
@@ -338,7 +338,8 @@
 static ProxyPtr
 get(ThreadContext *tc, typename ABI::State )
 {
-return ProxyPtr(Argument::get(tc, state), tc);
+return ProxyPtr(
+Argument::get(tc, state), tc);
 }
 };

@@ -349,7 +350,7 @@
 get(ThreadContext *tc, typename ABI::State )
 {
 return ConstProxyPtr(
-Argument::get(tc, state), tc);
+Argument::get(tc, state), tc);
 }
 };

diff --git a/src/sim/proxy_ptr.test.cc b/src/sim/proxy_ptr.test.cc
index b9f46e6..de0194d 100644
--- a/src/sim/proxy_ptr.test.cc
+++ b/src/sim/proxy_ptr.test.cc
@@ -465,6 +465,7 @@

 struct TestABI
 {
+using UintPtr = uint64_t;
 using State = int;
 };

diff --git a/src/sim/syscall_abi.hh b/src/sim/syscall_abi.hh
index 021e7b0..a60af42 100644
--- a/src/sim/syscall_abi.hh
+++ b/src/sim/syscall_abi.hh
@@ -42,18 +42,21 @@
 };

 struct GenericSyscallABI64 : public GenericSyscallABI
-{};
+{
+using UintPtr = uint64_t;
+};

 struct GenericSyscallABI32 : public GenericSyscallABI
 {
+using UintPtr = uint32_t;
+
 // Is this argument too big for a single register?
 template 
 struct IsWide : public std::false_type {};

 template 
-struct IsWide : public typename std::enable_if_t<
-std::is_integral::value && sizeof(T) > sizeof(uint32_t),
-std::true_type>
+struct IsWide sizeof(UintPtr))>> :
+public std::true_type
 {};

 // Read two registers and merge them into one value.
@@ -89,7 +92,8 @@
 // arguments aren't handled generically.
 template 
 struct Argument::value>>
+typename std::enable_if_t::value &&
+ 

[gem5-dev] Change in gem5/gem5[develop]: sim: Add a void * analogue to VPtr.

[Gabe Black (Gerrit) via gem5-dev]

Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/40497 )



Change subject: sim: Add a void * analogue to VPtr.
..

sim: Add a void * analogue to VPtr.

The default type for VPtr is now void, and the void partial
specialization of VPtr is basically just a fancy container for Addr. Its
purpose is to distinguish guest addresses from actual uint64_t-s in the
signature of simcalls so that types which are purposefully 64 bits will
stay that way, and addresses will scale to the size of pointers in the
target ABI.

Change-Id: I71e2201f5917005861ba678c6675dbcbaa0965b3
---
M src/sim/proxy_ptr.hh
1 file changed, 27 insertions(+), 2 deletions(-)



diff --git a/src/sim/proxy_ptr.hh b/src/sim/proxy_ptr.hh
index 968c156..cd0d409 100644
--- a/src/sim/proxy_ptr.hh
+++ b/src/sim/proxy_ptr.hh
@@ -251,7 +251,8 @@
 explicit ProxyPtr(Args&&... args) : CPP(0, args...) {}

 template ::value>>
+typename std::enable_if_t::value &&
+  !std::is_same::value>>
 ProxyPtr(const ProxyPtr ) : CPP(other) {}

 ProxyPtr(const PP ) : CPP(other) {}
@@ -322,6 +323,30 @@
 }
 };

+template 
+class ProxyPtr
+{
+  protected:
+Addr _addr;
+
+  public:
+ProxyPtr(Addr new_addr, ...) : _addr(new_addr) {}
+
+template 
+ProxyPtr(const ProxyPtr ) : _addr(other.addr()) {}
+
+ProxyPtr &
+operator = (Addr new_addr)
+{
+_addr = new_addr;
+return *this;
+}
+
+operator Addr() const { return _addr; }
+
+Addr addr() const { return _addr; }
+};
+
 template 
 typename std::enable_if_t::value, ProxyPtr>
 operator + (A a, const ProxyPtr )
@@ -368,7 +393,7 @@

 template 
 using ConstVPtr = ConstProxyPtr;
-template 
+template 
 using VPtr = ProxyPtr;

 #endif // __SIM_PROXY_PTR_HH__

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I71e2201f5917005861ba678c6675dbcbaa0965b3
Gerrit-Change-Number: 40497
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black 
Gerrit-MessageType: newchange
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