[m5-dev] Cron m5t...@zizzer /z/m5/regression/do-regression quick

* build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-timing-mp FAILED! * build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-atomic-mp FAILED! * build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-timing FAILED! *

Re: [m5-dev] Cron m5t...@zizzer /z/m5/regression/do-regression quick

Not me I hope. File system issues again? Cron Daemon wrote: * build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-timing-mp FAILED! * build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-atomic-mp FAILED! *

[m5-dev] Review Request: X86: Take advantage of new PCState syntax.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/307/ --- Review request for Default. Summary --- X86: Take advantage of new PCState

[m5-dev] Review Request: SPARC: Take advantage of new PCState syntax.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/308/ --- Review request for Default. Summary --- SPARC: Take advantage of new PCState

[m5-dev] Review Request: POWER: Take advantage of new PCState syntax.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/309/ --- Review request for Default. Summary --- POWER: Take advantage of new PCState

[m5-dev] Review Request: MIPS: Take advantage of new PCState syntax.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/310/ --- Review request for Default. Summary --- MIPS: Take advantage of new PCState

[m5-dev] Review Request: Alpha: Take advantage of new PCState syntax.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/311/ --- Review request for Default. Summary --- Alpha: Take advantage of new PCState

[m5-dev] Review Request: ARM: Take advantage of new PCState syntax.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/312/ --- Review request for Default. Summary --- ARM: Take advantage of new PCState

Re: [m5-dev] Review Request: ISA: Get the parser to support pc state components more elegantly.

This change implements the ISA parser part of new syntax to read and write components of the PCState more like the old syntax. Things center around the PCState operand type, it's default ctype, and its register index. When manipulating the PC state object as a whole, the ctype is set to None and

Re: [m5-dev] Cron m5t...@zizzer /z/m5/regression/do-regression quick

Pretty sure it is... I'll try to move a copy to zizzer soon. Ali On Nov 15, 2010, at 2:15 AM, Gabe Black wrote: Not me I hope. File system issues again? Cron Daemon wrote: * build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-timing-mp FAILED! *

Re: [m5-dev] isa_parser debug mode

Sounds reasonable to me too. Should we have a single flag that enables tracebacks in both the parser and in the rest of python? IIRC, we print the python backtrace by default when we hit a python exception, and it seems to me that most of the time the backtrace obscures a useful error message

Re: [m5-dev] Review Request: ISA: Get the parser to support pc state components more elegantly.

Nice! I just skimmed the code quickly, but it looks good to me. Steve On Mon, Nov 15, 2010 at 4:35 AM, Gabe Black gbl...@eecs.umich.edu wrote: This change implements the ISA parser part of new syntax to read and write components of the PCState more like the old syntax. Things center around

Re: [m5-dev] Review Request: O3: Make O3 support variably lengthed instructions.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/281/#review481 --- Ship it! - Ali On 2010-11-11 04:44:28, Gabe Black wrote:

[m5-dev] changeset in m5: ARM: Do something predictable for an UNPREDICTA...

changeset 9e11081542e4 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=9e11081542e4 description: ARM: Do something predictable for an UNPREDICTABLE branch. diffstat: src/arch/arm/types.hh | 4 1 files changed, 4 insertions(+), 0 deletions(-) diffs (14 lines):

[m5-dev] changeset in m5: ARM: Fix SRS instruction to micro-code memory o...

changeset 79adfecb2b8a in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=79adfecb2b8a description: ARM: Fix SRS instruction to micro-code memory operation and register update. Previously the SRS instruction attempted to writeback in initiateAcc() which

[m5-dev] changeset in m5: CPU: Fix bug when a split transaction is issued...

changeset 434b5dfb87d9 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=434b5dfb87d9 description: CPU: Fix bug when a split transaction is issued to a faster cache In the case of a split transaction and a cache that is faster than a CPU we could get two

[m5-dev] changeset in m5: ARM: Use the correct delete operator for RFE

changeset 2b65eb281f5f in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=2b65eb281f5f description: ARM: Use the correct delete operator for RFE diffstat: src/arch/arm/insts/mem.hh | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diffs (12 lines): diff -r

[m5-dev] changeset in m5: ARM: Add support for switching CPUs

changeset 7bf78d12b359 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=7bf78d12b359 description: ARM: Add support for switching CPUs diffstat: src/arch/arm/table_walker.cc | 16 ++-- src/arch/arm/table_walker.hh | 1 + src/arch/arm/utility.cc | 17

[m5-dev] changeset in m5: ARM: Add support for a dumb IDE controller

changeset 0731d632db76 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=0731d632db76 description: ARM: Add support for a dumb IDE controller diffstat: configs/common/FSConfig.py | 10 ++ src/dev/Ide.py | 2 ++ src/dev/arm/realview.cc| 6

[m5-dev] changeset in m5: ARM: Make utility.hh meet style guidelines

changeset b12a5700f1fa in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=b12a5700f1fa description: ARM: Make utility.hh meet style guidelines diffstat: src/arch/arm/utility.hh | 168 1 files changed, 84 insertions(+), 84

[m5-dev] changeset in m5: ARM: Add support for GDB on ARM

changeset 08e1e28a062a in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=08e1e28a062a description: ARM: Add support for GDB on ARM diffstat: src/arch/arm/SConscript|1 + src/arch/arm/remote_gdb.cc | 346 +

[m5-dev] changeset in m5: SCons: Cleanup SCons output during compile

changeset 846fb3ffe0dc in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=846fb3ffe0dc description: SCons: Cleanup SCons output during compile diffstat: SConstruct | 65 - src/SConscript | 48

[m5-dev] changeset in m5: O3: prevent a squash when completeAcc() modifie...

changeset 28a677d7cb51 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=28a677d7cb51 description: O3: prevent a squash when completeAcc() modifies misc reg through TC. This happens on ARM instructions when they update the IT state bits. Code and

[m5-dev] changeset in m5: CPU/ARM: Add SIMD op classes to CPU models and ...

changeset e93e7e0caae1 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=e93e7e0caae1 description: CPU/ARM: Add SIMD op classes to CPU models and ARM ISA. diffstat: src/arch/arm/isa/insts/div.isa |6 +- src/arch/arm/isa/insts/fp.isa | 278 ++-

[m5-dev] changeset in m5: ARM: Add comment about the organization of the ...

changeset 6e399e631a43 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=6e399e631a43 description: ARM: Add comment about the organization of the IT state register diffstat: src/arch/arm/miscregs.hh | 6 ++ 1 files changed, 6 insertions(+), 0 deletions(-) diffs

[m5-dev] changeset in m5: O3: reset architetural state by calling clear()

changeset ff2213d13e58 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=ff2213d13e58 description: O3: reset architetural state by calling clear() diffstat: src/cpu/o3/thread_context_impl.hh | 16 +++- 1 files changed, 15 insertions(+), 1 deletions(-)

Re: [m5-dev] Review Request: O3: Make all instructions that write a misc register not perform the write until commit.

On 2010-11-10 08:07:39, Steve Reinhardt wrote: So it looks like whether you call setMiscReg() or setMiscRegNoEffect() then you buffer the update and call setMiscReg() later... i.e., even if you called setMiscRegNoEffect() originally you end up calling setMiscReg() at commit. Are

Re: [m5-dev] Review Request: O3: Make all instructions that write a misc register not perform the write until commit.

On Nov 15, 2010, at 8:29 PM, Gabriel Michael Black wrote: It seems like our notion of serializing came from the definition Alpha uses, and sometimes we need a stronger one. X86 is going to have similar issues in some cases, although I couldn't necessarily list them for you off hand. The

Re: [m5-dev] Review Request: O3: Make all instructions that write a misc register not perform the write until commit.

Quoting Ali Saidi sa...@umich.edu: On Nov 15, 2010, at 8:29 PM, Gabriel Michael Black wrote: It seems like our notion of serializing came from the definition Alpha uses, and sometimes we need a stronger one. X86 is going to have similar issues in some cases, although I couldn't necessarily

Re: [m5-dev] Review Request: O3: Make all instructions that write a misc register not perform the write until commit.

On Nov 15, 2010, at 8:44 PM, Gabriel Michael Black wrote: Quoting Ali Saidi sa...@umich.edu: On Nov 15, 2010, at 8:29 PM, Gabriel Michael Black wrote: It seems like our notion of serializing came from the definition Alpha uses, and sometimes we need a stronger one. X86 is going to have

[m5-dev] changeset in m5: O3: Make O3 support variably lengthed instructi...

changeset 03efcdc3421f in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=03efcdc3421f description: O3: Make O3 support variably lengthed instructions. diffstat: src/arch/alpha/predecoder.hh | 11 +- src/arch/mips/predecoder.hh | 11 +- src/arch/power/predecoder.hh

[m5-dev] changeset in m5: Stats: Update the O3 fetch stats for SPARC.

changeset 634d88f0dbd4 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=634d88f0dbd4 description: Stats: Update the O3 fetch stats for SPARC. diffstat: tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-)

Re: [m5-dev] changeset in m5: ARM: Add support for a dumb IDE controller

On 11/15/10 12:09, Ali Saidi wrote: diffs (119 lines): diff -r 859e8bc1cdc2 -r 0731d632db76 configs/common/FSConfig.py --- a/configs/common/FSConfig.py Mon Nov 15 14:04:03 2010 -0600 +++ b/configs/common/FSConfig.py Mon Nov 15 14:04:03 2010 -0600 @@ -209,6 +209,16 @@

Re: [m5-dev] changeset in m5: ARM: Add support for a dumb IDE controller

On Nov 15, 2010, at 9:52 PM, Gabe Black wrote: On 11/15/10 12:09, Ali Saidi wrote: diffs (119 lines): diff -r 859e8bc1cdc2 -r 0731d632db76 configs/common/FSConfig.py --- a/configs/common/FSConfig.py Mon Nov 15 14:04:03 2010 -0600 +++ b/configs/common/FSConfig.py Mon Nov 15

Re: [m5-dev] Review Request: ARM: Take advantage of new PCState syntax.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/312/#review483 --- src/arch/arm/isa/operands.isa http://reviews.m5sim.org/r/312/#comment698

Re: [m5-dev] Review Request: imported patch ext/noisa.patch

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/303/#review484 --- Ship it! I can't wait to use it - Nathan On 2010-11-15 14:43:46, Ali

Re: [m5-dev] Review Request: imported patch ext/noisa.patch

Think I could convince you to get your stats changes in order. :) Ali ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev