* build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-timing
passed.
* build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing passed.
* build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby
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*
Hi All,
I am doing some experiments on M5 for research, and I want to run splash2 in
FS mode but for SMT not CMP. And I found that right now M5 doesn't support
SMT for FS mode. So my question is if someone can explain or highlight the
major things that should be done to support SMT which will
Hi Ziad,
I think Korey would be the best person to ask, but I think the main issue is
that while most of the o3 functionality is split out by ThreadID, interrupt
handling isn't. It's all hard-coded for thread 0. Korey, any idea on the time
it would take?
Thanks,
Ali
On Dec 6, 2010, at
Thank you Ali for your reply.
Ziad.
--
On Mon, Dec 6, 2010 at 11:37 AM, Ali Saidi sa...@umich.edu wrote:
Hi Ziad,
I think Korey would be the best person to ask, but I think
I put together a wiki page here:
http://m5sim.org/wiki/index.php/Python_Parameter_Types
that attempts to document the parameter types that are available and
how they work. If the experts (that's probably you, Steve and Nate)
could look it over and make sure I didn't misinterpret/mangle
I put together a wiki page here:
http://m5sim.org/wiki/index.php/Python_Parameter_Types
that attempts to document the parameter types that are available and
how they work. If the experts (that's probably you, Steve and Nate)
could look it over and make sure I didn't misinterpret/mangle
Quoting nathan binkert n...@binkert.org:
I put together a wiki page here:
http://m5sim.org/wiki/index.php/Python_Parameter_Types
that attempts to document the parameter types that are available and
how they work. If the experts (that's probably you, Steve and Nate)
could look it over and make
On Wed, Dec 1, 2010 at 3:07 PM, Ali Saidi sa...@umich.edu wrote:
Continuing the e-mail thread that never dies
It appears as though the dcache some how does the correct thing when a read
request comes into the l2 bus. Note that the dcache is snooping the
request.
Listening for system
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http://reviews.m5sim.org/r/337/#comment751
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On 2010-12-06 15:56:33, Steve Reinhardt wrote:
src/mem/ruby/common/Debug.hh, line 146
http://reviews.m5sim.org/r/337/diff/2/?file=5442#file5442line146
What changed in these lines? I don't see any difference here. Was it
just a whitespace thing? If so, was it intentional?
I
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Ship it!
- Steve
On 2010-12-02 20:35:31, Nilay Vaish wrote:
On 2010-12-06 15:56:33, Steve Reinhardt wrote:
src/mem/ruby/common/Debug.hh, line 146
http://reviews.m5sim.org/r/337/diff/2/?file=5442#file5442line146
What changed in these lines? I don't see any difference here. Was it
just a whitespace thing? If so, was it intentional?
I think the reason is that we would like to have the line numbers from the
.sm file. If we use ASSERT(), then the line numbers from the generated .cc
files will be put in place.
That makes sense, thanks...
Better would be to eventually make SLICC emit #file and #line directives.
Nate
That's what is going on right now.
Nilay
On Mon, December 6, 2010 10:16 pm, nathan binkert wrote:
I think the reason is that we would like to have the line numbers from
the .sm file. If we use ASSERT(), then the line numbers from the
generated .cc files will be put in place.
That makes
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