ac4da9f8ea80
src/mem/slicc/ast/MemberExprAST.py ac4da9f8ea80
Diff: http://reviews.m5sim.org/r/611/diff
Testing
---
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of the protocol implementation is close to \epsilon. I
think this is what I observed today in the morning. Do think this
understanding is correct?
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Korey, try 'hg status'. It would list the set of files that are not being
tracked. May be there is some file that should be committed and has not
been.
--
Nilay
On Thu, 9 Jun 2011, Korey Sewell wrote:
My local repo has this at the tip:
hg tip
changeset: 8342:77d12d8f7971
tag: tip
On Wed, 8 Jun 2011, Jack Harvard wrote:
When you declare your function private, you can't use instance.function() to
access it. Is it generating a compile time error?
On 8 Jun 2011, at 00:31, Nilay Vaish wrote:
Consider the following class declarations --
class A
{
public:
virtual void
On Wed, 8 Jun 2011, Jack Harvard wrote:
On 8 Jun 2011, at 19:09, Nilay Vaish wrote:
On Wed, 8 Jun 2011, Jack Harvard wrote:
When you declare your function private, you can't use instance.function() to
access it. Is it generating a compile time error?
On 8 Jun 2011, at 00:31, Nilay Vaish
On Wed, 8 Jun 2011, Jack Harvard wrote:
On 8 Jun 2011, at 23:28, Nilay Vaish wrote:
On Wed, 8 Jun 2011, Jack Harvard wrote:
On 8 Jun 2011, at 19:09, Nilay Vaish wrote:
On Wed, 8 Jun 2011, Jack Harvard wrote:
When you declare your function private, you can't use instance.function
not output any error if set/getState() or
set/getAccessPermission() are missing. But I have patch in the
queue which enables catching these errors in SLICC. For now
GCC outputs that a particular function has not been implemented.
- Nilay
changeset 30daf1dd5c91 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=30daf1dd5c91
description:
Ruby: Correctly set access permissions for directory entries
The access permissions for the directory entries are not being set
correctly.
This is because
Consider the following class declarations --
class A
{
public:
virtual void function() = 0;
};
class B : public A
{
private:
void function();
}
int main()
{
B b;
b.function();
}
Will this code compile correctly?
--
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/protocol/RubySlicc_Types.sm b9ba22cb23f2
src/mem/ruby/slicc_interface/AbstractController.hh b9ba22cb23f2
src/mem/slicc/ast/MethodCallExprAST.py b9ba22cb23f2
src/mem/slicc/symbols/StateMachine.py b9ba22cb23f2
Diff: http://reviews.m5sim.org/r/684/diff
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---
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and 1 loads with ruby random tester.
Thanks,
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(SCons.Node.FS.File instance at 0x11353bd8) in state executed
--
Nilay
On Sun, 5 Jun 2011, m5test wrote:
scons: *** Found dependency cycle(s):
* build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/o3-timing passed.
* build/ALPHA_SE/tests/opt/quick/01.hello-2T-smt/alpha/linux/o3-timing
/DMA_Controller.hh
(SCons.Node.FS.File instance at 0x8f1dcf8) in state up_to_date
Internal Error: no cycle found for node
build/ALPHA_SE_MOESI_hammer/params/L1Cache_Controller.hh
(SCons.Node.FS.File instance at 0x9b7d7e8) in state up_to_date
--
Nilay
On Sat, 4 Jun 2011, Cron Daemon wrote:
scons
Will clearing all the existing builds and starting afresh remove this
issue? Can some one do this?
--
Nilay
On Sat, 4 Jun 2011, Steve Reinhardt wrote:
It seems very strange... like at a high level it thinks there's a
cycle, but when it goes to print out where it is it can't find one.
I've
changeset b9ba22cb23f2 in /z/repo/m5
details: http://repo.gem5.org/m5?cmd=changeset;node=b9ba22cb23f2
description:
SLICC: Remove machine name as prefix to functions
Currently, the machine name is appended before any of the functions
defined with in the sm files. This is not
accesses for different ratios -- 100:0, 99:1, 90:1, 50:50,
10:90, 1:99. It is working in all the cases.
Thanks,
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/slicc/ast/MemberExprAST.py 681497e0356b
src/mem/slicc/symbols/Func.py 681497e0356b
src/mem/slicc/symbols/StateMachine.py 681497e0356b
Diff: http://reviews.m5sim.org/r/611/diff
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Diff: http://reviews.m5sim.org/r/723/diff
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. In fact, we
advise users to move to gem5.
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On Thu, 2 Jun 2011, huangyongbing wrote:
Hi.
I am currently using GEMS and Simics. So I care about whether the corresponding
codes are also updated in GEMS.
-Yongbing Huang
发件人： Nilay Vaish
发送时间： 2011-06-02 09:57:40
收件人： Nilay Vaish
On Sat, 28 May 2011, Nilay Vaish wrote:
Hi Brad
I am trying to complete the patch on functional accesses in Ruby. I came
across this problem while testing the patch for higher number of processors.
I am working with MESI CMP directory protocol right now. So I will describe
the problem
state.
It seems to me that the controller should supply the function for deciding
the access permissions, since it is possible that one the TBE holds the
block.
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dda2a88eb7c4
src/mem/protocol/RubySlicc_Types.sm dda2a88eb7c4
src/mem/slicc/ast/MethodCallExprAST.py dda2a88eb7c4
src/mem/slicc/symbols/StateMachine.py dda2a88eb7c4
Diff: http://reviews.m5sim.org/r/684/diff
Testing
---
Thanks,
Nilay
On Fri, 6 May 2011, Beckmann, Brad wrote:
Hi Nilay,
Yeah, pulling the State into the Machine makes sense to me. If I
recall, my previous patch made it necessary that each machine included a
state_declaration (previously the state enum). More tightly integrating
the state to the machine
changeset a6363c870af6 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=a6363c870af6
description:
Trace: Remove the options trace-help and trace-flags
The options trace-help and trace-flags are no longer required. In there
place,
the options debug-help
Joel, I have pushed in the patch the removes the options trace-help and
trace-flags. But trace-start and trace-file work as before. You can use
them in conjunction with debug-flags.
--
Nilay
On Fri, 6 May 2011, Nilay Vaish wrote:
I was thinking og doing it since Nate is not around. I'll do
Korey, I don't think there will be any change in the simulation
performance. I am not sure about stats.
Brad, were the stats updated after you made the change?
--
Nilay
On Fri, 6 May 2011, Korey Sewell wrote:
Nilay,
can you explain the impact of that bug in terms of simulation performance
Koreay, DPRINTF already works in sm files. Use RubySlicc as the flag. You
can also use error() and assert() functions which have the following
prototypes --
void error(std::string msg);
void assert(bool condition);
--
Nilay
On Fri, 6 May 2011, Korey Sewell wrote:
I guess I should rephrase
I was thinking og doing it since Nate is not around. I'll do it soon.
--
Nilay
On Fri, 6 May 2011, Joel Hestness wrote:
Hey Nilay,
It looks like the tracing (debug) functionality is now working again,
but the M5 help message is still incorrect (and extremely misleading). For
instance, trace
/RubySlicc_Types.sm 3c628a51f6e1
src/mem/slicc/ast/MethodCallExprAST.py 3c628a51f6e1
src/mem/slicc/symbols/StateMachine.py 3c628a51f6e1
Diff: http://reviews.m5sim.org/r/684/diff
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on
sorting included files.
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Nate, since I have provided the option USE_MYSQL=False, why should
mysql.hh even come in to picture?
--
Nilay
On Wed, 20 Apr 2011, nathan binkert wrote:
The solution is to #include base/types.hh in mysql.hh, but to be
honest, I'm not sure how this is even happening. Perhaps you need
Is there a tester for testing the functionality of Ruby's memory
controller?
Thanks
Nilay
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().
Overall, I hope/think we can add functional access support without
requiring any more changes to the protocol specific .sm files beyond the
changeset: 8086:bf0335d98250 that I checked in a couple months ago.
Nilay Vaish wrote:
How would you use the function that is generated by SLICC
) {
cmd = MemCmd::FunctionalAccessError;
}
}
Will make the required changes.
- Nilay
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Nate, it seems one of your checkins from yesterday has a bug. I receive
the following message on executing any merculrial command.
*** failed to import extension style from ./util/style.py: invalid syntax
(file_types.py, line 143)
--
Nilay
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from yesterday has a bug. I receive the
following message on executing any merculrial command.
*** failed to import extension style from ./util/style.py: invalid syntax
(file_types.py, line 143)
--
Nilay
I am using python version 2.4.3.
Nilay
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().
Overall, I hope/think we can add functional access support without
requiring any more changes to the protocol specific .sm files beyond the
changeset: 8086:bf0335d98250 that I checked in a couple months ago.
Nilay Vaish wrote:
How would you use the function that is generated by SLICC
Brad, can you elaborate on implementing functional accesses for the
PioPort?
--
Nilay
On Wed, 13 Apr 2011, Beckmann, Brad wrote:
I just reviewed it. Please let me know if you have any questions.
Brad
-Original Message-
From: m5-dev-boun...@m5sim.org [mailto:m5-dev-boun
system experts (Nate, Steve, or Ali) and get them
to sign off. They might not see that this change touches outside of Ruby.
Gabe, I made the changes that you had pointed.
- Nilay
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().
Overall, I hope/think we can add functional access support without
requiring any more changes to the protocol specific .sm files beyond the
changeset: 8086:bf0335d98250 that I checked in a couple months ago.
Nilay Vaish wrote:
How would you use the function that is generated by SLICC
://reviews.m5sim.org/r/611/diff/6/?file=11565#file11565line246
Please align this statement.
I am removing this line.
- Nilay
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:1, 50:50,
10:90, 1:99. It is working in all the cases.
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On Mon, 11 Apr 2011, Beckmann, Brad wrote:
Hi Nilay,
Yes, that is a good point. We really just need the interface to the
permission to be available from AbstractEntry. The variable itself
doesn't really need to be there. However, to make that change, you'll
need to modify how CacheMemory
permission, unless we expose the state to Cache Memory class.
Also, as it now stands, it seems one cannot have two different types of
directory controllers in a system. Is this correct? If yes, then why this
restriction?
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);
testerSenderState-subBlock-mergeFrom(data);
}
Thanks
Nilay
On Tue, 1 Mar 2011, Beckmann, Brad wrote:
I forgot that the memtester includes functional accesses. That is a
good suggestion, especially when it comes to testing the situations
where Ruby can't satisfy the functional access due to contention
Brad, I figured out the error, so no need to respond to my previous mail.
--
Nilay
On Sat, 9 Apr 2011, Nilay Vaish wrote:
Brad, functional accesses work for the case when the only functional accesses
are allowed in the system. Currently I am working when the ratio is 1:1 for
functional
popcount() builtin available with GCC.
--
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Between different versions of gcc. Do we actually test whether the code
compiles using other compilers?
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The problem is that LONG_BITS is 31, ie std::numeric_limitslong::digits
returns 31 and not 32 which is what the writer expected.
--
Nilay
From: koreylsew...@gmail.com [mailto:koreylsew...@gmail.com] On Behalf Of
Korey Sewell
Sent: Tuesday, April 05, 2011 7:14 AM
To: Beckmann, Brad
Subject
On Thu, 7 Apr 2011, Gabriel Michael Black wrote:
Quoting Nilay Vaish ni...@cs.wisc.edu:
On Thu, 7 Apr 2011, Gabriel Michael Black wrote:
When you say this is portable, what do you mean? Portable between
compilers? We usually use gcc, but we have at least partial support for
other compilers
comment as before.
- Nilay
On 2011-04-05 11:19:26, Korey Sewell wrote:
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(Updated
popcount() builtin available with GCC.
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On 2011-03-31 22:08:21, Brad Beckmann wrote:
This looks great, I just have a few minor suggestions below.
It seems like the next step is to figure out how to deal with functional
accesses not succeeding in the CPUs and devices.
Nilay Vaish wrote:
Brad, I would make the changes
AbstractMemory.py file.
- Nilay
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---
On 2011-04-02 11:42:47, Nilay Vaish wrote
aeec9e157d06
src/mem/ruby/system/Sequencer.cc aeec9e157d06
src/mem/ruby/system/Sequencer.py aeec9e157d06
src/mem/ruby/system/System.hh aeec9e157d06
src/mem/ruby/system/System.cc aeec9e157d06
Diff: http://reviews.m5sim.org/r/611/diff
Testing
---
Thanks,
Nilay
On Fri, 1 Apr 2011, Korey Sewell wrote:
That's a good point.
I'll coordinate with Nilay offline to get him the right image.
Nilay, from your previous optimizations trials, where did you see most of
the simulation time being sent at?
On Fri, Apr 1, 2011 at 4:48 PM, Ali Saidi sa...@umich.edu
On 2011-03-31 22:08:21, Brad Beckmann wrote:
This looks great, I just have a few minor suggestions below.
It seems like the next step is to figure out how to deal with functional
accesses not succeeding in the CPUs and devices.
Nilay Vaish wrote:
Brad, I would make the changes
On 2011-04-01 09:30:54, Brad Beckmann wrote:
Hi Nilay,
Comments below. I might be missing something, but the changes to
DirectoryMemory seem straightforward.
No, you are not missing anything. It is just that I had not implemented
it up till now.
- Nilay
of places in src/mem/port.cc, the packet is on the stack.
But in src/cpu/testers/memtest/memtest.cc, the packet is on the heap.
As per the documentation, the packet is owned by the requestor. So, the
requestor will have to free the packet. I will remove this code.
- Nilay
aeec9e157d06
src/mem/ruby/system/Sequencer.py aeec9e157d06
src/mem/ruby/system/System.hh aeec9e157d06
src/mem/ruby/system/System.cc aeec9e157d06
Diff: http://reviews.m5sim.org/r/611/diff
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also need to add
code for directory memory accesses. Can you elaborate on the next step you
mentioned? We are yet not dealing with the devices, I believe.
- Nilay
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I am wondering what's the need of the file Protocol.hh, I removed it from
different in the protocol independent part of Ruby. I also removed the
file standard_1level_CMP-protocol.sm from the MOESI_hammer.slicc.
Everything compiles perfectly. I am not sure what the requirement is.
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---
Ship it!
Is context Id being used any where?
- Nilay
On 2011-03-31
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---
Ship it!
- Nilay
On 2011-03-31 12:21:22, Lisa Hsu wrote
/#comment1430
Remove the comment.
src/mem/ruby/system/WireBuffer.hh
http://reviews.m5sim.org/r/627/#comment1431
Remove this line as well.
src/mem/ruby/system/WireBuffer.py
http://reviews.m5sim.org/r/627/#comment1429
Do we need this commented piece of code?
- Nilay
On 2011-03-31 12
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Ship it!
- Nilay
On 2011-03-31 12:20:59, Lisa Hsu wrote
with these changes.
- Nilay
On 2011-03-31 12:20:53, Lisa Hsu wrote:
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(Updated 2011-03-31 12
the existing
protocols compile properly.
- Nilay
On 2011-03-31 14:26:33, Lisa Hsu wrote:
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-write copies simultaneously. Is this possible, or would
this be a bug in the protocol?
- Nilay
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On 2011-03-31 14:22:16, Nilay Vaish wrote:
I hope you have tested the existing protocols with these changes.
Lisa Hsu wrote:
Yes - MOESI_[CMP_[directory|token]|hammer] all compile and run -l 1000 -n
4 on the Ruby Tester. Since no logic has changed (for all my Ruby changes),
I
Lisa, should not compiler yell in this case as well?
Nilay
On Thu, March 31, 2011 8:22 pm, Lisa Hsu wrote:
changeset c7302d55d644 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=c7302d55d644
description:
CacheMemory: add allocateVoid() that is == allocate
c7302d55d644
src/mem/ruby/system/Sequencer.py c7302d55d644
src/mem/ruby/system/System.hh c7302d55d644
src/mem/ruby/system/System.cc c7302d55d644
Diff: http://reviews.m5sim.org/r/611/diff
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---
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d54b7775a6b0
src/mem/ruby/system/System.hh d54b7775a6b0
src/mem/ruby/system/System.cc d54b7775a6b0
Diff: http://reviews.m5sim.org/r/611/diff
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On Tue, 29 Mar 2011, Nilay Vaish wrote:
Brad, I have posted on the review board my current implementation for
supporting functional accesses in Ruby. This is untested and is mainly meant
for furthering the discussions. I have some questions for you --
1. How do we inform the other end
, PovrayAutumn, PovrayBench, SurgeSpecweb,
SurgeStandard, ValAccDelay, ValAccDelay2, ValCtxLat, ValMemLat,
ValMemLat2MB, ValMemLat8MB, ValStream, ValStreamCopy, ValStreamScale,
ValSysLat, ValTlbLat, Validation, bnAn
Which of these do you think would closely resemble FFT?
Nilay
On Wed, 30 Mar 2011
6ae58f06a41c
src/mem/ruby/system/System.cc 6ae58f06a41c
Diff: http://reviews.m5sim.org/r/611/diff
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as well. How can
physical memory be accessed from RubyPort?
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On Tue, 29 Mar 2011, Nilay Vaish wrote:
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changeset 1333bd6cc2eb in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=1333bd6cc2eb
description:
Config: Import math in MI_example.py
diffstat:
configs/ruby/MI_example.py | 1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diffs (11 lines):
diff -r 832ae3727c2b
I pushed in patch that imports math in MI_example.py
--
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On Mon, 28 Mar 2011, Cron Daemon wrote:
* build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby
FAILED!
* build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby
FAILED!
* build/ALPHA_SE
I will try to bisect this.
--
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On Wed, 23 Mar 2011, Arkaprava Basu wrote:
Hi Lisa and Nilay,
Thanks for the response. Following is the tip of my repo
changeset: 8174:e21f6e70169e
tag: tip
user:Nilay Vaishni...@cs.wisc.edu
date:Tue Mar 22 06:41:54 2011
here
Exiting @ tick 14536941 because Ruby Tester completed
On Wed, 23 Mar 2011, Nilay Vaish wrote:
I will try to bisect this.
--
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On Wed, 23 Mar 2011, Arkaprava Basu wrote:
Hi Lisa and Nilay,
Thanks for the response. Following is the tip of my repo
changeset: 8174:e21f6e70169e
changeset e21f6e70169e in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=e21f6e70169e
description:
Ruby: Remove CacheMsg class from SLICC
The goal of the patch is to do away with the CacheMsg class currently
in use
in coherence protocols. In place of
(const RubyRequest)':
build/ARM_FS/mem/ruby/system/Sequencer.cc:616: warning: 'ctype' may be used
uninitialized in this function
build/ARM_FS/mem/ruby/system/Sequencer.cc:653: warning: 'amtype' may be used
uninitialized in this function
These I think have been around for quite a while.
--
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processors. Since your
testing with ruby random tester, would the processor architecture even
come in to play?
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other
way I should use to do this?
What is the regression test that I should run to reproduce the errors
and warnings?
Thanks,
Tushar
Tushar, try compiling with GCC 4.2, that's the version on zizzer.
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: Convert AccessModeType to
RubyAccessMode
Hi Nilay,
Why do you want to change the name? Both names seem equivalent to me.
Brad
Brad, I had to make the decision in favor of one of the two names. I
decided not to choose AccessModeType because Mode and Type have almost the
same meaning
momentarily.
Korey and Malek, please pull these changes and confirm they fix your
problem.
Brad
Brad, how come the mails you sent on Saturday are being received now?
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changeset c1c6f36e118e in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=c1c6f36e118e
description:
SLICC: Remove WakeUp* import calls from ast/__init__.py
I had recently committed a patch that removed the WakeUp*.py files from
the
slicc/ast directory. I
I had committed an error in one of the my recent patches. I have committed
a patch that should fix this error.
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On Sun, 20 Mar 2011, Cron Daemon wrote:
See /z/m5/regression/regress-2011-03-20-03:00:01 for details.
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/DMASequencer.cc c1c6f36e118e
src/mem/ruby/system/RubyPort.cc c1c6f36e118e
src/mem/ruby/system/Sequencer.cc c1c6f36e118e
Diff: http://reviews.m5sim.org/r/327/diff
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On Sat, 19 Mar 2011, Nilay Vaish wrote:
On Fri, 18 Mar 2011, Lisa Hsu wrote:
What's going on with this patch? I don't believe it's been committed but
it
seems like it should. I've also got some patches waiting behind this
because they used to touch CacheMsg and I don't want to mess Nilay
/tests/fast/quick build/ARM_FS/tests/fast/quick
Child returned 1
When attemping to execute: util/regress '--scons-opts' '-k USE_MYSQL=no
EXTRAS=/z/m5/regression/zizzer/encumbered RUBY=True -j 7 -Q' 'quick'
--
Nilay
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changeset b043c0efa024 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=b043c0efa024
description:
Ruby: Convert AccessModeType to RubyAccessMode
This patch converts AccessModeType to RubyAccessMode so that both the
protocol dependent and independent code
changeset 5955406f7ed0 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=5955406f7ed0
description:
Ruby: Convert CacheRequestType to RubyRequestType
This patch converts CacheRequestType to RubyRequestType so that both the
protocol dependent and independent
changeset f3d1493787d4 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=f3d1493787d4
description:
SLICC: Remove the keyword wake_up_all_dependents
In order to add stall and wait facility for protocols, a keyword
wake_up_all_dependents was introduced. This
changeset 099771c7725d in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=099771c7725d
description:
SLICC: Remove the keyword wake_up_dependents
In order to add stall and wait facility for protocols, a keyword
wake_up_dependents was introduced. This patch
changeset 9a6a02a235f1 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=9a6a02a235f1
description:
SLICC: Remove external_type for structures
In SLICC, in order to define a type a data type for which it should not
generate any code, the keyword
9a6a02a235f1
Diff: http://reviews.m5sim.org/r/602/diff
Testing
---
Thanks,
Nilay
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On Fri, 18 Mar 2011, Lisa Hsu wrote:
What's going on with this patch? I don't believe it's been committed but it
seems like it should. I've also got some patches waiting behind this
because they used to touch CacheMsg and I don't want to mess Nilay up, so
I've been waiting to serialize behind
system and rest of Ruby components under RubySystem, we
are creating two paths in the graph that are running parallel to each
other, even though we have dependence between them. I would rather have a
tree / directed acyclic structure.
Thanks
Nilay
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