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(Updated 2011-06-12 14:55:00.907885)
Review request for Default.
Summary
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(Updated 2011-06-12 14:55:53.667339)
Review request for Default.
Summary
Brad, in the token coherence protocol, the l2 cache controller moves from
state O to I and sends data to the memory. I think this particular
transition is may pose a problem in enabling functional accesses for the
protocol. The problem, I think, is that both the directory and the cache
Korey, try 'hg status'. It would list the set of files that are not being
tracked. May be there is some file that should be committed and has not
been.
--
Nilay
On Thu, 9 Jun 2011, Korey Sewell wrote:
My local repo has this at the tip:
hg tip
changeset: 8342:77d12d8f7971
tag: tip
On Wed, 8 Jun 2011, Jack Harvard wrote:
When you declare your function private, you can't use instance.function() to
access it. Is it generating a compile time error?
On 8 Jun 2011, at 00:31, Nilay Vaish wrote:
Consider the following class declarations --
class A
{
public:
virtual void
On Wed, 8 Jun 2011, Jack Harvard wrote:
On 8 Jun 2011, at 19:09, Nilay Vaish wrote:
On Wed, 8 Jun 2011, Jack Harvard wrote:
When you declare your function private, you can't use instance.function() to
access it. Is it generating a compile time error?
On 8 Jun 2011, at 00:31, Nilay Vaish
On Wed, 8 Jun 2011, Jack Harvard wrote:
On 8 Jun 2011, at 23:28, Nilay Vaish wrote:
On Wed, 8 Jun 2011, Jack Harvard wrote:
On 8 Jun 2011, at 19:09, Nilay Vaish wrote:
On Wed, 8 Jun 2011, Jack Harvard wrote:
When you declare your function private, you can't use instance.function
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On 2011-06-06 14:45:22, Nilay Vaish wrote:
---
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changeset 30daf1dd5c91 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=30daf1dd5c91
description:
Ruby: Correctly set access permissions for directory entries
The access permissions for the directory entries are not being set
correctly.
This is because
Consider the following class declarations --
class A
{
public:
virtual void function() = 0;
};
class B : public A
{
private:
void function();
}
int main()
{
B b;
b.function();
}
Will this code compile correctly?
--
Nilay
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(Updated 2011-06-06 14:44:19.791924)
Review request for Default.
Summary
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(Updated 2011-06-06 14:45:22.384167)
Review request for Default.
Summary
---
We again had the same problem as yesterday, though it seems that all the
regression tests run up to completion. Any suggestions on resolving this?
scons: *** Found dependency cycle(s):
Internal Error: no cycle found for node
build/ALPHA_SE_MOESI_CMP_directory/params/DMA_Controller.hh
Does any one has any idea what a dependency cycles is? This is what
zizzer's log has.
scons: *** Found dependency cycle(s):
Internal Error: no cycle found for node
build/ALPHA_SE/params/L1Cache_Controller.hh (SCons.Node.FS.File instance
at 0x412a680) in state up_to_date
Internal Error: no
never seen this myself; I wonder if it's a bug in the version of
scons on zizzer (v0.98), as the machine I use has v.1.2.0.
It is a little strange that we're building params structs for Ruby
objects in ALPHA_SE though.
Steve
On Sat, Jun 4, 2011 at 6:41 AM, Nilay Vaish ni...@cs.wisc.edu wrote:
Does
changeset b9ba22cb23f2 in /z/repo/m5
details: http://repo.gem5.org/m5?cmd=changeset;node=b9ba22cb23f2
description:
SLICC: Remove machine name as prefix to functions
Currently, the machine name is appended before any of the functions
defined with in the sm files. This is not
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(Updated 2011-06-01 18:59:16.473427)
Review request for Default.
Summary
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(Updated 2011-06-01 18:59:39.117342)
Review request for Default.
Summary
---
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Review request for Default.
Summary
---
SLICC: Add a check function for State
. In fact, we
advise users to move to gem5.
--
Nilay
On Thu, 2 Jun 2011, huangyongbing wrote:
Hi.
I am currently using GEMS and Simics. So I care about whether the corresponding
codes are also updated in GEMS.
-Yongbing Huang
发件人： Nilay Vaish
发送时间： 2011-06-02 09:57:40
收件人： Nilay Vaish
On Sat, 28 May 2011, Nilay Vaish wrote:
Hi Brad
I am trying to complete the patch on functional accesses in Ruby. I came
across this problem while testing the patch for higher number of processors.
I am working with MESI CMP directory protocol right now. So I will describe
the problem
Hi Brad
I am trying to complete the patch on functional accesses in Ruby. I came
across this problem while testing the patch for higher number of
processors. I am working with MESI CMP directory protocol right now. So I
will describe the problem in its context.
Assume we are trying to
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(Updated 2011-05-27 11:41:44.345753)
Review request for Default.
Summary
On Fri, 6 May 2011, Beckmann, Brad wrote:
Hi Nilay,
Yeah, pulling the State into the Machine makes sense to me. If I
recall, my previous patch made it necessary that each machine included a
state_declaration (previously the state enum). More tightly integrating
the state to the machine
changeset a6363c870af6 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=a6363c870af6
description:
Trace: Remove the options trace-help and trace-flags
The options trace-help and trace-flags are no longer required. In there
place,
the options debug-help
Joel, I have pushed in the patch the removes the options trace-help and
trace-flags. But trace-start and trace-file work as before. You can use
them in conjunction with debug-flags.
--
Nilay
On Fri, 6 May 2011, Nilay Vaish wrote:
I was thinking og doing it since Nate is not around. I'll do
Korey, I don't think there will be any change in the simulation
performance. I am not sure about stats.
Brad, were the stats updated after you made the change?
--
Nilay
On Fri, 6 May 2011, Korey Sewell wrote:
Nilay,
can you explain the impact of that bug in terms of simulation
Koreay, DPRINTF already works in sm files. Use RubySlicc as the flag. You
can also use error() and assert() functions which have the following
prototypes --
void error(std::string msg);
void assert(bool condition);
--
Nilay
On Fri, 6 May 2011, Korey Sewell wrote:
I guess I should rephrase
I was thinking og doing it since Nate is not around. I'll do it soon.
--
Nilay
On Fri, 6 May 2011, Joel Hestness wrote:
Hey Nilay,
It looks like the tracing (debug) functionality is now working again,
but the M5 help message is still incorrect (and extremely misleading). For
instance,
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Review request for Default.
Summary
---
Ruby: Correctly set access
I am trying to compile m5 and the scons exits with errors.
Following is the compilation command --
scons -j 12 CXX=g++44 CC=gcc44 USE_MYSQL=False RUBY=True
build/ALPHA_SE_MESI_CMP_directory/m5.fast
and errors
In file included from
Nate, since I have provided the option USE_MYSQL=False, why should
mysql.hh even come in to picture?
--
Nilay
On Wed, 20 Apr 2011, nathan binkert wrote:
The solution is to #include base/types.hh in mysql.hh, but to be
honest, I'm not sure how this is even happening. Perhaps you need to
Is there a tester for testing the functionality of Ruby's memory
controller?
Thanks
Nilay
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().
Overall, I hope/think we can add functional access support without
requiring any more changes to the protocol specific .sm files beyond the
changeset: 8086:bf0335d98250 that I checked in a couple months ago.
Nilay Vaish wrote:
How would you use the function that is generated by SLICC
---
On 2011-04-13 14:29:01, Nilay Vaish wrote:
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(Updated
Nate, it seems one of your checkins from yesterday has a bug. I receive
the following message on executing any merculrial command.
*** failed to import extension style from ./util/style.py: invalid syntax
(file_types.py, line 143)
--
Nilay
___
On Sat, 16 Apr 2011, nathan binkert wrote:
What version of python are you using? It could be that that syntax
wasn't available until 2.5 and you're using something older. I can't
do anything about it right now because I'm about to leave on a hike.
Nate
Nate, it seems one of your checkins
().
Overall, I hope/think we can add functional access support without
requiring any more changes to the protocol specific .sm files beyond the
changeset: 8086:bf0335d98250 that I checked in a couple months ago.
Nilay Vaish wrote:
How would you use the function that is generated by SLICC
...@m5sim.org]
On Behalf Of Nilay Vaish
Sent: Tuesday, April 12, 2011 4:39 PM
To: Default
Subject: Re: [m5-dev] Review Request: Ruby: Add support for functional
accesses
Brad, can you take a look at the patch? I think we are now in position to
implement functional accesses for the PioPort.
--
Nilay
, visit:
http://reviews.m5sim.org/r/611/#review1113
---
On 2011-04-13 14:29:01, Nilay Vaish wrote:
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http
().
Overall, I hope/think we can add functional access support without
requiring any more changes to the protocol specific .sm files beyond the
changeset: 8086:bf0335d98250 that I checked in a couple months ago.
Nilay Vaish wrote:
How would you use the function that is generated by SLICC
---
On 2011-04-12 16:35:34, Nilay Vaish wrote:
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(Updated 2011-04-13 11:17:53.272247)
Review request for Default.
Summary
a protocol in which different directory
controllers may behave differently?
--
Nilay
-Original Message-
From: m5-dev-boun...@m5sim.org [mailto:m5-dev-boun...@m5sim.org]
On Behalf Of Nilay Vaish
Sent: Sunday, April 10, 2011 2:12 AM
To: m5-dev@m5sim.org
Subject: [m5-dev] AccessPermission
Brad, it seems like the m_Permission variable in AbstractEntry is not
being used at all. In order to get AccessPermission for a state, the
state_To_AccessPermission function needs to be called. Then, why have that
variable? And this would mean that CacheMemory has no idea about the
access
Brad, functional accesses work for the case when the only functional
accesses are allowed in the system. Currently I am working when the ratio
is 1:1 for functional and timing accesses.
I am facing some problem with the timing access right now, which should
work perfectly fine. Actually the
Brad, I figured out the error, so no need to respond to my previous mail.
--
Nilay
On Sat, 9 Apr 2011, Nilay Vaish wrote:
Brad, functional accesses work for the case when the only functional accesses
are allowed in the system. Currently I am working when the ratio is 1:1 for
functional
On Thu, 7 Apr 2011, Gabriel Michael Black wrote:
When you say this is portable, what do you mean? Portable between compilers?
We usually use gcc, but we have at least partial support for other compilers.
I think this is necessary on some platforms.
Gabe
I would still root for using
The problem is that LONG_BITS is 31, ie std::numeric_limitslong::digits
returns 31 and not 32 which is what the writer expected.
--
Nilay
From: koreylsew...@gmail.com [mailto:koreylsew...@gmail.com] On Behalf Of
Korey Sewell
Sent: Tuesday, April 05, 2011 7:14 AM
To: Beckmann, Brad
Subject:
On Thu, 7 Apr 2011, Gabriel Michael Black wrote:
Quoting Nilay Vaish ni...@cs.wisc.edu:
On Thu, 7 Apr 2011, Gabriel Michael Black wrote:
When you say this is portable, what do you mean? Portable between
compilers? We usually use gcc, but we have at least partial support for
other compilers
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src/mem/ruby/network/simple/PerfectSwitch.cc
On Wed, 6 Apr 2011, Korey Sewell wrote:
A few comments:
(1) Using uint64_t seems like a quick, interim solution. But I still
haven't grasped why we have the 31st bit problem, but we don't have
the 63rd bit problem as well?
I think if you use unsigned long, in place of long, the code would
On 2011-03-31 22:08:21, Brad Beckmann wrote:
This looks great, I just have a few minor suggestions below.
It seems like the next step is to figure out how to deal with functional
accesses not succeeding in the CPUs and devices.
Nilay Vaish wrote:
Brad, I would make the changes
AbstractMemory.py file.
- Nilay
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On 2011-04-02 11:42:47, Nilay Vaish wrote
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(Updated 2011-04-04 06:22:20.346203)
Review request for Default.
Summary
---
On Fri, 1 Apr 2011, Korey Sewell wrote:
That's a good point.
I'll coordinate with Nilay offline to get him the right image.
Nilay, from your previous optimizations trials, where did you see most of
the simulation time being sent at?
On Fri, Apr 1, 2011 at 4:48 PM, Ali Saidi sa...@umich.edu
On 2011-03-31 22:08:21, Brad Beckmann wrote:
This looks great, I just have a few minor suggestions below.
It seems like the next step is to figure out how to deal with functional
accesses not succeeding in the CPUs and devices.
Nilay Vaish wrote:
Brad, I would make the changes
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On 2011-03-31 20:44:17, Nilay Vaish wrote
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On 2011-03-31 20:44:17, Nilay Vaish wrote
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(Updated 2011-04-02 11:42:47.195024)
Review request for Default.
Summary
---
://reviews.m5sim.org/r/611/#review1082
---
On 2011-03-31 20:44:17, Nilay Vaish wrote:
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I am wondering what's the need of the file Protocol.hh, I removed it from
different in the protocol independent part of Ruby. I also removed the
file standard_1level_CMP-protocol.sm from the MOESI_hammer.slicc.
Everything compiles perfectly. I am not sure what the requirement is.
--
Nilay
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Ship it!
Is context Id being used any where?
- Nilay
On 2011-03-31
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Ship it!
- Nilay
On 2011-03-31 12:21:22, Lisa Hsu wrote:
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src/mem/ruby/system/WireBuffer.hh
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Ship it!
- Nilay
On 2011-03-31 12:20:59, Lisa Hsu wrote:
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Ship it!
I hope you have tested the existing protocols with these
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Ship it!
Lisa, the changes look fine to me. Just make sure that all the
---
On 2011-03-30 16:19:26, Nilay Vaish wrote:
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(Updated
On 2011-03-31 14:22:16, Nilay Vaish wrote:
I hope you have tested the existing protocols with these changes.
Lisa Hsu wrote:
Yes - MOESI_[CMP_[directory|token]|hammer] all compile and run -l 1000 -n
4 on the Ruby Tester. Since no logic has changed (for all my Ruby changes),
I
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(Updated 2011-03-31 20:44:17.499794)
Review request for Default.
Summary
---
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(Updated 2011-03-30 16:19:26.551926)
Review request for Default.
Summary
---
On Tue, 29 Mar 2011, Nilay Vaish wrote:
Brad, I have posted on the review board my current implementation for
supporting functional accesses in Ruby. This is untested and is mainly meant
for furthering the discussions. I have some questions for you --
1. How do we inform the other end
Korey, I do not have the FftBase32 benchmark. Is it possible for you to
run the simulation with one of the following benchmarks --
IScsiInitiator, IScsiTarget, MutexTest, NetperfMaerts, NetperfStream,
NetperfStreamNT, NetperfStreamUdp, NetperfUdpLocal, Nfs, NfsTcp,
Nhfsstone, Ping,
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Review request for Default.
Summary
---
Ruby: Add support for functional
as well. How can
physical memory be accessed from RubyPort?
--
Nilay
On Tue, 29 Mar 2011, Nilay Vaish wrote:
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changeset 1333bd6cc2eb in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=1333bd6cc2eb
description:
Config: Import math in MI_example.py
diffstat:
configs/ruby/MI_example.py | 1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diffs (11 lines):
diff -r 832ae3727c2b
I pushed in patch that imports math in MI_example.py
--
Nilay
On Mon, 28 Mar 2011, Cron Daemon wrote:
* build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby
FAILED!
* build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby
FAILED!
*
I will try to bisect this.
--
Nilay
On Wed, 23 Mar 2011, Arkaprava Basu wrote:
Hi Lisa and Nilay,
Thanks for the response. Following is the tip of my repo
changeset: 8174:e21f6e70169e
tag: tip
user:Nilay Vaishni...@cs.wisc.edu
date:Tue Mar 22 06:41:54 2011
here
Exiting @ tick 14536941 because Ruby Tester completed
On Wed, 23 Mar 2011, Nilay Vaish wrote:
I will try to bisect this.
--
Nilay
On Wed, 23 Mar 2011, Arkaprava Basu wrote:
Hi Lisa and Nilay,
Thanks for the response. Following is the tip of my repo
changeset: 8174:e21f6e70169e
changeset e21f6e70169e in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=e21f6e70169e
description:
Ruby: Remove CacheMsg class from SLICC
The goal of the patch is to do away with the CacheMsg class currently
in use
in coherence protocols. In place of
On Tue, 22 Mar 2011, Gabriel Michael Black wrote:
The two issues below are copied from ARM_FS, but other targets had the same
problems.
These errors are making the build fail.
build/ARM_FS/cpu/testers/networktest/networktest.cc: In member function 'void
changeset c1c6f36e118e in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=c1c6f36e118e
description:
SLICC: Remove WakeUp* import calls from ast/__init__.py
I had recently committed a patch that removed the WakeUp*.py files from
the
slicc/ast directory. I
I had committed an error in one of the my recent patches. I have committed
a patch that should fix this error.
--
Nilay
On Sun, 20 Mar 2011, Cron Daemon wrote:
See /z/m5/regression/regress-2011-03-20-03:00:01 for details.
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(Updated 2011-03-20 10:53:10.248023)
Review request for Default.
Summary
On Sat, 19 Mar 2011, Nilay Vaish wrote:
On Fri, 18 Mar 2011, Lisa Hsu wrote:
What's going on with this patch? I don't believe it's been committed but
it
seems like it should. I've also got some patches waiting behind this
because they used to touch CacheMsg and I don't want to mess Nilay
changeset b043c0efa024 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=b043c0efa024
description:
Ruby: Convert AccessModeType to RubyAccessMode
This patch converts AccessModeType to RubyAccessMode so that both the
protocol dependent and independent code
changeset 5955406f7ed0 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=5955406f7ed0
description:
Ruby: Convert CacheRequestType to RubyRequestType
This patch converts CacheRequestType to RubyRequestType so that both the
protocol dependent and independent
changeset f3d1493787d4 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=f3d1493787d4
description:
SLICC: Remove the keyword wake_up_all_dependents
In order to add stall and wait facility for protocols, a keyword
wake_up_all_dependents was introduced. This
changeset 099771c7725d in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=099771c7725d
description:
SLICC: Remove the keyword wake_up_dependents
In order to add stall and wait facility for protocols, a keyword
wake_up_dependents was introduced. This patch
changeset 9a6a02a235f1 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=9a6a02a235f1
description:
SLICC: Remove external_type for structures
In SLICC, in order to define a type a data type for which it should not
generate any code, the keyword
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Review request for Default.
Summary
---
Ruby: Convert CacheRequestType to
On Fri, 18 Mar 2011, Lisa Hsu wrote:
What's going on with this patch? I don't believe it's been committed but it
seems like it should. I've also got some patches waiting behind this
because they used to touch CacheMsg and I don't want to mess Nilay up, so
I've been waiting to serialize behind
On Fri, 11 Mar 2011, Steve Reinhardt wrote:
Thanks for the explanation... I was expecting to see a loop on
L1DcacheMemory like before and I missed the one on system.ruby.network.
In the short run, I think the easiest way to break the cycle is to have the
network take the RubySystem object as
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Review request for Default.
Summary
---
SLICC: Remove the keyword
On Sat, 12 Mar 2011, Steve Reinhardt wrote:
On Sat, Mar 12, 2011 at 1:34 PM, Nilay Vaish ni...@cs.wisc.edu wrote:
On Fri, 11 Mar 2011, Steve Reinhardt wrote:
Thanks for the explanation... I was expecting to see a loop on
L1DcacheMemory like before and I missed the one
self.getCCObject()
On Wed, Mar 9, 2011 at 2:34 PM, Nilay Vaish ni...@cs.wisc.edu wrote:
Creating root
Creating system.physmem
Creating system
Creating system.l1_cntrl0.L1DcacheMemory
Creating system.ruby
Creating system.ruby.network
Creating system.ruby.network.topology
Creating
previous example, not less...
On Thu, Mar 10, 2011 at 5:36 AM, Nilay Vaish ni...@cs.wisc.edu wrote:
Steve, here is the output after putting in the print statements.
Creating root params
Creating root
Done creating root
Creating system params
Creating system
Done creating system
Creating
I made some changes to MESI_CMP_directory.py and those changes are
reflected in the output. The l1 and l2 controllers are now being attached
to ruby instead of system.
Nilay
On Thu, 10 Mar 2011, Nilay Vaish wrote:
I had originally put a print statement in getCCObject(), so using the word
As I understand, we use Python objects to initialize C++ objects. Is it
possible to pass a pointer to an array (dynamic sized) from Python to C++?
Thanks
Nilay
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