[gem5-dev] changeset in gem5: sparc: merge regr. updates w/last update

changeset a81aefcef6f9 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=a81aefcef6f9 description: sparc: merge regr. updates w/last update diffstat: src/arch/sparc/isa/decoder.isa | 6 +- src/arch/sparc/isa/formats/branch.isa | 5 ++ src/arch/s

[gem5-dev] changeset in gem5: sparc: update simple cpu regressions

changeset ce61b7a13407 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=ce61b7a13407 description: sparc: update simple cpu regressions use stats file generated by zizzer diffstat: tests/quick/00.hello/ref/sparc/linux/simple-atomic/stats.txt

Re: [gem5-dev] Cron /z/m5/regression/do-regression quick

I was late in updating the repository. I think this may have happened since I was running stuff on zizzer while the regressions were loading up. What's the method of choice for rerunning the do-regression script? Also, when updating the simple cpu regressions, I had to "hg merge" the changesets,

[gem5-dev] Ruby: Token Coherence and Functional Access

Brad, in the token coherence protocol, the l2 cache controller moves from state O to I and sends data to the memory. I think this particular transition is may pose a problem in enabling functional accesses for the protocol. The problem, I think, is that both the directory and the cache controll

Re: [gem5-dev] Cron /z/m5/regression/do-regression quick

Merging the regression output (mainly stats) is probably not going to do what you want, so if those files had to be merged then that's probably part of the problem. Gabe On 06/10/11 01:16, Korey Sewell wrote: > I was late in updating the repository. I think this may have happened since > I was ru

Re: [gem5-dev] Cron /z/m5/regression/do-regression quick

The regression runs as the 'm5test' user; if you tried to run under /z/m5/regression as yourself or as root then it's probably running into file/dir permissions problems. I'll delete the build dir so we shouldn't run into this again. Usually it's best just to run the regressions in your own direc

[gem5-dev] changeset in gem5: o3: missing newlines on some dprintfs

changeset ce8b9a250021 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=ce8b9a250021 description: o3: missing newlines on some dprintfs diffstat: src/cpu/o3/commit_impl.hh | 4 ++-- src/cpu/o3/fetch_impl.hh | 2 +- src/cpu/o3/lsq_impl.hh| 6 +++--- src/cpu/o

[gem5-dev] changeset in gem5: sparc: update o3 regressions

changeset ac4da9f8ea80 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=ac4da9f8ea80 description: sparc: update o3 regressions diffstat: tests/quick/02.insttest/ref/sparc/linux/o3-timing/simerr| 1 - tests/quick/02.insttest/ref/sparc/linux/o3

[gem5-dev] changeset in gem5: sparc: don't use directcntrl branch flag

changeset 9bb24e6edc35 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=9bb24e6edc35 description: sparc: don't use directcntrl branch flag this flag is only used for early branch resolution in the O3 model (of pc-relative branches) but this isnt cleanly

Re: [gem5-dev] changeset in gem5: sparc: don't use directcntrl branch flag

This was working at some point. What happened? Ali Sent from my ARM powered device On Jun 10, 2011, at 9:14 PM, Korey Sewell wrote: > changeset 9bb24e6edc35 in /z/repo/gem5 > details: http://repo.gem5.org/gem5?cmd=changeset;node=9bb24e6edc35 > description: >sparc: don't use directcntrl br

Re: [gem5-dev] Review Request: SLICC: Add a check function for State Machine

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/723/#review1320 --- src/mem/slicc/symbols/StateMachine.py

Re: [gem5-dev] changeset in gem5: sparc: don't use directcntrl branch flag

I dont think this was ever working for sparc. In changeset 77d12d8f7971 (2 days ago?), I added all the sparc control flags so I'm pretty sure just having the annotation of branch/no branch was new for sparc. If you are referring to the o3 early branch resolution, I didnt touch that, it's just tha

Re: [gem5-dev] Review Request: cpus/isa: add a != operator for pcstate

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/738/ --- (Updated 2011-06-10 22:33:40.877518) Review request for Default, Ali Saidi, Gabe Bl

Re: [gem5-dev] Review Request: cpus/isa: add a != operator for pcstate

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/738/ --- (Updated 2011-06-10 22:38:50.780875) Review request for Default, Ali Saidi, Gabe Bl

Re: [gem5-dev] Review Request: inorder/dtb: make sure DTB translate correct address

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/743/ --- (Updated 2011-06-10 22:52:04.462095) Review request for Default, Ali Saidi, Gabe Bl

Re: [gem5-dev] Review Request: inorder/dtb: make sure DTB translate correct address

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/743/#review1321 --- src/arch/alpha/tlb.cc