[m5-dev] changeset in m5: Fault: Forgot to refresh to grab these header g...

changeset 57dec8c3e03f in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=57dec8c3e03f description: Fault: Forgot to refresh to grab these header guard updates. diffstat: src/sim/fault_fwd.hh | 6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-) diffs (20 lines):

[m5-dev] changeset in m5: imported patch regression_updates

changeset 459db0aebcf7 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=459db0aebcf7 description: imported patch regression_updates diffstat: tests/long/50.vortex/ref/alpha/tru64/inorder-timing/config.ini |5 +- tests/long/50.vortex/ref/alpha/tru64/inorder-timing/si

[m5-dev] changeset in m5: inorder: fault handling

changeset 6fa135943891 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=6fa135943891 description: inorder: fault handling Maintain all information about an instruction's fault in the DynInst object rather than any cpu-request object. Also, if there is a fa

[m5-dev] changeset in m5: inorder: add a fetch buffer to fetch unit

changeset 87a6f2ed585a in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=87a6f2ed585a description: inorder: add a fetch buffer to fetch unit Give fetch unit it's own parameterizable fetch buffer to read from. Very inefficient (architecturally and in simulat

[m5-dev] changeset in m5: inorder: pcstate and delay slots bug

changeset 1ffb11f8e8bb in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=1ffb11f8e8bb description: inorder: pcstate and delay slots bug not taken delay slots were not being advanced correctly to pc+8, so for those ISAs we 'advance()' the pcstate one more ti

[m5-dev] changeset in m5: inorder: overload find-req fn

changeset fa81553d67ea in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=fa81553d67ea description: inorder: overload find-req fn no need to have separate function name findSplitRequest, just overload the function diffstat: src/cpu/inorder/resources/cache_unit.cc

[m5-dev] changeset in m5: inorder: implement separate fetch unit

changeset 303293e1517f in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=303293e1517f description: inorder: implement separate fetch unit instead of having one cache-unit class be responsible for both data and code accesses, separate code that is just for f

[m5-dev] changeset in m5: inorder: cache port blocking

changeset 6e810a479c3e in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=6e810a479c3e description: inorder: cache port blocking set the request to false when the cache port blocks so we dont deadlock. also, comment out the outstanding address list sanity che

[m5-dev] changeset in m5: inorder: stage width as a python parameter

changeset ba84e1da98a7 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=ba84e1da98a7 description: inorder: stage width as a python parameter allow the user to specify how many instructions a pipeline stage can process on any given cycle (stageWidth...i.e.b

[m5-dev] changeset in m5: inorder: activity tracking bug

changeset 3b4d595397fb in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=3b4d595397fb description: inorder: activity tracking bug Previous code was marking CPU activity on almost every cycle due to a bug in tracking the status of pipeline stages. This disab

[m5-dev] changeset in m5: inorder: change skidBuffer to list instead of q...

changeset c9286580867a in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=c9286580867a description: inorder: change skidBuffer to list instead of queue manage insertion and deletion like a queue but will need access to internal elements for future changes

[m5-dev] changeset in m5: inorder: multi-issue branch resolution

changeset 9b559768152b in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=9b559768152b description: inorder: multi-issue branch resolution Only execute (resolve) one branch per cycle because handling more than one is a little more complicated diffstat: sr

[m5-dev] changeset in m5: inorder: pipe. stage inst. buffering

changeset 87f4fd9a2760 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=87f4fd9a2760 description: inorder: pipe. stage inst. buffering use skidbuffer as only location for instructions between stages. before, we had the insts queue from the prior stage and t

[m5-dev] changeset in m5: Mem, X86: Make the IO bridge pass APIC messages ...

changeset 19beb0676222 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=19beb0676222 description: Mem,X86: Make the IO bridge pass APIC messages back towards the CPU. diffstat: configs/example/fs.py | 9 - 1 files changed, 8 insertions(+), 1 deletions(-) diffs

[m5-dev] changeset in m5: Fault: Rename sim/fault.hh to fault_fwd.hh to d...

changeset d3e6ebcccabf in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=d3e6ebcccabf description: Fault: Rename sim/fault.hh to fault_fwd.hh to distinguish it from faults.hh. diffstat: src/arch/alpha/tlb.hh| 2 +- src/arch/arm/table_walker.hh | 2 +- src/ar

Re: [m5-dev] Copyrights

> A lot of the copyrights on the inorder cpu files are (c) 2007 MIPS. > > If I've made a substantial change to a particular file, do I add another > copyright to that file (say (c) 2010 UofM), or how does that type of thing > get handled? Yes, you should. Follow what you see in other files. If y

Re: [m5-dev] Review Request: Fault: Rename sim/fault.hh to fault_fwd.hh to distinguish it from faults.hh.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/466/#review835 --- Ship it! src/sim/fault_fwd.hh

[m5-dev] Review Request: Fault: Rename sim/fault.hh to fault_fwd.hh to distinguish it from faults.hh.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/466/ --- Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan Binke

Re: [m5-dev] changeset in m5: O3: Fix some variable length instruction issues...

I went back and checked this out, and this was actually fine. I would have still liked to have determined that before it went in, but the problem I had with it was misguided. Good work ARM folks, and sorry for the hassle. Gabe On 01/18/11 15:08, Gabe Black wrote: > I'm pretty sure I mentioned twi

[m5-dev] changeset in m5: Config: Keep track of uncached and cached ports...

changeset 189b9b258779 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=189b9b258779 description: Config: Keep track of uncached and cached ports separately. This makes sure that the address ranges requested for caches and uncached ports don't conflict wi

Re: [m5-dev] Review Request: inorder: pcstate and delay slots bug

Getting all the ISA_HAS_DELAY_SLOTs out the code is a worthwhile goal that I'd like to take another stab at in the near term (more than likely when I get the next ISA working in InOrder). It seems as if the PCState had just some "default target" member function or something that could be called th

Re: [m5-dev] Review Request: inorder: pcstate and delay slots bug

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/449/#review834 --- Ship it! This looks better. It would be even better still if we could get

[m5-dev] 20 hour long regression test

So how do people feel about this? bzip2 in x86 on O3 takes more than 20 hours to run. Should that be part of the regressions or not? I have it ready to go if that's acceptable, but to me it seems too long. Gabe On 02/01/11 17:30, Gabe Black wrote: > Normally I wouldn't send stats updates out for

Re: [m5-dev] PerfectSwitch

On Thu, 3 Feb 2011, Nilay Vaish wrote: On Thu, 3 Feb 2011, Nilay Vaish wrote: On Thu, 3 Feb 2011, Nilay Vaish wrote: Hi Brad, On Thu, 3 Feb 2011, Beckmann, Brad wrote: Hi Nilay, Yes, you could make such an optimization, but you want to be careful not to introduce starvation. You want t

Re: [m5-dev] PerfectSwitch

On Thu, 3 Feb 2011, Nilay Vaish wrote: On Thu, 3 Feb 2011, Nilay Vaish wrote: Hi Brad, On Thu, 3 Feb 2011, Beckmann, Brad wrote: Hi Nilay, Yes, you could make such an optimization, but you want to be careful not to introduce starvation. You want to make sure that newly arriving messages

Re: [m5-dev] PerfectSwitch

On Thu, 3 Feb 2011, Nilay Vaish wrote: Hi Brad, On Thu, 3 Feb 2011, Beckmann, Brad wrote: Hi Nilay, Yes, you could make such an optimization, but you want to be careful not to introduce starvation. You want to make sure that newly arriving messages are not always prioritized over previous

Re: [m5-dev] Fwd: Questions about FS Support using Ruby's Memory Model

I'd like to follow up on this question a bit. Does anyone have tests for Ruby in FS mode? I'd like to move from the memtester CPU in SE mode and see if we can get some real benchmarks running in FS mode. As stated before, the comments in ruby_fs.py dont sound too promising: "# currently ruby fs o

Re: [m5-dev] PerfectSwitch

Hi Brad, On Thu, 3 Feb 2011, Beckmann, Brad wrote: Hi Nilay, Yes, you could make such an optimization, but you want to be careful not to introduce starvation. You want to make sure that newly arriving messages are not always prioritized over previously stalled messages. Could you avoid lo

Re: [m5-dev] PerfectSwitch

Hi Nilay, Yes, you could make such an optimization, but you want to be careful not to introduce starvation. You want to make sure that newly arriving messages are not always prioritized over previously stalled messages. Could you avoid looping through all message buffers by creating a list of

Re: [m5-dev] PerfectSwitch

On Thu, 3 Feb 2011, Nilay Vaish wrote: I implemented this approach. But it did not improve the performance. So I tried to explore what could be the cause. The function PerfectSwitch::wakeup() contains three loops. loop on number of virtual networks loop on number of incoming links loop ti

Re: [m5-dev] Review Request: inorder: pcstate and delay slots bug

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/449/ --- (Updated 2011-02-03 09:59:35.112333) Review request for Default, Ali Saidi, Gabe Bl

[m5-dev] Copyrights

A lot of the copyrights on the inorder cpu files are (c) 2007 MIPS. If I've made a substantial change to a particular file, do I add another copyright to that file (say (c) 2010 UofM), or how does that type of thing get handled? -- - Korey ___ m5-dev m

Re: [m5-dev] PerfectSwitch

On Thu, 27 Jan 2011, Steve Reinhardt wrote: On Thu, Jan 27, 2011 at 5:24 AM, Nilay Vaish wrote: I tested my hypothesis yesterday. About 90% of the messages have destination count = 1. I think, for such messages, we should avoid going through the entire routing table. Instead, we should als

[m5-dev] Review Request: X86: Don't read in dest regs if all bits are replaced.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/464/ --- Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan Binke

[m5-dev] Cron /z/m5/regression/do-regression quick

* build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing-ruby FAILED! scons: *** Source `tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt' not found, needed by target `build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-