This is done. User-name pdudnik.
On Tue, Jun 1, 2010 at 1:47 PM, nathan binkert n...@binkert.org wrote:
I have four diffs that remove code from mem/gems_common that I'd like
to get reviewed. I'd like to use reviewboard, but not all of the
necessary people are there.
I'd appreciate it if
Hi Nate,
Just to clarify: what script do you mean?
On Tue, May 4, 2010 at 6:28 PM, nathan binkert n...@binkert.org wrote:
We would like to run memtest with x86 FS. Can anyone tell us how to do
this?
It should be exactly the same as running memtest in ALPHA_SE. Looking
at the script, it
Sorry Nate,
That was from a while ago and wasn't meant to be committed. I take the
blame.
Polina
On Sat, Jan 23, 2010 at 12:31 PM, nathan binkert n...@binkert.org wrote:
I was about to commit my change to the style hook, but I just wasted
two hours trying to figure out why my fix was no
Hi Nate,
Just letting you know that we saw the failures as well as your email. We'll
be working on it.
Polina
On Sat, Jan 23, 2010 at 11:50 AM, nathan binkert n...@binkert.org wrote:
Derek/Polina,
Can you two fix up the regeression tests?
Thanks,
Nate
On Sat, Jan 23, 2010 at 12:08
changeset d480ef5b9028 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=d480ef5b9028
description:
Atomics bug fix
diffstat:
2 files changed, 7 insertions(+), 5 deletions(-)
src/mem/ruby/system/Sequencer.cc | 11 +++
src/mem/slicc/symbols/StateMachine.cc |
Hi Brad,
Yes, the new atomic support also requires the sequencer to have a pointer to
the cache controller. The code that is in the repository now is a hack of
the slicc protocol code generator. The code is inserted in the middle of the
wakeup function in the cache controller. The new uncommited
protocols, and one with MOESI. Since memtest uses MI
and doesn't issue DMA or atomic requests, the stats should be
unaffected. Are we sure that it was one of those changes that altered
the stats?
-Derek
On Sun, Oct 18, 2009 at 7:18 PM, Polina Dudnik pdud...@gmail.com wrote:
Nate,
So my
Thanks Nate, I didn't know about it. I will read about it.
On Mon, Oct 19, 2009 at 5:13 PM, nathan binkert n...@binkert.org wrote:
Can I recommend the mercurial bisect extension? It's totally designed
for doing this exact thing.
Nate
On Mon, Oct 19, 2009 at 3:10 PM, Polina Dudnik pdud
...@m5sim.org [mailto:m5-dev-boun...@m5sim.org] On
Behalf
Of Polina Dudnik
Sent: Sunday, October 18, 2009 11:10 AM
To: M5 Developer List
Subject: Re: [m5-dev] Cron
m5t...@zizzer/z/m5/regression/do-regression--scratch all
Thanks Brad,
Nate, let's see if it works after this check
don't think I changed the stats, and even if I did, the test then would
have failed for when I haven't yet applied my changes.
So,
I can't say I know why the test fails, I don't.
Polina
On Sun, Oct 18, 2009 at 2:41 PM, Polina Dudnik pdud...@gmail.com wrote:
Right,
I'm not sure if it does make
Nate, I can't fix it just now because I am busy with other things but as
soon as I can I will.
I actually have to look into it because I am not sure what is causing the
cycle count change because the bug fix was in general for DMA and the tester
doesn't test DMA, so as soon as I get a chance I
Nate,
Can you please go into src/mem/ruby/debug/config.rb and find debug_ss and
set it to none. This is Somayeh's debugging trace.
Polina
On Tue, Sep 22, 2009 at 2:50 PM, nathan binkert n...@binkert.org wrote:
When I run the regression tests, I get a file called debug_ss in my
directory that
Ruby must be failing due to stats changes in MOESI since the recent patch.
On Sun, Sep 20, 2009 at 5:17 PM, Steve Reinhardt ste...@gmail.com wrote:
I did a manual run just to kick things off, and it looks like there
are some small stats changes in MIPS_SE as well as the ruby problems.
Korey,
On Mon, Sep 14, 2009 at 6:27 PM, nathan binkert n...@binkert.org wrote:
You are right and that's probably more my mistake than Dereks. What
happens
is that mercurial crashes whenever it would detect a white-space issue.
So,
for me to make a patch or commit I hacked the style file, and
On Mon, Sep 14, 2009 at 6:07 PM, Gabriel Michael Black
gbl...@eecs.umich.edu wrote:
I notice you have several patches that change around style.py. You
probably shouldn't have that in a commit ready patch, and you
shouldn't change it back and forth throughout the series.
You are right and
On Fri, Sep 11, 2009 at 7:57 PM, nathan binkert n...@binkert.org wrote:
I finally read this diff. My comments are inline. In the future,
please use hg email which is found in the patchbomb extension. It
makes it far easier to comment on diffs since I can just then reply to
the e-mail
Nate,
Did you get a chance to look at it? Thanks.
Polina
On Tue, Sep 1, 2009 at 9:30 AM, Nathan Binkert n...@binkert.org wrote:
I will read it today. There are some issues. Please be a bit more patient.
On Sep 1, 2009, at 8:15, Polina Dudnik pdud...@gmail.com wrote:
I will push
I will push this if nobody has any objections.
On Mon, Aug 31, 2009 at 4:48 PM, Polina Dudnik pdud...@gmail.com wrote:
Hi,
I am attaching a small patch that enables the passing of the ruby config
file as a parameter. So, multiple protocols can be tested without manually
modifying
Thank you. No rush.
On Tue, Sep 1, 2009 at 9:30 AM, Nathan Binkert n...@binkert.org wrote:
I will read it today. There are some issues. Please be a bit more patient.
On Sep 1, 2009, at 8:15, Polina Dudnik pdud...@gmail.com wrote:
I will push this if nobody has any objections.
On Mon, Aug
Hi,
I am attaching a patch that allows memtest.cc to issue DMA requests.
The changes include:
1. Add bool use_dma and percent_dma to MemTest.py
2. Fix if O3CPU SCons issue that Somayeh had
3. Add percent_dma and use_dma to memtest.hh and memtest.cc
4. Added generation of dma requests to
Thanks. I didn't know that and I was wondering how I could do that.
On Tue, Sep 1, 2009 at 10:33 AM, Steve Reinhardt ste...@gmail.com wrote:
BTW, if you use the '-e' or '-m' options to qnew or qref you can
enter/edit a commit message for a patch which will get used when you
actually commit...
On Tue, Sep 1, 2009 at 10:29 AM, Steve Reinhardt ste...@gmail.com wrote:
Before we worry about the details of this patch, I have a higher-level
question: why do we need a separate DMA request type and port at all?
On the M5 side, we've gotten by just fine so far with ReadReq and
WriteReq, and
On Tue, Sep 1, 2009 at 11:16 AM, Steve Reinhardt ste...@gmail.com wrote:
On Tue, Sep 1, 2009 at 9:09 AM, Derek Howerderek.ho...@gmail.com wrote:
On Tue, Sep 1, 2009 at 10:29 AM, Steve Reinhardtste...@gmail.com
wrote:
Before we worry about the details of this patch, I have a higher-level
Hi,
I am attaching a small patch that enables the passing of the ruby config
file as a parameter. So, multiple protocols can be tested without manually
modifying the config_file name.
Comments are welcome.
Polina
config_as_param
Description: Binary data
Hi,
I have a question: why is it that the access_size is first calculated as
random() % 4 and then reset to zero before issuing the request in
MemTest::tick?
Thank you.
Polina
___
m5-dev mailing list
m5-dev@m5sim.org
I see. It seems like it would be more appropriate to have tester test larger
requests because we are getting a false sense of correctness by running the
test. It tests the protocol logic well but not the data correctness.
Also, is there a maximum on the size of the m5 request? I would like to
Sorry, I yet again have one push for two different things. I also modified
state machine besides fixing the licenses. Nate, I am not sure what the
licenses for getopt should be.
On Thu, Jul 23, 2009 at 11:28 AM, Polina Dudnik pdud...@gmail.com wrote:
changeset 82ee4a597908 in /z/repo/m5
Yes, the tester uses it although it doesn't have to. Is that a problem?
On Thu, Jul 23, 2009 at 9:27 PM, nathan binkert n...@binkert.org wrote:
Sorry, I yet again have one push for two different things. I also
modified
state machine besides fixing the licenses. Nate, I am not sure what the
Hi Nate,
We saw it. However, the day before the tester passed and we didn't check in
anything in between the pass and the fail. One of the reasons it might be
failing is because I changed the StateMachine to reorder the queues. That
may have changed the timing and the stats don't correspond now.
Hi,
I would like to test atomics in ruby.
The regression tester contains a test_atomic binary in
/gem5/regression/test-progs/m5threads/bin/sparc/linux.
I try to run the tester by issuing:
build/SPARC_SE/m5.fast -d
On Tue, Jul 14, 2009 at 3:07 PM, Daniel Sanchez sanch...@stanford.eduwrote:
Polina Dudnik wrote:
Hi,
I would like to test atomics in ruby.
The regression tester contains a test_atomic binary in
/gem5/regression/test-progs/m5threads/bin/sparc/linux.
I try to run the tester
On Tue, Jul 14, 2009 at 3:21 PM, Daniel Sanchez sanch...@stanford.eduwrote:
Polina Dudnik wrote:
On Tue, Jul 14, 2009 at 3:07 PM, Daniel Sanchez sanch...@stanford.edu
mailto:sanch...@stanford.edu wrote:
Polina Dudnik wrote:
Hi,
I would like to test atomics
On Tue, Jul 14, 2009 at 3:40 PM, Daniel Sanchez sanch...@stanford.eduwrote:
Polina Dudnik wrote:
On Tue, Jul 14, 2009 at 3:21 PM, Daniel Sanchez sanch...@stanford.edu
mailto:sanch...@stanford.edu wrote:
Polina Dudnik wrote:
On Tue, Jul 14, 2009 at 3:07 PM
Hi,
As far as I know DRAMsim has already been integrated into M5. However, it
probably uses the old memory model and not ruby. We would like to integrate
DRAMsim into Ruby+M5. Can anyone comment on suggestions/advice from the M5
side? Would it be better to adjust what is already in M5 or start
Hi,
I am working on a store buffer to couple with Ruby in order to simulate TSO.
As far as I know, the TSOTool described in *TSOtool**: A Program for
Verifying Memory Systems Using the Memory Consistency Model *has not been
open sourced. There is a different tso checker which comes as part of
Hi,
I was pointed to a store buffer in the M5 OOO model and it is unified with
LSQ. As I am writing a store buffer, a natural question is: should it be
unified with an LSQ? In general, I think that parallelization would be made
easier if as many structures as possible were decoupled. I also think
changeset 91e31308be1e in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=91e31308be1e
description:
ruby: Remove transactional access types (e.g. LD_XACT) from
CacheRequestType
1. Modified enumeration
2. Also modified profiler
3. Remove
changeset 92318648212f in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=92318648212f
description:
ruby: decommission code
1. Set.* and BigSet.* are replaced with OptBigSet.* which was renamed
Set.*
2. Decomissioned all bloom filters
3.
, Polina Dudnik pdud...@gmail.com wrote:
Yep, got it. I may have been looking at the wrong invoke() before.
Polina
On Sun, Mar 22, 2009 at 7:35 PM, Polina Dudnik pdud...@gmail.com wrote:
I see. I will look at that because it's weird that when I boot the disk it
complains about unhandled MMU
(data, 5,0)
should be vector. If that fails take a look at the sparc architecture
manual and see what the specifics of a write to that ASI as supposed
to do.
Ali
On Mar 23, 2009, at 4:06 PM, Polina Dudnik wrote:
So Ali,
So far the reason why it woudn't boot is because it tlb.cc under case
, but in reality there are actually multiple CPUs. All
the code I wrote for threads/cpus as far as the OS/hypervisor layer is
concerned assumed this (e.g. take the thread context ID % 4 to get the
CPU/thread id.
Ali
On Mar 22, 2009, at 2:47 PM, Polina Dudnik wrote:
So, you just don't allow multiple
at 5:39 PM, Ali Saidi sa...@umich.edu wrote:
number of CPUs as I've defined them. If you wanted 8 contexts you
would pass -n 8
Ali
On Mar 22, 2009, at 5:09 PM, Polina Dudnik wrote:
So, when I pass -n 2, shouldn't there be 8 thread contexts: 4 for
each processor? Or is -n 2 is the number
something?
Where is the FastDataAccessMMUMiss actually handled?
Polina
On Sun, Mar 22, 2009 at 5:39 PM, Ali Saidi sa...@umich.edu wrote:
number of CPUs as I've defined them. If you wanted 8 contexts you
would pass -n 8
Ali
On Mar 22, 2009, at 5:09 PM, Polina Dudnik wrote:
So, when I pass -n 2
(?) which rexecutes the
instruction and away it goes.
Ali
On Mar 22, 2009, at 6:11 PM, Polina Dudnik wrote:
Ali,
I traced the FastDataAccessMMUMiss and it seems that the fault
triggers advancePC function, which calls predecode.reset() and
that's about it. predecode.reset() doesn't seem
Yep, got it. I may have been looking at the wrong invoke() before.
Polina
On Sun, Mar 22, 2009 at 7:35 PM, Polina Dudnik pdud...@gmail.com wrote:
I see. I will look at that because it's weird that when I boot the disk it
complains about unhandled MMU.
On Sun, Mar 22, 2009 at 7:21 PM, Ali
.
Ali
On Mar 20, 2009, at 12:52 PM, Polina Dudnik wrote:
Right, I wasn't going to modify the hypervisor. But swizzling the
numbers clearly affects the hypervisor because when hypervisor sends
messages, the processor number is swizzled from 4 to 1. So,
initially the hypervisor thinks
documentation but can't find it.
Thanks.
Polina
On Fri, Mar 20, 2009 at 1:26 PM, Polina Dudnik pdud...@gmail.com wrote:
On Fri, Mar 20, 2009 at 1:11 PM, Ali Saidi sa...@umich.edu wrote:
Yea, that makes sense. You should probably look at the TLBs (that is
where a lot of the miscellaneous system
is it?
Thanks,
Polina
On Fri, Mar 20, 2009 at 2:54 PM, Polina Dudnik pdud...@gmail.com wrote:
Regarding running one processor with two threads, now that I think about
it, OpenSparc definitely assigns thread numbers and not processor numbers in
hardware description file. Niagara does not have
Hi,
So, to make sparc_fs work Ali and later I swizzled the processor numbers
from 4 to 1 because m5 expects 1 and gets 4. In order to make this hack
work, we also need to swizzle the numbers back before calling the
hypervisor. So, the processor numbers going into the hypervisor should be
swizzled
the numthreads to 2 and keep numcores
at 1.
Ali
On Mar 10, 2009, at 2:44 PM, Polina Dudnik wrote:
Yeah, I kinda though that too, more along the lines that other
OpenSparc binaries are dependent somehow on the hypervisor binary
and should also be recompiled. So, I did post to their forum
the cpu number
confuses the hypervisor because now there are two different numbers for the
second cpu. So, I will be looking into hypervisor.
Polina
On Thu, Mar 12, 2009 at 11:29 AM, Polina Dudnik pdud...@gmail.com wrote:
Ali,
I am a little worried that NumInterruptTypes is set to seven. I ran
numbers in the
hypervisor doesn't fix the problem.
Polina
On Fri, Mar 6, 2009 at 11:24 AM, Polina Dudnik pdud...@gmail.com wrote:
On Thu, Mar 5, 2009 at 5:10 PM, Gabriel Michael Black
gbl...@eecs.umich.edu wrote:
The change is simple enough that I'll just describe it. This deals
solely
at l307 and I don't think it should return if the thread is
suspended. It should get activated if the thread is suspended, isn't that
right or am I missing something?
Polina
Quoting Polina Dudnik pdud...@gmail.com:
Oh, I see. Do you think you can distribute the partial patch you have
after the cpuX: ... lines are printed and look at an
exec trace and try to debug the problem.
Ali
On Mar 5, 2009, at 2:30 PM, Polina Dudnik wrote:
It is m5-stable. Maybe I should change to m5. I can do that.
Also, are any of the binaries dependent on 1g2p-md.bin or 1g2p-
hv.bin
Can you tell me where you see id 3?
Polina
On Fri, Mar 6, 2009 at 3:49 PM, Ali Saidi sa...@umich.edu wrote:
You probably need to swizzle those bits as well.. turn id 3 into id 1.
Perhaps then it will work.
Ali
On Mar 6, 2009, at 4:44 PM, Polina Dudnik wrote:
Hi Ali!
So, I did run
Oh, never mind, I understand what you are saying. I will do that.
On Fri, Mar 6, 2009 at 3:49 PM, Ali Saidi sa...@umich.edu wrote:
You probably need to swizzle those bits as well.. turn id 3 into id 1.
Perhaps then it will work.
Ali
On Mar 6, 2009, at 4:44 PM, Polina Dudnik wrote:
Hi
at 12:52 PM, Ali Saidi sa...@umich.edu wrote:
Could you run m5 in gdb and give us a backtrace? That would probably
identify the problem. What additional changes did you make?
Ali
On Mar 5, 2009, at 11:57 AM, Polina Dudnik wrote:
Hi Ali,
Would you mind sending me the console output
I am doing it in m5.
Polina
On Thu, Mar 5, 2009 at 1:04 PM, Steve Reinhardt ste...@gmail.com wrote:
2009/3/5 Polina Dudnik pdud...@gmail.com:
I am not sure why our code base would be different and by how much, but
that
could be why yours is running fine and mine segfaults.
Hi Polina
, since it might shed some light on the reason.
The thing to do now is look through the solaris source to see what is
going on right after the cpuX: ... lines are printed and look at an
exec trace and try to debug the problem.
Ali
On Mar 5, 2009, at 2:30 PM, Polina Dudnik wrote:
It is m5
some light on the reason.
The thing to do now is look through the solaris source to see what is
going on right after the cpuX: ... lines are printed and look at an
exec trace and try to debug the problem.
Ali
On Mar 5, 2009, at 2:30 PM, Polina Dudnik wrote:
It is m5-stable
On Thu, Mar 5, 2009 at 4:50 PM, nathan binkert n...@binkert.org wrote:
There are multiple benchmarks that can be run in FS mode (like
ValStream). Where can I find a precise description of what those
benchmarks do exactly? The reason I ask is because I would like to
verify their behavior
Oh, I see. Do you think you can distribute the partial patch you have?
Thank you.
Polina
On Thu, Mar 5, 2009 at 4:48 PM, Gabriel Michael Black gbl...@eecs.umich.edu
wrote:
Quoting Polina Dudnik pdud...@gmail.com:
On Thu, Mar 5, 2009 at 3:38 PM, Gabriel Michael Black
gbl
thing to do.
Gabe
Quoting Polina Dudnik pdud...@gmail.com:
Oh, I see. Do you think you can distribute the partial patch you have?
Thank you.
Polina
On Thu, Mar 5, 2009 at 4:48 PM, Gabriel Michael Black
gbl...@eecs.umich.edu
wrote:
Quoting Polina Dudnik pdud...@gmail.com
writes to the IOB device registers that the hypervisor code does to
get things going.
Ali
On Mar 2, 2009, at 5:29 PM, Polina Dudnik wrote:
Never mind, I started the console and got ERROR: 1 CPUs in PD did
not start without the hack. So, you are right, there is something
wrong
PM, Polina Dudnik wrote:
Never mind, I started the console and got ERROR: 1 CPUs in PD did not
start without the hack. So, you are right, there is something wrong with
the cpu numbers. But I want to fix it for arbitrary numCpus. SO, to do that
I want to find a place where the requests
Hi Ali,
Why do you say:
Additionally, I had to put two hacks in to swizzle the CPU id numbers. For
whatever reason the hypervisor insists that the second CPU should be id 4
while m5 would like it to be id 1. I tried changing the hypervisor
description file and changing cpu4 to cpu1, however
where
bits(12, 8) get generated. So, I guess my question is: where are the packets
generated?
Polina
On Mon, Mar 2, 2009 at 3:26 PM, Polina Dudnik pdud...@gmail.com wrote:
Hi Ali,
Why do you say:
Additionally, I had to put two hacks in to swizzle the CPU id numbers. For
whatever reason
Hi,
I am trying to run SPARC_FS and it's not clear what the kernel should be set
to. It is set to vmlinux for Alpha, so I do the same thing for SPARC_FS but
I doubt that is the right thing to do. Regardless of what the kernel is set
to I get the following error:
REAL SIMULATION
warn:
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