[gem5-users] Re: Difference between using the Configuration Script vs Standard Library?

Hi Kaze, Thank you for reaching out and expressing your interest in gem5 simulations. I understand that you’re curious about the difference between the configuration script and the standard library when executing the SE binary with the same parameters. gem5’s interface is primarily based on

[gem5-users] Re: catching the traces of communication between the processors

Note: this is the output from the gem5 GPT ( https://chat.openai.com/g/g-o3y1y4t8J-gem5-gpt/) Certainly, Ojas! To capture traces of communication between processors in your gem5 simulation, a more specialized approach involves using the Communication Monitor component. This feature is designed

[gem5-users] Re: Limit debug output to certain instruction address range

he file in the event > handler in the config script (using the open and truncate python > functions), but that did nothing (my guess is because the file is already > open elsewhere). > > Thanks again! > > Best, > Hossam > -- > *From:* Jaso

[gem5-users] Re: Can I use RiscvO3CPU with TSO?

Hello, That *should* work, but my confidence isn't very high. I suggest running tests to see if you can produce TSO and non-TSO executions with and without the option. Cheers, Jason On Thu, Feb 15, 2024 at 12:32 PM Z HW via gem5-users wrote: > > I know that RISC-V assumes RVWMO. But if I want

[gem5-users] Re: Executing Binary Code in FS without a Kernel

Hi Alain, I'm the gem5-GPT bot, here to assist with your queries about the gem5 simulator. Please note that while I aim to provide accurate information, my responses could be wrong or may have been slightly edited for clarity. You can access the gem5-GPT on chat.openai.com/g/g-o3y1y4t8J-gem5-gpt

[gem5-users] Re: Limit debug output to certain instruction address range

Hi Hossam, > Yet another option is a way to enable/disable debugging in the config script mid-simulation. This would allow me to exit the simulation using an m5op before the instructions, enable debugging in the config script, continue, exit using an m5op after the instructions, disable

[gem5-users] Re: How to suspend FS simulation after certain number of ticks

Hello, Unfortunately, we don't have enough time to answer all questions in depth. You may be able to find more help on either the gem5 slack or the gem5 youtube channel . If you have access to ChatGPT Plus, you can also use the gem5

[gem5-users] Re: Can CloudSuite Run on FullSystem Simulation

Hello, Note: the output below is from the gem5-GPT. If you have chatGPT Plus you can access this GPT/bot at https://chat.openai.com/g/g-o3y1y4t8J-gem5-gpt. I've made some inline comments as well. Hello! Regarding your queries about running CloudSuite on gem5 in Full System (FS) mode with x86

[gem5-users] Re: Adding 9p support to the riscv-fs platform not working

Hi Thilo, My guess is that you need to add a node to the device tree. I would look at the device tree generated for Arm and see if you can pattern match what you need to add for RISC-V. Cheers, Jason On Mon, Oct 2, 2023 at 1:12 AM Thilo Voertler via gem5-users < gem5-users@gem5.org> wrote: >

[gem5-users] Re: Sharing cache lines at memory level

Hi Arteen, This is dependent on the Ruby coherence protocol you are using. It sounds like you're using MESI_Three_Level or MESI_Two_Level in which the LLC is a single logical cache that is banked between different instances. If you want something more like "cluster-private" LLC slices, then

[gem5-users] Re: Libthreads for Gem5

Hi George, You can use pthreads. There's no need for m5threads anymore. The only wrinkle is that you have to make sure the cross-compiled dynamic libraries are in the right place. You can use the "redirect paths" option to map a path on the host to a different location in the guest (like volumes

[gem5-users] Re: Generate Multiple Trace Files for Multi-Threaded Workloads on FS

Hi Abdelrahman, Thank you for your questions on the mailing list. I will try to answer them as best as I can. - The trace CPU model was not designed to support multithreaded applications or multiple cores. It was only tested with single-threaded benchmarks in both SE and FS mode. Therefore,

[gem5-users] Re: can't run riscv simulation with any CPU model except Atomic

Hello, These scripts are tested nightly, so they should be working. How long did you wait for the terminal output? It can take 15-30 minutes before you see any output. Cheers, Jason On Wed, Aug 23, 2023 at 5:00 AM oe-fans via gem5-users wrote: > hi, all > > I built gem5 v23.0.1.0, I can run

[gem5-users] Re: Memory allocation when using heterogeneous memory controllers

Hi Jaeyong, No, there's no way to distinguish the memory types in SE mode. You will have to modify the memory allocator or use `Process.map` ( https://github.com/gem5/gem5/blob/develop/src/sim/Process.py#L39) to map specific virtual addresses to physical addresses. If you use `map` you can then

[gem5-users] Re: How to solve "AttributeError: Can't resolve proxy" error when l1icache is replaced with new module

Hi Shaikhul, I think that you have somehow unset the `assoc` parameter (or set it to None) in the cache. Can you provide us the exact script you're running, the command line that you use to run, the information about the gem5 build (variant used), the version of gem5 you're using, and any

[gem5-users] Re: Prefetching during instruction decode

Hi Pedro, On quick suggestion: It may make sense to put the prefetcher in the CPU model code (e.g., during the decode stage in the O3CPU) instead of in the decode logic of the ISA. After you get the `StaticInst` from the decoder, you should be able to push prefetch requests into the instruction

[gem5-users] Re: RISCV Vector Extension in gem5

! > > BTW, is there a instruction list that supported ? Because I notice that > vector load unit-stride fault-only-first is not supported, I'm wondering if > there is a list/site/doc about instructions and other stuff in RVV 1.0. > Thanks again ! > > Best regards > xbj > > ---

[gem5-users] Re: RISCV Vector Extension in gem5

Hello, Initial RVV support was just merged today! See https://github.com/gem5/gem5/pull/83 On Thu, Aug 3, 2023 at 12:29 AM 谢 佰杰 via gem5-users wrote: > Hi all, > I found that both rivosInc and RALC888 used to work on RISC-V Vector > Extension in gem5, but both of them seem to be busy with

[gem5-users] Re: ARM KVM Switch + Restoration

This should work... can you provide an example script and specific commands to reproduce the error? Thanks, Jason On Tue, Aug 1, 2023 at 11:24 AM AbdelQader AlKilany via gem5-users < gem5-users@gem5.org> wrote: > Hello gem5 users, > > > > I was wondering if it is possible to start a FS ARM

[gem5-users] Re: Unable to boot Linux in FS mode

Hi Zhenwen, The actual error is one line higher in the kernel output: `/lib/x86_64-linux-gnu/libc.so.6: CPU ISA level is lower than required` I believe we fixed the incompatibility of gem5-x86 with newer kernels in gem5-v22.1, but it is definitely fixed in gem5-v23.0. I suggest either updating

[gem5-users] Re: Using Traffic Generators with Ruby

Hi Vishnu, I do not believe there is any way to direct traffic to a particular message buffer (e.g, `requestToDir`). Ruby is in some sense a "black box" that only has port inputs (which are directed to a sequencer) and port output (via `requestToMemory`). That said, this is a cool idea! I would

[gem5-users] Re: stopping simulation via ThreadContext::halt()

Hi David, I think you want to call the function `exitSimLoopNow` or `exitSimLoop`. You can call this function from an instruction implementation, (e.g., halt), I believe. See https://github.com/search?q=repo%3Agem5%2Fgem5+exitSimLoop+=code Cheers, Jason On Wed, Jul 26, 2023 at 9:39 AM David

[gem5-users] Re: Facing issue while trying to use PARSEC benchmark using Gem5

Hi Abhinav, I would suggest using the most recent version of gem5 (v23.0) and use the gem5-resources version of parsec. See https://resources.gem5.org/resources/x86-parsec/example?database=gem5-resources=1.0.0 for an example using parsec. Cheers, Jason On Thu, Jul 27, 2023 at 2:14 AM Abhinav

[gem5-users] Re: Inquiry about using RiscvTimingSimpleCPU to connect with TLM memory in Gem5

Hi Zitai, You should be able to use any CPU model with the TLM interface. You can write your own configuration file / run script that creates a TimingSimpleCPU and connects the I/D ports to the TLM interface. Cheers, Jason On Thu, Jul 27, 2023 at 2:44 AM 泰。 via gem5-users wrote: > Hi： > > I

[gem5-users] Re: potential error in gem5 simulation?

There's a lot of information missing in your email, but I'll make some guesses and try to help. If you're using x86 and you compiled lbm on your host, then most likely it is using SSE/AVX/vector instructions that may not be implemented or implemented incorrectly in gem5. I would expect to see

[gem5-users] Re: Question about pulling in the latest version of gem5 with the bootcamp 2022 files.

Hi Nick, You should be able to `cd` to the gem5 directory, set up a remote to the new github location (`git remote add upstream https://github.com/gem5/gem5`) then checkout stable (`git checkout upstream/stable`). (Note: commands off the top of my head and may have mistakes.) That said, be

[gem5-users] Re: Meltdown simulation & analysis in FS mode using fs.py

Hi Robin, This may be helpful: http://www.lowepower.com/jason/visualizing-spectre-with-gem5.html For `warn: instruction 'palignr_Vdq_Wdq_Ib' unimplemented`, this is an AVX (or SSE) instruction that gem5 doesn't implement. Overall, I'm not sure if gem5 is vulnerable to meltdown. I think that the

[gem5-users] Re: Adding a delay of certain ticks in gem5

Hi John, The following may be helpful: https://gem5bootcamp.github.io/gem5-bootcamp-env/modules/developing%20gem5%20models/events/ https://www.youtube.com/watch?v=OcXA1D4b1RA=3868s Cheers, Jason On Thu, Jul 6, 2023 at 9:53 AM Eliot Moss via gem5-users < gem5-users@gem5.org> wrote: > On

[gem5-users] Re: Hi does gem5 Ruby support pthreads lock and unlock

Full system mode is fully supported for RISC-V. There should not be any problems with running pthreads on RISC-V. (Side note: There could be a small bug in the RISC-V atomic instructions... we're looking into it, but haven't been able to track it down.) Cheers, Jason On Thu, Jun 29, 2023 at

[gem5-users] Re: simulate a multi-core processor with Gem5

Hello, You may also find the "Learning gem5" documentation https://www.gem5.org/documentation/learning_gem5/introduction/ and the bootcamp videos https://www.youtube.com/playlist?list=PL_hVbFs_loVSaSDPr1RJXP5RRFWjBMqq3 useful. Cheers, Jason On Tue, Jun 20, 2023 at 10:49 AM Eliot Moss via

[gem5-users] Re: About Risc-V custom ISA

Hello, I believe you would have to modify your compiler to emit the instruction to avoid using embedded assembly. Cheers, Jason On Tue, Jun 20, 2023 at 10:36 AM 中国石油大学张天 via gem5-users < gem5-users@gem5.org> wrote: > When I have customized a RISC-V instruction, I want to know how to make > the

[gem5-users] Re: Writing a script to run multiple simulations at once

Hi all, You can use python multiprocessing with gem5. See https://github.com/gem5/gem5/tree/develop/src/python/gem5/utils/multiprocessing for details. So, in theory, you can create scripts such that you can run `./gem5 run.py` which will run a set of different experiments. You could potentially

[gem5-users] Re: [EXT] Re: Question about running the hpca-2023 tutorial

Hi Nick, I think you have a typo. It's `gcr.io` as in "google *c*ontainer registry." I believe you have an "e" instead of a "c" in your URL. Cheers, Jason On Sat, Jun 10, 2023 at 7:52 AM Beser, Nicholas D. via gem5-users < gem5-users@gem5.org> wrote: > Bobby, > > > > I tried your

[gem5-users] Re: [EXT] Re: Question about running the hpca-2023 tutorial

Hi Nick, For teaching you may be able to get some inspiration from my class assignments. Specifically, assignment 5 is about coherence: https://jlpteaching.github.io/comparch/modules/gem5/assignment5/ All of the code for my assignments can be found here under different branches for each

[gem5-users] Re: Multi-level TLB is implemented in performance

t; > Thanks > Arun > > On Wed, Oct 28, 2020 at 9:01 PM Jason Lowe-Power via gem5-users < > gem5-users@gem5.org> wrote: > >> Yes, this is possible, and I believe it's already implemented for Arm. >> >> The best place to start is src/arch//tlb.cc >> >> Che

[gem5-users] Re: Full System + external memory

at 4:30 PM Jonathan Kang wrote: > Thanks! > > > > Would you have an example of how to instantiate this bridge? Also, I > imagine this bridge is right after the CPU I and D side ports and before > any membus that Gem5 has internally right? > > > > *From: *Jason Lowe

[gem5-users] Re: Full System + external memory

Hi Jonathan, Absolutely! You can set up a "bridge" which will take a subset of addresses and route to a different gem5 port. If you can convert from the port interface to the AXI, then it should "just work". Note that there are also already bindings to SystemC/TLM in gem5 as well that could serve

[gem5-users] Re: I really want these files for old x86 gem5

Hi Xiang, I would advise against using such old resources for current research. Using an OS from a decade ago may not give you results that are accurate for today's systems. For "linux-bigswap2.img", this is just an empty disk image that was used as swap space. You can probably use an empty file

[gem5-users] Re: Question Regarding L1 Cache Transient States handling Load Hit in Ruby MOESI CMP Directory protocol

Hello, This is a great question! The short answer is I believe that the coherence protocol is correct. (Though, there could always be unexpected bugs.) The slightly longer answer: You are probably seeing that the store happens before the load in "real" time. However, in the processors' view

[gem5-users] Re: Capturing SimPoint and running on ARM CycleModel

e resulting ELFies are > x86 right? I’d want to do this for ARM. > > > > *From: *Jason Lowe-Power > *Date: *Thursday, March 9, 2023 at 8:15 AM > *To: *Giacomo Travaglini > *Cc: *Jonathan Kang , The gem5 Users mailing list < > gem5-users@gem5.org> > *Subject: *

[gem5-users] Re: Capturing SimPoint and running on ARM CycleModel

com> wrote: > Hi Jonathan, > > > On 08/03/2023 17:47, Jonathan Kang wrote: > > Thanks Giacomo, > > > > A few questions: > > > >1. Who is Jason? So that I can contact him  > > > Jason Lowe-Power, here CCed > > > > >1. Reg

[gem5-users] Re: Location of gem5 dist

Hi Rajesh, You can find all of the links in this json file: https://gem5.googlesource.com/public/gem5-resources/+/refs/heads/stable/resources.json It's not very user-friendly, but we're working on it :) Cheers, Jason On Fri, Feb 17, 2023 at 10:15 AM Rajesh Shashi Kumar via gem5-users <

[gem5-users] Re: Query about Support for Chiplet Architecture

Hi Zhengrong, On Thu, Jan 12, 2023 at 2:40 PM Zhengrong Wang via gem5-users < gem5-users@gem5.org> wrote: > Hi All, > > Our group has been using gem5 for architecture research for a long time, > and we currently want to explore some ideas on modern multi-chiplet > architectures, e.g. AMD's EPYC.

[gem5-users] Re: DerivO3CPU panic: initiateAcc not defined: ROB fills and locks up

Hi Eliot, Unfortunately, I don't have a direct answer for you. However, I want to say that I appreciate you keeping the mailing list updated with your progress! Cheers, Jason On Fri, Jan 6, 2023 at 10:07 AM Eliot Moss via gem5-users < gem5-users@gem5.org> wrote: > On 1/4/2023 11:51 PM, Eliot

[gem5-users] Re: Command line options to modify the replacement policy in gem5

Hi Vipin, The interface to gem5 isn't the command line, it's a python runscript. In your python script, you can add parameters (e.g., with optparse) which are accessible from the command line, but this shouldn't be considered the main interface to modifying the parameters of gem5 objects. If you

[gem5-users] Re: Panic when running gem5 Full System mode

I believe the problem is with the kernel binary you are passing in. It needs to be the path to the binary (not a directory), and it must be the uncompressed kernel binary, not the compressed binary. Cheers, Jason On Tue, Nov 22, 2022 at 11:06 AM JASPINDER KAUR via gem5-users <

[gem5-users] Re: SPEC CPU 2017 taking days to simulate

mpoint with gem5 v22? Thanks a lot! > > > > BR, Markus > > > > On 08.11.2022, at 20:10, Jonathan Kang wrote: > > > > Something as big as Spec typically wouldn’t be simulated as a whole but > rather, using SimPoint on a cycle-accurate model. > > > >

[gem5-users] Re: SPEC CPU 2017 taking days to simulate

wrote: > Hi Jason, > > > >Is there any roadmap (near future not long term) to take gem5 to multi > thread accerleration? > > > > Regards > > Yao > > > > *发件人:* Jason Lowe-Power via gem5-users [mailto:gem5-users@gem5.org] > *发送时间:* 2022年11月

[gem5-users] Re: SPEC CPU 2017 taking days to simulate

Hi Markus, I would expect gem5 to be at least 10,000-100,000x slower than your host. So, if it takes 100 seconds on the host, then I would expect between 1,000,000 and 10,000,000 seconds or more! That's 277-2770 hours or 10-100 days!! BTW, I actually think a 10-100,000x slowdown is on the low

[gem5-users] Re: Top-down micro arch analysis

I don't think so, but it seems like a fabulous idea! Keep us posted if you work on it, please! Cheers, Jason On Fri, Oct 28, 2022 at 11:05 AM Majid Jalili wrote: > Hi, > Has anyone developed some script to do top down microarchitecture analysis > with gem5 stats? > > >

[gem5-users] Re: PyGILState_Check() failure

Can you describe what your python run script is doing? It looks like the error is happening when dumping stats. To do this, gem5 does python->C++->python, which may be causing the problem. Though, that's just a guess. Can you create a minimal example that causes the error so we can reproduce it?

[gem5-users] Re: HPCG on RISCV

0 | i*j: > >> > 5.291503): 225.380650 > >> > ITER: 1 | i: 7 | j: 5 Result(i: 2.645751 | j: 2.236068 | i*j: > >> > 5.916080): 231.296730 > >> > ITER: 1 | i: 7 | j: 6 Result(i: 2.645751 | j: 2.449490 | i*j: > >> > 6.480741): 237.777

[gem5-users] Re: HPCG on RISCV

see, something goes wrong with the accuracy of calculations in FS mode > (benchmark uses double precission). You can find the files here: > http://kition.mhl.tuc.gr:8000/d/68d82f3533/ > > Best regards, > Nikos > > Quoting Jason Lowe-Power : > > > That's quite odd that it works in SE

[gem5-users] Re: 3D NoC and Routerless NoC support in gem5

Hi Ali, For a 3D mesh, you'll have to create your own topology. This video should be helpful in explaining how to do that: https://youtu.be/rZ-AYaKBK4M For the most recent updates to the network models, you can see information on HeteroGarnet: https://www.gem5.org/2020/05/27/heterogarnet.html

[gem5-users] Re: HPCG on RISCV

://kition.mhl.tuc.gr:8000/f/4ca25fdd3c/) with the > following configuration: > > ./xhpcg --nx=16 --ny=16 --nz=16 --npx=1 --npy=1 --npz=1 --rt=0.1 > > Please let me know if you have any updates! > > Best regards, > Nikos > > > Quoting Jason Lowe-Power : > > &g

[gem5-users] Re: 回复：Re: 回复：Re: Different simulation results on different computers with the same configuration

Hello, The following two command produce very different gem5 binaries scons build/Garnet_standalone/gem5.opt The above command will use the Garnet_standalone "coherence" protocol. I use quotes around coherence because that protocol is essentially an empty protocol with no coherence. It's meant

[gem5-users] Re: HPCG on RISCV

Hi Nikos, I notice you said the following in your original email: In addition, I used the RISCV Ubuntu image > (https://github.com/gem5/gem5-resources/tree/stable/src/riscv-ubuntu), > I installed the gcc compiler, compile it (through qemu) and I get > wrong results too. Is this saying you get

[gem5-users] Re: Running Multithreaded Workload on O3CPU

confusing > me a bit, given the link I included above. > > I forgot to mention that I am using x86. > > Thanks. > > -- > > *Best,Abdelrahman Hussein* > MSc. Student -- Graduate RA/TA > School of Computing Sciences > Simon Fraser University, Canada > > &

[gem5-users] Re: Running Multithreaded Workload on O3CPU

Hello, In this case "Thread" means hardware context in the CPU (e.g., Intel hyperthreads), not *core*. Have you configured your O3CPU to have 8 hardware contexts? I'll give a few short pointers: 1. SPEC is single threaded (unless running SPEC rate), so there may not be other software threads

[gem5-users] Re: Trying to add barrier to threads example

> Thanks and Regards, > Gautam Pathak > ------ > *From:* Jason Lowe-Power > *Sent:* Friday, September 2, 2022 10:51 AM > *To:* The gem5 Users mailing list > *Subject:* [gem5-users] Re: Trying to add barrier to threads example > > Hi Gautam, > >

[gem5-users] Re: Trying to add barrier to threads example

Hi Gautam, Functional accesses (i.e., fake/debug accesses that bypass all timing) and Ruby do not play well together. Fundamentally, it is hard to know what is the most up to date value or which value(s) you have to update when a cache block is in an intermediate state. With MI_example and MESI,

[gem5-users] Re: Is there a dev branch with 2 level TLB in X86 Full System

Hi Arun, There's no mainline changes which implement a two level TLB in x86. This would be a welcome contribution, though! Cheers, Jason On Wed, Aug 31, 2022 at 12:14 AM Arun Kavumkal wrote: > Hi All, > I would like to know whether there is any ongoing work to implement 2 > level TLB in X86

[gem5-users] Re: Linux not booting on x86 (timing cpu, single core) after pulling latest stable branch

Hi Arun, Can you give us some details on the error that you're experiencing? Thanks, Jason On Sun, Aug 7, 2022 at 7:48 AM Arun Kavumkal wrote: > Dear All, > I was able to boot Linux v5.2.3 on x86 system (timing cpu, single core) > and execute benchmarks using gem5art

[gem5-users] Re: Support of SSE, MMX, X87, CMOV in gem5

call nx mmxext >> fxsr_opt rdtscp lm 3dnowext 3dnow nopl cpuid pni monitor ssse3 lahf_lm cpb >> proc_feedback pti clflushopt clwb overflow_recov > > > Thanks. > > -- > > *Best,Abdelrahman Hussein* > MSc. Student -- Graduate RA/TA > School of Computing S

[gem5-users] Re: Support of SSE, MMX, X87, CMOV in gem5

Hello, We support some of those instructions, but not all of them. I suggest running your workloads and watching out for unimplemented instruction warnings. Cheers, Jason On Mon, Jul 25, 2022 at 11:08 PM Abdelrahman S. Hussein < abdelrahman.sob...@gmail.com> wrote: > Hello, > > I am trying to

[gem5-users] Re: Running gem5 with DRAMsim3

Hello, We can only support the official gem5 repository found at https://gem5.googlesource.com/. You can find the information on how to use DRAMSim3 in the README https://gem5.googlesource.com/public/gem5/+/refs/heads/stable/ext/dramsim3/README Cheers, Jason On Sat, Jul 23, 2022 at 9:49 AM

[gem5-users] Re: turn off gem5 mailing list

Hello, At the end of all messages it says "To unsubscribe send an email to gem5-users-le...@gem5.org" You can also manage your subscription at https://harmonylists.io/list/gem5-users.gem5.org by creating an account and logging in. Cheers, Jason On Thu, Jul 7, 2022 at 7:14 AM Zhipeng Cao

[gem5-users] Re: What happens when a atomic only port is accessed in Timing simulation?

equest to atomic, and calls the > recvAtomic function. In this case it's the XBar. I will try to measure how > it's delayed. > > ------ > *From:* Jason Lowe-Power > *Sent:* Wednesday, July 6, 2022, 11:09 a.m. > *To:* The gem5 Users mailing list > *Subj

[gem5-users] Re: What happens when a atomic only port is accessed in Timing simulation?

Hi Zehan, Atomic memory accesses should not be used during the same simulation loop as timing accesses. I.e., you should not call "sendAtomic" on a port during the same simulation loop that you call "sendTiming". If there isn't a panic in that case, there probably should be. If you want to get a

[gem5-users] Re: _pid 100 is already used: Error gem5 - running benchmark

th the older version of gem5, right? > > Regards > Syam > > On Fri, 24 Jun 2022, 12:43 am Jason Lowe-Power, > wrote: > >> Hi Syam, >> >> The error is that in *SE mode* you have to manually specify the PID for >> each process when you are creating the pro

[gem5-users] Re: O3CPU "panic: Is stalled should have been cleared by stalling load!" when simulating for >5Billion insts, SE and FS, AARCH64

Hi Norbert, This is going to be a tough bug to track down! I would suggest enabling the Exec debug flag (and maybe some others for the O3CPU) and using --debug-start and starting the debug dumping a billion ticks or so before the error happens. Hopefully, you can then trace back what is causing

[gem5-users] Re: _pid 100 is already used: Error gem5 - running benchmark

Hi Syam, The error is that in *SE mode* you have to manually specify the PID for each process when you are creating the processes in Python. However, I think you're going to run into many problems trying to simulate such a large system/workload in SE mode. For instance, I seriously doubt 3GB is

[gem5-users] Re: Gem5 segfaults in build/X86/cpu/o3/fetch.cc

Hi Gagan, The problem is that the CPU doesn't have an ISA object as a child. Most likely, the function `createThreads()` wasn't called on the CPU instance. You need to set all of this up *in the python configuration*, not in the C++ models. Solving this problem is difficult if you're using the

[gem5-users] Re: "No alive nodes found in your cluster"

Hi Jason, To be honest, the mailman server isn't great at providing search/archiving. I would search on mail-archive (link in previous email below) and/or use google :). Cheers, Jason On Mon, Jun 6, 2022 at 4:48 PM wrote: > Hi Jason, > > > Thank you for your reply, I am using the “Search this

[gem5-users] Re: "No alive nodes found in your cluster"

Hi Jason, I'm not sure where you were trying to search. However, mail archive ( https://www.mail-archive.com/gem5-users@gem5.org/) is usually pretty reliable. If that's not working for you, you may be able to reach out to their support. Cheers, Jason On Mon, Jun 6, 2022 at 4:13 PM wrote: > Hi

[gem5-users] Re: mail sent to mailing list not visible in gem5-users Mail archive

Hi Javed, I received that message. No idea why it doesn't show up on mail archive.. Cheers, Jason On Tue, May 31, 2022 at 3:33 AM Javed Osmany wrote: > Hello > > > > I sent an email the gem5-users mailing list on the 27th May 2022, titled > “CHI compilation error when trying to add L3$

[gem5-users] Re: How to make _addr version of m5 ops work on x86+syscall emulation?

Hello, In the first case, since you're using SE mode, gem5 is trying to use /dev/mem *on your host*, not on the guest. The addr interface for the m5 ops is really meant for FS mode, not SE mode. In the second case, this is probably because KVM + SE mode is rarely, if ever, tested. I'm not

[gem5-users] Re: virtual address -> base + offset

of the > memory address through the request > > object like this. > > req->getPaddr(); > > req->getVaddr(); > > But I would like to extract the base and offset component of the virtual > address as separate entities. Is that also possible? > > > > Thank

[gem5-users] Re: virtual address -> base + offset

Hi Sindhuja, The WholeTranslationState object should have all of the virtual and physical address information. In fact, the Request object (a member of the Packet) should also have both virtual and physical addresses. Cheers, Jason On Mon, May 9, 2022 at 10:23 AM Sindhuja Gopalakrishnan Elango

[gem5-users] Re: fatal: Syscall 278 out of range (ARM) - can i skip/supress syscall unimplemeted errors

Hi Tom, My guess is that you're using a newer version of GLIBC which calles different syscalls than the versions of GLIBC that have been tested with gem5. I believe 278 is mq_notify. You can try to update the syscall implementation to ignore the syscall and see if the application still works. See

[gem5-users] Re: Adding DmaDevice leads to TypeError: No constructor defined

n/m5/SimObject.py", line 1720, in getCCParams > cc_params = cc_params_struct() > > TypeError: _m5.param_DmaDevice.DmaDeviceParams: No constructor defined! > > > > *Dma_device.cc* > > DmaDevice::DmaDevice(const Params ) > > : PioDevice(p), dmaPort(th

[gem5-users] Test email please ignore

Sorry for the spam. We're working to fix the issues that some people have been having with our mailing list. I hope this will be the last test email for a while! Cheers, Jason ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an

[gem5-users] Re: Low memory bandwidth achieved with STREAM benchmark

Majid, These are all great suggestions! Do you have a configuration file that you would be willing to share? It would be a huge benefit to the community if we had some better default configurations in the "examples" for gem5 configuration files. We're also trying to use the new standard library

[gem5-users] Re: Adding PioDevice leads to TypeError: No constructor defined

I just pushed a change that will make this error message better. "fatal: Cannot instantiate an abstract SimObject (system.dev)" is what the error now says :). See https://gem5-review.googlesource.com/c/public/gem5/+/59049 Cheers, Jason On Fri, Apr 22, 2022 at 8:57 AM Jason Lowe-Po

[gem5-users] Re: Adding PioDevice leads to TypeError: No constructor defined

Hello, I believe the problem is that gem5 tries to do too much automatically for you! gem5 automatically creates a lot of the constructor/destructor codes. Given all of this hidden/automatic code generation, it's difficult to know exactly what's going wrong (for both you and for us). That said,

[gem5-users] Re: Integrating MCPAT with gem5

Hi Vipin, McPAT is not the same kind of simulator as SST, DRAMSim, and SystemC, so it cannot be integrated in the same way. It's not really a timing simulator at all. You can use gem5's statistics output as the "activity rate" which is one of the inputs to McPAT. However, the other inputs (e.g.,

[gem5-users] Re: How to set the Cache replacement policy

Hi Ankit, I would suggest modifying your python runscript instead of using command line parameters. https://www.gem5.org/documentation/learning_gem5/introduction/ may help explain how to set parameters on SimObjects. Cheers, Jason On Wed, Apr 6, 2022 at 2:48 PM Ankit Berde wrote: > Hi Gem5

[gem5-users] Re: How does an out of order pipeline implementation handle instructions (cmp, adds,cmn etc.) which update N,Z,C,V?

Hi Tom, On Tue, Mar 29, 2022 at 9:39 AM tomjosekallooran--- via gem5-users < gem5-users@gem5.org> wrote: > Hi , > This may sound very generic, but i want to try some experiments with the > out of order implementation. I came across few scenarios, which are listed > below (any input would be

[gem5-users] Re: Problem with SimObject

Hi Artyom, You're absolutely right that the tutorial needs to be updated! The website is also open source and managed via a git repo: https://gem5.googlesource.com/public/gem5-website/. Updating this would be a good way to get started contributing to gem5 :). By the way, for the namespace, you

[gem5-users] Re: gem5 and non volatile memory

Hello Taiyu, I would suggest reaching out to the VANS authors. Since this project is not part of the gem5 repository, we have little control over the integration. Cheers, Jason On Thu, Mar 24, 2022 at 8:49 PM Taiyu Zhou via gem5-users < gem5-users@gem5.org> wrote: > Could you give me some

[gem5-users] Re: CXL protocol/model implementation

Hi Zicong, 1. I personally don't believe that CXL in SE mode would be very interesting. From my point of view, CXL would be interesting only to capture the OS and system-level effects. That said, you may be able to test CXL.cache in SE mode. 2. To implement the different protocols: CXL.io: This

[gem5-users] Re: Issue with strange virtual address access

Hi Tom, I'm not sure. Again, I'd add the Vma and the SyscallVerbose debug flags which may help figure it out. It's possible that's the address of a dynamically-loaded library as well. Also, this trace looks like it came from Arm instead of x86. I don't have as much experience looking at Arm

[gem5-users] Re: Building Old gem5 error

Hello Abdelrahman, Unfortunately, it's incredibly difficult to keep the development environment for older versions of gem5 working. You may be able to find an old dockerfile in those gem5 repositories that could help to recreate the build environment. (I'm not sure if we were using docker at the

[gem5-users] Re: Issue with strange virtual address access

Hi Liyan, This looks like a stack address to me, so it won't appear in the objdump. Since you're using SE mode, gem5 is controlling the physical address mappings (not the OS). You can use the "Vma" debug flag to see all of the virtual memory areas that gem5 creates/assigns. the "SyscallVerbose"

[gem5-users] Re: How do I disable most statistics in the stats.txt under Atomic CPU

Hello, I don't believe there's a way to do that right now. However, in atomic mode, many stats *are* skipped as they are only accessed in the "timing" functions. I doubt it would make much performance difference. However, that's just a guess, and I could be wrong. Cheers, Jason On Wed, Mar 16,

[gem5-users] Re: Is thread lock not working under both SE and FS mode?

Hi Meng, It depends on the ISA you're using and the configuration of the system. For instance, x86+classic caches is known to have some synchronization issues. The transactional memory support only works with Arm, and I'm not sure which memory system it requires. What system are you trying to

[gem5-users] Re: Running FS in example/gem5_library/x86-spec-cpu2017-benchmarks.py

gem5? >- My understanding is that the FS simulation is significantly slow. >Any guidelines on how to make it as fast as possible? > > Above all, thanks a lot for taking time helping us. Much appreciated! > > > > > On Thu, Mar 10, 2022 at 7:01 AM Jason Lowe-Power

[gem5-users] Re: Running FS in example/gem5_library/x86-spec-cpu2017-benchmarks.py

Hi Abdelrahman, >From the get error message, it says: "This error may be caused by a too restrictive setting in the file '/proc/sys/kernel/perf_event_paranoid' The default value was changed to 2 in kernel 4.6 A value greater than 1 prevents gem5 from making the syscall to perf_event_open"

[gem5-users] Re: M5 Fs utility workbegin

ning first in KVM mode on a x86 host hoping to switch CPUs > once the work start event happens. Are magic ops unsupported in KVM mode? > > Thanks! > > > On Wednesday, March 9, 2022, 09:14:24 AM PST, Jason Lowe-Power via > gem5-users wrote: > > > Hi George, > >

[gem5-users] Re: M5 Fs utility workbegin

Hi George, For workbegin/workend, they can be called from within applications if you link to the libm5 library. For instance, in the parsec resource here: https://resources.gem5.org/resources/parsec we use the m5_workbegin() function in the ROI hooks. See

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