[gem5-users] Re: gem5art, FS mode, panic: PerfKvmCounter (perf_event_paranoid is set to -1)

2021-09-23 Thread Jason Lowe-Power via gem5-users
es! Seems like quite a can of worms.It's almost > looking like it could be easier to partition a computer for Linux and start > over. Would you recommend that as an alternative? > > All th > > On Thu, Sep 23, 2021 at 1:36 PM Jason Lowe-Power via gem5-users < > gem5-use

[gem5-users] Re: gem5art, FS mode, panic: PerfKvmCounter (perf_event_paranoid is set to -1)

2021-09-23 Thread Jason Lowe-Power via gem5-users
Hi Reiko, The KVM CPU requires that the host platform supports KVM. Given that you're using WSL, this means that you need to have nested virtualization enabled and implemented on your WSL kernel.

[gem5-users] Re: Problems with Deprecated names are not supported by the compiler

2021-09-23 Thread Jason Lowe-Power via gem5-users
Hi Xihui, The error is "died with " I would guess you're out of memory or trying to compile too many files at once. But, it could be many different problems. If it's an issue with dependencies or your host, you can always use our docker images:

[gem5-users] Re: Problems with Deprecated names are not supported by the compiler

2021-09-20 Thread Jason Lowe-Power via gem5-users
Hi Xihui, That's just a warning and you can safely ignore it. The most recent hotfix release should remove this warning as well. Cheers, Jason On Sun, Sep 19, 2021 at 10:02 PM Xihui Yuan via gem5-users < gem5-users@gem5.org> wrote: > Hello everyone: > > I am a beginner with GEM5. >

[gem5-users] Re: --take-checkpoints flag

2021-09-08 Thread Jason Lowe-Power via gem5-users
k I've honed in on the source of the problem > -- namely, number of cpus. Is there a reason why having multiple CPUs in a > particular configuration would limit the simulator's ability to write a > checkpoint? > > Again, thank you for your help! > > Best, > Sam > > On Wed, Sep

[gem5-users] Re: Is it ok to remove `maxRoutingTableSizeCheck`?

2021-09-08 Thread Jason Lowe-Power via gem5-users
Hi Emil, You can remove that check. However, you should note that the classic caches aren't designed to support high-bandwidth operation. Also, this assert triggering could be a sign that there's infinite queuing somewhere (which is one reason why the classic caches aren't great for high

[gem5-users] Re: --take-checkpoints flag

2021-09-08 Thread Jason Lowe-Power via gem5-users
Hi Sam, Sorry for the frustration. Writing better documentation is always #2 on the priority list :(. I always tell people not to trust any of the "options" to fs.py and se.py. Those scripts have gotten so far beyond "out of hand" at this point that they are almost useless. They are trying to be

[gem5-users] Re: Query: Valgrind speed in FS

2021-09-07 Thread Jason Lowe-Power via gem5-users
Hi Sindhuja, Yes, there is an expectation that valgrind causes a slowdown. Let me give you a couple of suggestions. 1. Make sure you compile without tcmalloc (e.g., scons build//gem5.opt --without-tcmalloc). Using tcmalloc will make valgrind miss all allocations. 2. Use the suppressions file in

[gem5-users] Re: regarding building of dependencies

2021-09-02 Thread Jason Lowe-Power via gem5-users
Hello, It should be X86 (capitol X) instead of x86. You can see the files in gem5/build_opts for the different possibilities for default build variables. Cheers, Jason On Thu, Sep 2, 2021 at 3:58 AM Sravani Sravanam 20PHD7041 via gem5-users < gem5-users@gem5.org> wrote: > sir, > i am sravani

[gem5-users] Re: Collecting Two Sets of Data Within Same Simulation

2021-08-13 Thread Jason Lowe-Power via gem5-users
Hi Sam, This is a use case that I don't think we've thought about in the mainline gem5. I think the easiest solution would be to add some custom Statistics objects to track the info from the function you're interested in. Cheers, Jason On Wed, Aug 11, 2021 at 10:59 AM Thomas, Samuel via

[gem5-users] Re: 答复: gem5 v21.1 released!

2021-07-29 Thread Jason Lowe-Power via gem5-users
Hi Liyichao, We welcome contributions to the gem5 resources! Currently, we have full system resources available for x86 and one available for RISC-V. We don't have any Arm resources available right now, but that's only because we haven't had the time (or resources ;)) to get around to it. Again,

[gem5-users] Re: ARM KVM

2021-07-12 Thread Jason Lowe-Power via gem5-users
To use hardware-accelerated virtualization (i.e., KVM) your host and guest must have the same ISA (and the host must have virtualization extension). Cheers, Jason On Mon, Jul 12, 2021 at 12:17 PM Νικόλαος Ταμπουρατζής via gem5-users < gem5-users@gem5.org> wrote: > Dear gem5 community, > > I

[gem5-users] Re: Custom SimObject Causes Host Machine to Freeze

2021-07-06 Thread Jason Lowe-Power via gem5-users
Hi Sam, My suggestion would be to use gdb. You can run gem5 in gdb and then use ctrl-c to stop the execution and see where the program is getting stuck. Also, enabling debug flags (or just good ole printf debugging) can also be useful in these cases. Another option with gdb would be to put

[gem5-users] Re: question about RSCV-V implementation on Gem5

2021-07-05 Thread Jason Lowe-Power via gem5-users
See https://gem5.atlassian.net/browse/GEM5-618 On Sat, Jul 3, 2021 at 5:23 PM lovline via gem5-users wrote: > Hi, >We are working on an important project, and we want to use RSCV-V1.0 > vector instructions on Gem5. >But we cann't find any features or codes about RSCV-V on Gem5. >We

[gem5-users] Re: does gem5 have a C++ API?

2021-07-02 Thread Jason Lowe-Power via gem5-users
he > examples, > but hopefully at least 100x faster than this. > > What's the best supported mechanism for running many tiny simulations > w/o having to pay for the large python overhead? > Any examples? > > --kcc > > > > > > > On Thu, Jul 1, 202

[gem5-users] Re: does gem5 have a C++ API?

2021-07-01 Thread Jason Lowe-Power via gem5-users
Hello, It's somewhat possible. You can compile gem5 as a library (e.g., scons build//libgem5-opt.so). However, gem5 *is a python interpreter* and is configured via python scripts. Getting that to work with an external program is "exciting". It's possible to get python working, and there are other

[gem5-users] Re: gem5 + GPU support?

2021-06-30 Thread Jason Lowe-Power via gem5-users
Hi Adrian, The AMD GPU model has never been tested with Arm. I doubt the ROCm stack will compile/work with any ISA other than x86, unfortunately. For multi-GPU support see http://www.gem5.org/2020/05/30/enabling-multi-gpu.html Of course, multiple CPUs will work with no problem with or without

[gem5-users] Re: gem5 + GPU support?

2021-06-30 Thread Jason Lowe-Power via gem5-users
Hi Adrian, gem5 has support for AMD's GCN3 (compute) GPU in SE mode, and we're working on merging both Vega support (AMD's newer GPU ISA) and full system support. The status of these new features can be followed on Jira. Here's documentation on the current GPU support:

[gem5-users] Re: Fatal error while running multithreaded program in SE mode

2021-06-25 Thread Jason Lowe-Power via gem5-users
What version of gem5 are you using? I believe gem5-20.0+ has the getdents syscall implemented. I'm sure that 21.0 has the syscall implemented. Whether you're using Ruby or classic caches it shouldn't make any difference on whether the syscalls are implemented. Cheers, Jason On Fri, Jun 25, 2021

[gem5-users] Re: gem5 RISCV, issue on boot when mounting filesystem

2021-06-25 Thread Jason Lowe-Power via gem5-users
Hi everyone, These details on gem5-resources have also been tested multiple times. We have also gotten unmodified OpenSBI working with gem5 as well. Ayaz can provide more details if you need. https://gem5.googlesource.com/public/gem5-resources/+/refs/heads/stable/src/riscv-fs/ Cheers, Jason On

[gem5-users] Re: Understanding write timing in MemCtrl

2021-06-22 Thread Jason Lowe-Power via gem5-users
Hi Vincent, It depends on when/how you're ending the simulation. If you end the simulation at some particular tick, then you'll see writes left in the write queue. Just like a real machine, writes don't happen instantaneously, and at some point in time, there are writes sitting in the write

[gem5-users] Re: Memory-Intensive C Programs in SE Mode

2021-06-21 Thread Jason Lowe-Power via gem5-users
Hi Sam, Are the (virtual, physical?) addresses different when you use the larger arrays? I wonder if the underlying mmap or malloc calls are breaking in SE mode somehow. Maybe, after you allocate in your guest code you can print out the virtual address to make sure it looks reasonable. You can

[gem5-users] Re: Reserve a chuck of memory space in SE mode

2021-06-21 Thread Jason Lowe-Power via gem5-users
Hi Xijing, You can set specific mappings from virtual to physical addresses by calling the `map()` function on the Process object from your python configuration file. See https://gem5.googlesource.com/public/gem5/+/refs/heads/stable/src/sim/Process.py#37 Then, once you have a virtual->physical

[gem5-users] Re: Call m5ops writefile when simulation ends

2021-06-21 Thread Jason Lowe-Power via gem5-users
Hi Pedro, No, I don't think there's an easy way to run m5_write_file on the guest from the host. That is an instruction that is executed on the guest, and the host can't easily control what is executing on the guest (especially when you consider that it has to execute in the right context, etc.).

[gem5-users] Re: Making virtual address range of a PIO device uncacheable in x86 FS simulation.

2021-06-21 Thread Jason Lowe-Power via gem5-users
Hi Deepak, Yeah, the cache disable bit may not work correctly in the page table walker/TLB. You can check the code there to see if that's what's going wrong. You can also try adding an E820 entry to the workload object (e.g.,

[gem5-users] Re: [gem5 version 20.1.0.5] Writing to satp in RISCV FS mode causes error when L1 caches are added.

2021-06-21 Thread Jason Lowe-Power via gem5-users
Hi Deepak, Have you tried the latest gem5? There's been a lot of work in both gem5-21.0 and on gem5-develop to improve the RISC-V FS support. Another option would be to look at how the RISC-V code has changed to see if that helps diagnose this problem. Cheers, Jason On Fri, Jun 18, 2021 at

[gem5-users] Re: Queued Ports

2021-06-21 Thread Jason Lowe-Power via gem5-users
Hi Sam, No, there's not good documentation on this (yet ;)). It's relatively easy to set up, though. Instead of using a single packet ptr, you can have a queue (or whatever datastructure you would like), and you can set the blocked flag only when it is "full" (e.g., the number of items in the

[gem5-users] Re: Caches with different line sizes

2021-06-08 Thread Jason Lowe-Power via gem5-users
Hi Patrick, gem5 doesn't support multiple cache line sizes "out of the box", but there's no reason you couldn't add the support. Creating a memory-side cache with a larger cache line is certainly possible! You might need to make some modifications to the Cache SimObject or create your own object.

[gem5-users] Re: gem5.org seems to be down

2021-06-08 Thread Jason Lowe-Power via gem5-users
It seems to be back now, but please let us know if you can't access it! I think it was related to the Fastly outage. See the CNN article for more details :). https://www.cnn.com/2021/06/08/tech/internet-outage-fastly/index.html Cheers, Jason On Tue, Jun 8, 2021 at 3:21 AM Pedro Henrique

[gem5-users] Re: Topology errors

2021-05-28 Thread Jason Lowe-Power via gem5-users
Hi Travix, I believe Garnet (and/or Ruby) can only support 64 cores. They use a 64 bit number as a mask for the cores. To fix this, we'll need to dig in and replace all of those explicitly sized variables with vector. I don't think it's actually that many plance that need to change, but it's been

[gem5-users] Re: Fail to bootup with KVM in se.py on X86 arch

2021-05-12 Thread Jason Lowe-Power via gem5-users
son: > > > > I find that if I set –mem-size < 4GB, there is no error, but when > I set –mem-size=4GB or more than 4GB, the error occurred. > > > > > > > > *发件人:* Liyichao > *发送时间:* 2021年5月12日 0:26 > *收件人:* Jason Lowe-Power > *抄送:* gem5 users

[gem5-users] Re: Fail to bootup with KVM in se.py on X86 arch

2021-05-11 Thread Jason Lowe-Power via gem5-users
l stack, I find that the ioctl() > with KVM_CREATE_VCPU returned EEXIST errno, this means the vCPU exist. > > > >ioctl(5, KVM_CREATE_VCPU, 2)= -1 EEXIST (File > exists) > > > > > > *发件人:* Liyichao > *发送时间:* 2021年5月11日 12:54 > *收件人:* 'Jason

[gem5-users] Re: Fail to bootup with KVM in se.py on X86 arch

2021-05-10 Thread Jason Lowe-Power via gem5-users
Hmm, I don't immediately know what's going wrong. I would extend the panic on line 559 of vm.cc to also print the error code number so you can look it up. I believe you can use `errno` like normal after calling `ioctl`. For instance, you could add `strerror(errno)` to the panic. Cheers, Jason

[gem5-users] Re: When using clwb “panic: Tried to write unmapped address” in Gem5 X86

2021-05-07 Thread Jason Lowe-Power via gem5-users
Hi Arun, Two quick ideas... 1. The address 0x56318e53ed40 looks suspect. That's not on the stack, in the OS, on the heap... I think it's probably a bad address. Most likely some other instruction before this one is causing a bad address to be emitted. 2. CLWB/CLFLUSH/CLFLUSHOPT may or may not

[gem5-users] Re: 答复: TimingCPU's IPC

2021-04-27 Thread Jason Lowe-Power via gem5-users
Hello, Check out the config.ini file in m5out/ and see what your CPU clock is actually set to. I would guess that the options are not behaving the way you expect (well, the way anyone would expect). se.py (and the options in Options.py) is pretty fundamentally broken. There are tons of special

[gem5-users] Re: TBE Tables in Ruby and Garnet Network

2021-04-26 Thread Jason Lowe-Power via gem5-users
Hi Human, On Sun, Apr 25, 2021 at 2:43 AM MOHAMMAD HUMAM KHAN via gem5-users < gem5-users@gem5.org> wrote: > Hello all, > > I am studying MESI Two Level Protocol in gem5 using garnet2.0 network and > CPU2006 benchmarks. I want to know the L1 Cache MSHR entries that are > present at any point in

[gem5-users] Re: A puzzle about how TLB is emulated

2021-04-22 Thread Jason Lowe-Power via gem5-users
Hello, As far as I know, TLB misses are not modeled in SE mode at all. Cheers, Jason On Thu, Apr 22, 2021 at 12:50 PM Θοδωρής Τροχάτος via gem5-users < gem5-users@gem5.org> wrote: > Hi Jason! Thanks for the info! > > Do you know what is happening when there is a TLB miss in SE mode? > Is the

[gem5-users] Re: A puzzle about how TLB is emulated

2021-04-22 Thread Jason Lowe-Power via gem5-users
Hi Leon, I believe you're correct. When there is a TLB hit, it's up to the *CPU model* to model the latency of the TLB access. I think this implementation was designed this way to give flexibility to the CPU models. Since the TLB is deeply embedded in the pipeline, we wouldn't want to always have

[gem5-users] Re: How to measure how many ticks a particular part of process costs?

2021-04-22 Thread Jason Lowe-Power via gem5-users
Hi Leon, This is exactly what gem5's region of interest (ROI) markers are for. You can use these "special instructions" as either magic instructions (using unused opcodes in the ISA) or as memory-mapped IO (useful for KVM CPUs). You can embed these markers in your program by calling the m5ops

[gem5-users] Re: Running parallel version of a CPU benchmark on multiple cores

2021-04-16 Thread Jason Lowe-Power via gem5-users
On Fri, Apr 16, 2021 at 2:13 PM Jason Lowe-Power > wrote: > >> Hi John, >> >> Yeah, it's something like that. We usually suggest using N + 1 cores >> where N is the number of threads. You can always use more ;). >> >> As a side note, if you configure thin

[gem5-users] Re: Running parallel version of a CPU benchmark on multiple cores

2021-04-16 Thread Jason Lowe-Power via gem5-users
gt; John Smith > > On Fri, Apr 16, 2021 at 12:58 PM Jason Lowe-Power > wrote: > >> Soon! https://gem5.atlassian.net/browse/GEM5-195 >> >> We're hopeful that in the next month or so all of this code will be >> public. >> >> Cheers, >> Jason >

[gem5-users] Re: Running parallel version of a CPU benchmark on multiple cores

2021-04-16 Thread Jason Lowe-Power via gem5-users
AM Jason Lowe-Power > wrote: > >> Hi John, >> >> I suggest using full system mode instead of SE mode if you're running a >> multithreaded workload. In FS mode, there's a full OS so it can handle >> thread switching, etc. For Parsec on x86 we've created a se

[gem5-users] Re: Running parallel version of a CPU benchmark on multiple cores

2021-04-16 Thread Jason Lowe-Power via gem5-users
Hi John, I suggest using full system mode instead of SE mode if you're running a multithreaded workload. In FS mode, there's a full OS so it can handle thread switching, etc. For Parsec on x86 we've created a set of resources for you to get started. See

[gem5-users] Re: Referencing an upstream component in parameters

2021-04-14 Thread Jason Lowe-Power via gem5-users
Hi Gabriel, I agree it's not intuitive and it's a bit awkward. Is there a reason for adopting that design? My guess is that it allows to > build the system top to bottom in the python scripts. > Haha! No, there's not an underlying reason for this. In fact, I would guess that there is a much

[gem5-users] Re: Referencing an upstream component in parameters

2021-04-13 Thread Jason Lowe-Power via gem5-users
Hi Gabriel, First, Ruby is a bit of a mess as far as circular dependencies go. Some of this is historic, and some of it is inherent to the design. I'm not too surprised you're running into this issue. The SimObject initialization is documented here:

[gem5-users] Re: Question about multi-socket simulation for x86

2021-04-12 Thread Jason Lowe-Power via gem5-users
Hi Chris, Using Garnet or SimpleNetwork with Ruby will allow you to set the latency of each link to anything you'd like and create any topology you'd like. You should be able to configure this to model a multi-socket system. That said, it's unclear if any of the current protocols will model a

[gem5-users] Re: Out of order memory responses

2021-03-30 Thread Jason Lowe-Power via gem5-users
Yes! That's no problem at all. The default memory controller is FRFCFS and it snoops the write queue, so it is already out of order :). Cheers, Jason On Tue, Mar 30, 2021 at 12:32 PM lsteiner--- via gem5-users < gem5-users@gem5.org> wrote: > Hi Jason, > thank's for your help. So if I have

[gem5-users] Re: Out of order memory responses

2021-03-30 Thread Jason Lowe-Power via gem5-users
Hello, Generally, there are no requirements or restrictions on memory access order in gem5. In Ruby, you can create a protocol that requires the network to be in order, but most protocols assume networks that are not explicitly ordered. The classic caches have no ordering restrictions. Cheers,

[gem5-users] Re: Problem with SimpleCache provided by learning_gem5/part2 when the ISA is ARM

2021-03-29 Thread Jason Lowe-Power via gem5-users
Hi Fugelin, This is an interesting bug! I would guess that there's a packet being copied in the cache when it should be reused. The simple cache isn't tested with Arm, and it's really just an example and shouldn't be used for anything "real". If you do figure out the bug, we'd love to accept your

[gem5-users] Re: Error: Can't find a working Python installation

2021-03-27 Thread Jason Lowe-Power via gem5-users
What I can say confidently is that I've never been able to get a virtual environment to work with gem5. It will 100% definitely work with python3 and scons installed on the system. Jason On Fri, Mar 26, 2021 at 10:18 PM haurunis--- via gem5-users < gem5-users@gem5.org> wrote: > Hi Jason, > >

[gem5-users] Re: Error: Can't find a working Python installation

2021-03-26 Thread Jason Lowe-Power via gem5-users
Hello, > I wonder how do I make gem5 detect the python in my current anaconda env, while I can directly run by `python`? This is difficult, and I've really struggled to get this to work with gem5. You need to make sure that scons picks up the correct `python3-config` binary. It *might* work to

[gem5-users] Some gem5 infrastructure down

2021-03-17 Thread Jason Lowe-Power via gem5-users
Hi all, We're having an issue with the billing for our Google cloud infrastructure. There may be intermittent issues with gem5 infrastructure for a little while. We hope to get this resolved within a few hours. Cheers, Jason ___ gem5-users mailing list

[gem5-users] Re: Simobjects in gem5

2021-03-11 Thread Jason Lowe-Power via gem5-users
It's not terribly useful, but you can list all SimObjects with `gem5.opt --list-simobjects` (or something like that, use `gem5.opt --help` to find the exact argument). You can also check in the src/mem/ directory for files that end in .py. These files are the SimObject description files and all

[gem5-users] Re: gem5 and non volatile memory

2021-02-16 Thread Jason Lowe-Power via gem5-users
Hi Krishnan, There is also a native NVM model in gem5 now. See http://www.gem5.org/2020/05/27/memory-controller.html for details. Also, though not as well integrated with gem5, there is VANS from UCSD: https://github.com/TheNetAdmin/VANS Cheers, Jason On Tue, Feb 16, 2021 at 2:51 PM Samuel

[gem5-users] Re: run a binary file for 3 times on gem5

2021-02-01 Thread Jason Lowe-Power via gem5-users
Hello, I don't think there's a simple way to do this in SE mode. In FS mode, you could write a simple shell script to execute the program in a loop. One thing you can do is to modify the program to execute the ROI multiple times. Cheers, Jason On Sun, Jan 31, 2021 at 5:20 PM ABD ALRHMAN ABO

[gem5-users] Re: write if-else statement in slicc transition code blocks.

2021-02-01 Thread Jason Lowe-Power via gem5-users
Hello, If you want to trigger two different transitions based on different inputs, this should always go in the in_port definition. For instance, see http://www.gem5.org/documentation/learning_gem5/part3/cache-in-ports/. You can base this on the message information by using peek() on the buffer.

[gem5-users] Re: Gem5 hardware arrays

2021-01-25 Thread Jason Lowe-Power via gem5-users
I believe that's referring to RAM generally (e.g., registers, caches, DRAM, etc.) Cheers, Jason On Mon, Jan 11, 2021 at 10:23 PM husin alhaj ahmade via gem5-users < gem5-users@gem5.org> wrote: > "Gem5 already includes all key microarchitecture components which model > hardware arrays on which

[gem5-users] Re: Configure multi-bank cache in ruby ​mode with MESI coherence protocol

2021-01-25 Thread Jason Lowe-Power via gem5-users
Hi Zhen, Sorry for missing your previous message. (1) I think the biggest difference is that the former does not implement a port for each bank, is it right? - I guess it assumes that the banks are the bottlenecks not the ports. It assumes that the banks are distributed and have separate ports,

[gem5-users] Re: Adjusting gem5 CPU simulation granularity in heterogeneous memory environments?

2021-01-06 Thread Jason Lowe-Power via gem5-users
Hi Balazs, That sounds a lot like elastic traces. See the documentation: https://www.gem5.org/documentation/general_docs/cpu_models/TraceCPU and the paper: https://ieeexplore.ieee.org/document/7482084. Even if elastic traces don't work for your purpose, the code for them should give you hints on

[gem5-users] Re: Reset Stats from Software

2020-12-29 Thread Jason Lowe-Power via gem5-users
Hi Sam, There's the "m5 utility" and the "m5 magic operations" for exactly what you're describing! See util/m5 for details. There's some documentation here http://www.gem5.org/documentation/general_docs/m5ops/ and in the code https://gem5.googlesource.com/public/gem5/+/refs/heads/develop/util/m5/

[gem5-users] Re: CXL protocol model simulation support schedual in GEM5

2020-12-29 Thread Jason Lowe-Power via gem5-users
Hello, The quick answer is "no," we don't have any CXL implementation. However, that seems like a great idea, and would be a great contribution to the community! I assume that you would be doing this Ruby. Feel free to let me know if you have any questions or run into any issues. Cheers, Jason

[gem5-users] Re: A question regarding to .sm file

2020-12-09 Thread Jason Lowe-Power via gem5-users
Hi Leon, SLICC really is its own language. It looks like C++ only to make it simpler to implement, not because you should be able to write C++ code. If you haven't read the Learning gem5 Ruby section, I would suggest starting there: http://www.gem5.org/documentation/learning_gem5/part3/MSIintro/.

[gem5-users] Re: How to invoke the schedule() function in .sm file

2020-12-09 Thread Jason Lowe-Power via gem5-users
Hi Leon, Scheduling arbitrary events is not allowed in SLICC. The SLICC language is meant only for defining state machines and their actions. Any scheduling, etc. should either be done within the restrictions of SLICC or outside of SLICC in some other way. For instance, you could add a new method

[gem5-users] Re: X86 Elastic Trace Replay

2020-11-18 Thread Jason Lowe-Power via gem5-users
Hey Patrick, This isn't exactly an answer to your question, but you can find a similarly "simple" x86 FS configuration in the gem5-resources repository. E.g., https://gem5.googlesource.com/public/gem5-resources/+/refs/heads/stable/src/boot-exit/configs/system/ . I'm sure that it's *possible* to

[gem5-users] Re: gem5 stats , LLC average miss latency

2020-11-18 Thread Jason Lowe-Power via gem5-users
Hi Arun, That time is in simulator *ticks*, not cycles. By default, the tick time is 1ps, so that would be an average latency of 3.8us, which is high, but seems possible for non-volatile memory. Cheers, Jason On Sun, Nov 15, 2020 at 11:43 PM Arun Kavumkal via gem5-users < gem5-users@gem5.org>

[gem5-users] Re: Multi-process shared memory in SE mode

2020-11-03 Thread Jason Lowe-Power via gem5-users
Hi Pedro, No, I don't have any specific pointers beyond the code in src/sim/. One quick note: on develop there is something in flux about how syscalls work. There's been some recent changes from Gabe to the "Workload" and the syscall dispatch. I have to admit I don't understand them, but it might

[gem5-users] Re: Configure multi-bank cache in ruby ​mode with MESI coherence protocol

2020-11-03 Thread Jason Lowe-Power via gem5-users
Hello, (1) Yes, I believe so. (2) I thought MOESI_hammer was annotated, but it doesn't look like (huh...). However, AMD MOESI Base is annotated. See all of the transition in the core-pair file, for instance:

[gem5-users] Re: What is the role of TimeBuffer in gem5?

2020-11-03 Thread Jason Lowe-Power via gem5-users
Hello, I've been using gem5 for ~10 years, and this is the first time I've ever seen this code :D. It was committed 14 years ago, and it hasn't been touched since. It looks to me like it's used for gathering statistics about the activity of different CPU pipeline stages. However, I *know* it's

[gem5-users] Re: Configure multi-bank cache in ruby ​mode with MESI coherence protocol

2020-10-28 Thread Jason Lowe-Power via gem5-users
Hello, For (1), yes. You can set this *in the python configuration file*. You should not modify the SimObject description file to change a default parameter. For (2), yes, that's exactly where you should modify. Cheers, Jason On Wed, Oct 28, 2020 at 9:47 AM zhen bang via gem5-users <

[gem5-users] Re: Multi-level TLB is implemented in performance

2020-10-28 Thread Jason Lowe-Power via gem5-users
Yes, this is possible, and I believe it's already implemented for Arm. The best place to start is src/arch//tlb.cc Cheers, Jason On Wed, Oct 28, 2020 at 1:27 AM Laney Laney via gem5-users < gem5-users@gem5.org> wrote: > Hi,all. I would like to know if it is possible to implement multi-level >

[gem5-users] Re: Multi-process shared memory in SE mode

2020-10-27 Thread Jason Lowe-Power via gem5-users
Hi Predro, It would certainly be easier in FS mode :D. Also, I would worry that the system call emulation layer might not model your application with high enough fidelity if you care about multithreaded apps (e.g., the futex system call will take 0 time in SE mode). If you dynamically link your

[gem5-users] Re: How to run Python code with TensorFlow in Gem5 syscall emulation mode?

2020-10-23 Thread Jason Lowe-Power via gem5-users
Hi Hasan, I agree with Abhishek. Something as complex as tensorflow is going to be very difficult to get working in syscall emulation mode. Using full system mode should work (though without things like GPU acceleration, of course). Cheers, Jason On Fri, Oct 23, 2020 at 1:55 PM Abhishek Singh

[gem5-users] Re: Configure multi-bank cache in ruby ​mode with MESI coherence protocol

2020-10-21 Thread Jason Lowe-Power via gem5-users
In this case, I would use the resource stalls to model banking. You can extend the BankedCache implementation to model arbitrary address interleaving, if that's important to your model. To do this, you'll have to add annotations to the transitions in the L0 and L1 cache, but this should be easier

[gem5-users] Re: Add FLUSH in MESI prtocol

2020-10-21 Thread Jason Lowe-Power via gem5-users
Honestly, I'm not sure. I would need to dig much deeper into the MESI_Three_Level protocol to be able to help. Jason On Tue, Oct 20, 2020 at 9:06 PM 1154063264--- via gem5-users < gem5-users@gem5.org> wrote: > In MOESI_hammer, the state transition in the I state is defined as follows, > >

[gem5-users] Re: Add FLUSH in MESI prtocol

2020-10-20 Thread Jason Lowe-Power via gem5-users
I would look to see how it's done in MOESI_hammer. https://gem5.googlesource.com/public/gem5/+/refs/heads/stable/src/mem/ruby/protocol/MOESI_hammer-cache.sm#902 Cheers, Jason On Tue, Oct 20, 2020 at 9:04 AM 1154063264--- via gem5-users < gem5-users@gem5.org> wrote: > Hello Jason: > It is

[gem5-users] Re: Add FLUSH in MESI prtocol

2020-10-20 Thread Jason Lowe-Power via gem5-users
Hello, The lack of error when writing a checkpoint doesn't mean it was successful. Likely, the data was not written back to memory correctly if the random test is failing. No, you cannot use `writeCallbackScFail`. This is to signal that a store conditional has failed. It might help to learn

[gem5-users] Re: Any one bootup with fs.py in gem5 version 20.1 with dramsim3 or nvmain succuessfully

2020-10-20 Thread Jason Lowe-Power via gem5-users
Hello, DRAMSim isn't a drop in replacement for the memory object anymore. Since the change in the memory interface ( http://www.gem5.org/project/2020/10/01/gem5-20-1.html#new-dram-interface-contributed-by-wendy-elsasser) you can't just drop in a different type of DRAM model. You'll probably have

[gem5-users] Re: Configure multi-bank cache in ruby ​mode with MESI coherence protocol

2020-10-19 Thread Jason Lowe-Power via gem5-users
Hello, It depends on how you want to model banking. If you just want to set and limit the bandwidth to a cache, you can use the "resourceStalls = true" option on the RubyCache object and set the tag and data array values. You will also have to tag every transition in the cache controller (i.e.,

[gem5-users] Re: Add FLUSH in MESI prtocol

2020-10-19 Thread Jason Lowe-Power via gem5-users
Hello, It's difficult for me to say for certain without digging much deeper. However, my gut says the latter is probably closer to correct. I doubt that you can drop the line without first receiving an ack (somehow). I'm not sure if this was said before, but you can use the Ruby random tester in

[gem5-users] Re: X86KvmCPU fails -- reason code 0x80000021

2020-10-16 Thread Jason Lowe-Power via gem5-users
ng error when I try to run a full-system >>>>> (configs/example/fs.py) with the X86KvmCPU: >>>>> >>>>> panic: KVM: Failed to enter virtualized mode (hw reason: 0x8021) >>>>> >>>>> I used to have kvm working with a pre-2018 versio

[gem5-users] Re: Add FLUSH in MESI prtocol

2020-10-14 Thread Jason Lowe-Power via gem5-users
Hello, If the block is already in I, then there shouldn't be anything to flush/write back. You should be able to simply do something like transition(I, Flush_line) { flushRespsonse; } action(flushResponse) { sequencer.flushResponse(); (or whatever this function is on the sequencer) } Cheers,

[gem5-users] Re: Invalid RubyRequestType

2020-10-12 Thread Jason Lowe-Power via gem5-users
Hi Teo, That error is because you're still using MESI_Two_Level. You need to recompile gem5 to use a different protocol. I.e., to use MESI_Two_Level you could do the following: > scons build/X86_MESI_Two_Level/gem5.opt > build/X86_MESI_Two_Level/gem5.opt To use MOESI_hammer you could do the

[gem5-users] Re: Add FLUSH in MESI prtocol

2020-10-09 Thread Jason Lowe-Power via gem5-users
Hello, It's hard for me to know what's wrong. Debugging protocols is hard! It looks like you're moving in the right direction, though. Other than giving you encouragement, I'm not sure I can help much. Cheers, Jason On Thu, Oct 8, 2020 at 7:58 PM 1154063264--- via gem5-users <

[gem5-users] Re: CPU configuration and default values

2020-10-08 Thread Jason Lowe-Power via gem5-users
Hi Davide, I echo 100% of what Giacomo said. Also, there's a proposal for updating the Python API here: https://gem5.atlassian.net/browse/GEM5-432. That proposal is a pretty extreme example, and we'll probably end up with something closer to the status quo. You can also check out Learning gem5

[gem5-users] Re: some questions while using kvm

2020-10-08 Thread Jason Lowe-Power via gem5-users
check out the latest release. BTW, > could you let me know how to use he MMIO/address version of the m5ops? > I make the m5term in util/term. > > -- > Best regards, > > Yifan Song > > -原始邮件- > *发件人:*"Jason Lowe-Power" > *发送时间:*2020-10-08 04:55:56 (星

[gem5-users] Re: some questions while using kvm

2020-10-07 Thread Jason Lowe-Power via gem5-users
Hi Yifan, First of all, the branch that you referred to is pretty old. I would use gem5-20.1. You can check out the gem5-resources for information on how to get KVM+x86 working with SPEC, Parsec, and other benchmarks. http://www.gem5.org/documentation/general_docs/gem5_resources/ Switching CPUs

[gem5-users] Re: FLUSH request from CPU sequencer to cache controller

2020-10-06 Thread Jason Lowe-Power via gem5-users
son, > > I just thought that FLUSH request can be handled with invalidate and > write-back. Could you let me know what other things should be considered > for FLUSH? Or is it fine modifying the CPU sequencer that it just ignore > the FLUSH request? > > 2020년 10월 6일 (화) 오전 8:15

[gem5-users] Re: Regarding ruby prefetcher requestIssued and requestCompleted bitset

2020-10-05 Thread Jason Lowe-Power via gem5-users
Hi Kavya, This looks like a bug! The RubyPrefetcher has never been regularly tested, as far as I know. I would guess the place where these were updated got deleted at some point and no one noticed. I'd try checking out a gem5 from 5 years ago and see if it's there. We would welcome a contribution

[gem5-users] Re: Adjusting gem5 CPU simulation granularity in heterogeneous memory environments?

2020-10-05 Thread Jason Lowe-Power via gem5-users
Hi Balazs, What you suggest sounds like a panacea! I'm not sure it's possible, though :(. There are multiple different levels of fidelity between the O3 CPU and the Timing Simple CPU. You could imagine other CPU models with more or less fidelity as well, but currently these are the two main

[gem5-users] Re: FLUSH request from CPU sequencer to cache controller

2020-10-05 Thread Jason Lowe-Power via gem5-users
Hi Daecheol, Unfortunately, the flush command is a bit more complicated to implement than just a simple replacement. I responded to another message about this on the mailing list a few minutes ago that you can see for more information. Cheers, Jason On Mon, Sep 28, 2020 at 8:59 PM Daecheol You

[gem5-users] Re: How to initialize the the Stats:Scalar value and convert it to unsigned value

2020-10-05 Thread Jason Lowe-Power via gem5-users
Hi Shougang, I think you can use .value() to get the actual value out of the stat. That should be easy to cast to an unsigned, if needed. However, I think there might be some confusion on how to register/use the stats. If you've registered it correctly and it is updated during simulation (e.g.,

[gem5-users] Re: Add FLUSH in MESI prtocol

2020-10-05 Thread Jason Lowe-Power via gem5-users
Hello, Yeah, adding flush to a protocol is a pretty large task, but it shouldn't be too difficult. The key difficulty will be testing it, but the Ruby tester does support testing flushes (probably not out of the box with ruby_random_test.py, though). There's no particular reason except that we

[gem5-users] A quick note for the gem5 community

2020-10-05 Thread Jason Lowe-Power via gem5-users
Hi everyone, We are sending this email to be as transparent as possible. The gem5 community is respectful and inclusive of all people, and we enforce these standards in all community spaces. We as members, contributors, and leaders pledge to make participation in our community a harassment-free

[gem5-users] Re: Segmentation fault in gem5,

2020-10-02 Thread Jason Lowe-Power via gem5-users
opinions. Let's work > together to keep it away from it. > > Hope you all have a good weekend. > > Thanks, > > [image: Screen Shot 2020-10-02 at 5.41.55 PM.png] > > > -Tao > > > On Fri, Oct 2, 2020 at 10:26 AM Jason Lowe-Power via gem5-users < > gem5-use

[gem5-users] Re: Segmentation fault in gem5,

2020-10-02 Thread Jason Lowe-Power via gem5-users
Hi everyone, A few things: 1. Being polite is important! We strive to make the gem5 community inclusive and welcoming. :) 2. Email can be very impersonal. Adding a greeting and a signature with your name helps create a more welcoming environment! 3. When asking questions on the mailing list, help

[gem5-users] Re: Question about MESI_Three_Level protocol

2020-09-28 Thread Jason Lowe-Power via gem5-users
Hi Daecheol, You're correct that MESI_Three_Level, like MESI_Two_Level has a shared (banked) LLC. The L2 cache is chosen based on the function "mapAddressToRange" (see https://gem5.googlesource.com/public/gem5/+/refs/heads/stable/src/mem/ruby/protocol/MESI_Three_Level-L1cache.sm#403 ). The

[gem5-users] Re: Tracking read()/write() system calls in gem5

2020-09-22 Thread Jason Lowe-Power via gem5-users
See the `readFunc` and `writeFunc` implementations in sycall_emul.hh: https://gem5.googlesource.com/public/gem5/+/refs/heads/stable/src/sim/syscall_emul.hh#2454 On Tue, Sep 22, 2020 at 12:25 PM ABD ALRHMAN ABO ALKHEEL via gem5-users < gem5-users@gem5.org> wrote: > Hi All, can I track the

[gem5-users] Re: Indirect target predictor

2020-09-21 Thread Jason Lowe-Power via gem5-users
Hi Shyam, I don't think so! However, we'd be happy to accept the contribution of new indirect predictors! Cheers, Jason On Fri, Sep 18, 2020 at 4:07 PM Shyam Murthy via gem5-users < gem5-users@gem5.org> wrote: > Hi All, > > Is there any other target predictor for indirect jumps on gem5 apart

[gem5-users] Re: trigger is not recongnized for MSI protocol withRuby in gem5

2020-09-21 Thread Jason Lowe-Power via gem5-users
Hi Shaikhul, "trigger" isn't really a function. It's a language statement (like, `if` in C/C++). SLICC doesn't always give the most helpful errors. However, I notice that the eros is actually showing line 124, not line 219. That seems suspicious to me, and I'd look more into that. Also, you can

[gem5-users] Re: Why using guest code with pseudo-instructions has less number of simulated ticks

2020-09-21 Thread Jason Lowe-Power via gem5-users
Hi Aamir, Slight changes (e.g., less that 1%) wouldn't be too surprising as SE mode isn't always deterministic. Additionally, you're changing the number of instructions and the layout of the binary when you add instructions. So, again, slight changes wouldn't be surprising. If the changes in

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