[gem5-users] Re: HPCG on RISCV

2022-09-21 Thread Jason Lowe-Power
see, something goes wrong with the accuracy of calculations in FS mode > (benchmark uses double precission). You can find the files here: > http://kition.mhl.tuc.gr:8000/d/68d82f3533/ > > Best regards, > Nikos > > Quoting Jason Lowe-Power : > > > That's quite odd that it works in SE

[gem5-users] Re: 3D NoC and Routerless NoC support in gem5

2022-09-21 Thread Jason Lowe-Power
Hi Ali, For a 3D mesh, you'll have to create your own topology. This video should be helpful in explaining how to do that: https://youtu.be/rZ-AYaKBK4M For the most recent updates to the network models, you can see information on HeteroGarnet: https://www.gem5.org/2020/05/27/heterogarnet.html

[gem5-users] Re: HPCG on RISCV

2022-09-20 Thread Jason Lowe-Power
://kition.mhl.tuc.gr:8000/f/4ca25fdd3c/) with the > following configuration: > > ./xhpcg --nx=16 --ny=16 --nz=16 --npx=1 --npy=1 --npz=1 --rt=0.1 > > Please let me know if you have any updates! > > Best regards, > Nikos > > > Quoting Jason Lowe-Power : > > &g

[gem5-users] Re: 回复:Re: 回复:Re: Different simulation results on different computers with the same configuration

2022-09-20 Thread Jason Lowe-Power
Hello, The following two command produce very different gem5 binaries scons build/Garnet_standalone/gem5.opt The above command will use the Garnet_standalone "coherence" protocol. I use quotes around coherence because that protocol is essentially an empty protocol with no coherence. It's meant

[gem5-users] Re: HPCG on RISCV

2022-09-20 Thread Jason Lowe-Power
Hi Nikos, I notice you said the following in your original email: In addition, I used the RISCV Ubuntu image > (https://github.com/gem5/gem5-resources/tree/stable/src/riscv-ubuntu), > I installed the gcc compiler, compile it (through qemu) and I get > wrong results too. Is this saying you get

[gem5-users] Re: Running Multithreaded Workload on O3CPU

2022-09-08 Thread Jason Lowe-Power
confusing > me a bit, given the link I included above. > > I forgot to mention that I am using x86. > > Thanks. > > -- > > *Best,Abdelrahman Hussein* > MSc. Student -- Graduate RA/TA > School of Computing Sciences > Simon Fraser University, Canada > > &

[gem5-users] Re: Running Multithreaded Workload on O3CPU

2022-09-08 Thread Jason Lowe-Power
Hello, In this case "Thread" means hardware context in the CPU (e.g., Intel hyperthreads), not *core*. Have you configured your O3CPU to have 8 hardware contexts? I'll give a few short pointers: 1. SPEC is single threaded (unless running SPEC rate), so there may not be other software threads

[gem5-users] Re: Trying to add barrier to threads example

2022-09-06 Thread Jason Lowe-Power
> Thanks and Regards, > Gautam Pathak > ------ > *From:* Jason Lowe-Power > *Sent:* Friday, September 2, 2022 10:51 AM > *To:* The gem5 Users mailing list > *Subject:* [gem5-users] Re: Trying to add barrier to threads example > > Hi Gautam, > >

[gem5-users] Re: Trying to add barrier to threads example

2022-09-02 Thread Jason Lowe-Power
Hi Gautam, Functional accesses (i.e., fake/debug accesses that bypass all timing) and Ruby do not play well together. Fundamentally, it is hard to know what is the most up to date value or which value(s) you have to update when a cache block is in an intermediate state. With MI_example and MESI,

[gem5-users] Re: Is there a dev branch with 2 level TLB in X86 Full System

2022-08-31 Thread Jason Lowe-Power
Hi Arun, There's no mainline changes which implement a two level TLB in x86. This would be a welcome contribution, though! Cheers, Jason On Wed, Aug 31, 2022 at 12:14 AM Arun Kavumkal wrote: > Hi All, > I would like to know whether there is any ongoing work to implement 2 > level TLB in X86

[gem5-users] Re: Linux not booting on x86 (timing cpu, single core) after pulling latest stable branch

2022-08-08 Thread Jason Lowe-Power
Hi Arun, Can you give us some details on the error that you're experiencing? Thanks, Jason On Sun, Aug 7, 2022 at 7:48 AM Arun Kavumkal wrote: > Dear All, > I was able to boot Linux v5.2.3 on x86 system (timing cpu, single core) > and execute benchmarks using gem5art

[gem5-users] Re: Support of SSE, MMX, X87, CMOV in gem5

2022-07-28 Thread Jason Lowe-Power
call nx mmxext >> fxsr_opt rdtscp lm 3dnowext 3dnow nopl cpuid pni monitor ssse3 lahf_lm cpb >> proc_feedback pti clflushopt clwb overflow_recov > > > Thanks. > > -- > > *Best,Abdelrahman Hussein* > MSc. Student -- Graduate RA/TA > School of Computing S

[gem5-users] Re: Support of SSE, MMX, X87, CMOV in gem5

2022-07-26 Thread Jason Lowe-Power
Hello, We support some of those instructions, but not all of them. I suggest running your workloads and watching out for unimplemented instruction warnings. Cheers, Jason On Mon, Jul 25, 2022 at 11:08 PM Abdelrahman S. Hussein < abdelrahman.sob...@gmail.com> wrote: > Hello, > > I am trying to

[gem5-users] Re: Running gem5 with DRAMsim3

2022-07-25 Thread Jason Lowe-Power
Hello, We can only support the official gem5 repository found at https://gem5.googlesource.com/. You can find the information on how to use DRAMSim3 in the README https://gem5.googlesource.com/public/gem5/+/refs/heads/stable/ext/dramsim3/README Cheers, Jason On Sat, Jul 23, 2022 at 9:49 AM

[gem5-users] Re: turn off gem5 mailing list

2022-07-07 Thread Jason Lowe-Power
Hello, At the end of all messages it says "To unsubscribe send an email to gem5-users-le...@gem5.org" You can also manage your subscription at https://harmonylists.io/list/gem5-users.gem5.org by creating an account and logging in. Cheers, Jason On Thu, Jul 7, 2022 at 7:14 AM Zhipeng Cao

[gem5-users] Re: What happens when a atomic only port is accessed in Timing simulation?

2022-07-06 Thread Jason Lowe-Power
equest to atomic, and calls the > recvAtomic function. In this case it's the XBar. I will try to measure how > it's delayed. > > ------ > *From:* Jason Lowe-Power > *Sent:* Wednesday, July 6, 2022, 11:09 a.m. > *To:* The gem5 Users mailing list > *Subj

[gem5-users] Re: What happens when a atomic only port is accessed in Timing simulation?

2022-07-06 Thread Jason Lowe-Power
Hi Zehan, Atomic memory accesses should not be used during the same simulation loop as timing accesses. I.e., you should not call "sendAtomic" on a port during the same simulation loop that you call "sendTiming". If there isn't a panic in that case, there probably should be. If you want to get a

[gem5-users] Re: _pid 100 is already used: Error gem5 - running benchmark

2022-06-27 Thread Jason Lowe-Power
th the older version of gem5, right? > > Regards > Syam > > On Fri, 24 Jun 2022, 12:43 am Jason Lowe-Power, > wrote: > >> Hi Syam, >> >> The error is that in *SE mode* you have to manually specify the PID for >> each process when you are creating the pro

[gem5-users] Re: O3CPU "panic: Is stalled should have been cleared by stalling load!" when simulating for >5Billion insts, SE and FS, AARCH64

2022-06-23 Thread Jason Lowe-Power
Hi Norbert, This is going to be a tough bug to track down! I would suggest enabling the Exec debug flag (and maybe some others for the O3CPU) and using --debug-start and starting the debug dumping a billion ticks or so before the error happens. Hopefully, you can then trace back what is causing

[gem5-users] Re: _pid 100 is already used: Error gem5 - running benchmark

2022-06-23 Thread Jason Lowe-Power
Hi Syam, The error is that in *SE mode* you have to manually specify the PID for each process when you are creating the processes in Python. However, I think you're going to run into many problems trying to simulate such a large system/workload in SE mode. For instance, I seriously doubt 3GB is

[gem5-users] Re: Gem5 segfaults in build/X86/cpu/o3/fetch.cc

2022-06-13 Thread Jason Lowe-Power
Hi Gagan, The problem is that the CPU doesn't have an ISA object as a child. Most likely, the function `createThreads()` wasn't called on the CPU instance. You need to set all of this up *in the python configuration*, not in the C++ models. Solving this problem is difficult if you're using the

[gem5-users] Re: "No alive nodes found in your cluster"

2022-06-06 Thread Jason Lowe-Power
Hi Jason, To be honest, the mailman server isn't great at providing search/archiving. I would search on mail-archive (link in previous email below) and/or use google :). Cheers, Jason On Mon, Jun 6, 2022 at 4:48 PM wrote: > Hi Jason, > > > Thank you for your reply, I am using the “Search this

[gem5-users] Re: "No alive nodes found in your cluster"

2022-06-06 Thread Jason Lowe-Power
Hi Jason, I'm not sure where you were trying to search. However, mail archive ( https://www.mail-archive.com/gem5-users@gem5.org/) is usually pretty reliable. If that's not working for you, you may be able to reach out to their support. Cheers, Jason On Mon, Jun 6, 2022 at 4:13 PM wrote: > Hi

[gem5-users] Re: mail sent to mailing list not visible in gem5-users Mail archive

2022-05-31 Thread Jason Lowe-Power
Hi Javed, I received that message. No idea why it doesn't show up on mail archive.. Cheers, Jason On Tue, May 31, 2022 at 3:33 AM Javed Osmany wrote: > Hello > > > > I sent an email the gem5-users mailing list on the 27th May 2022, titled > “CHI compilation error when trying to add L3$

[gem5-users] Re: How to make _addr version of m5 ops work on x86+syscall emulation?

2022-05-12 Thread Jason Lowe-Power
Hello, In the first case, since you're using SE mode, gem5 is trying to use /dev/mem *on your host*, not on the guest. The addr interface for the m5 ops is really meant for FS mode, not SE mode. In the second case, this is probably because KVM + SE mode is rarely, if ever, tested. I'm not

[gem5-users] Re: virtual address -> base + offset

2022-05-09 Thread Jason Lowe-Power
of the > memory address through the request > > object like this. > > req->getPaddr(); > > req->getVaddr(); > > But I would like to extract the base and offset component of the virtual > address as separate entities. Is that also possible? > > > > Thank

[gem5-users] Re: virtual address -> base + offset

2022-05-09 Thread Jason Lowe-Power
Hi Sindhuja, The WholeTranslationState object should have all of the virtual and physical address information. In fact, the Request object (a member of the Packet) should also have both virtual and physical addresses. Cheers, Jason On Mon, May 9, 2022 at 10:23 AM Sindhuja Gopalakrishnan Elango

[gem5-users] Re: fatal: Syscall 278 out of range (ARM) - can i skip/supress syscall unimplemeted errors

2022-05-09 Thread Jason Lowe-Power
Hi Tom, My guess is that you're using a newer version of GLIBC which calles different syscalls than the versions of GLIBC that have been tested with gem5. I believe 278 is mq_notify. You can try to update the syscall implementation to ignore the syscall and see if the application still works. See

[gem5-users] Re: Adding DmaDevice leads to TypeError: No constructor defined

2022-04-28 Thread Jason Lowe-Power
n/m5/SimObject.py", line 1720, in getCCParams > cc_params = cc_params_struct() > > TypeError: _m5.param_DmaDevice.DmaDeviceParams: No constructor defined! > > > > *Dma_device.cc* > > DmaDevice::DmaDevice(const Params ) > > : PioDevice(p), dmaPort(th

[gem5-users] Test email please ignore

2022-04-26 Thread Jason Lowe-Power
Sorry for the spam. We're working to fix the issues that some people have been having with our mailing list. I hope this will be the last test email for a while! Cheers, Jason ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an

[gem5-users] Re: Low memory bandwidth achieved with STREAM benchmark

2022-04-23 Thread Jason Lowe-Power via gem5-users
Majid, These are all great suggestions! Do you have a configuration file that you would be willing to share? It would be a huge benefit to the community if we had some better default configurations in the "examples" for gem5 configuration files. We're also trying to use the new standard library

[gem5-users] Re: Adding PioDevice leads to TypeError: No constructor defined

2022-04-22 Thread Jason Lowe-Power via gem5-users
I just pushed a change that will make this error message better. "fatal: Cannot instantiate an abstract SimObject (system.dev)" is what the error now says :). See https://gem5-review.googlesource.com/c/public/gem5/+/59049 Cheers, Jason On Fri, Apr 22, 2022 at 8:57 AM Jason Lowe-Po

[gem5-users] Re: Adding PioDevice leads to TypeError: No constructor defined

2022-04-22 Thread Jason Lowe-Power via gem5-users
Hello, I believe the problem is that gem5 tries to do too much automatically for you! gem5 automatically creates a lot of the constructor/destructor codes. Given all of this hidden/automatic code generation, it's difficult to know exactly what's going wrong (for both you and for us). That said,

[gem5-users] Re: Integrating MCPAT with gem5

2022-04-22 Thread Jason Lowe-Power via gem5-users
Hi Vipin, McPAT is not the same kind of simulator as SST, DRAMSim, and SystemC, so it cannot be integrated in the same way. It's not really a timing simulator at all. You can use gem5's statistics output as the "activity rate" which is one of the inputs to McPAT. However, the other inputs (e.g.,

[gem5-users] Re: How to set the Cache replacement policy

2022-04-12 Thread Jason Lowe-Power via gem5-users
Hi Ankit, I would suggest modifying your python runscript instead of using command line parameters. https://www.gem5.org/documentation/learning_gem5/introduction/ may help explain how to set parameters on SimObjects. Cheers, Jason On Wed, Apr 6, 2022 at 2:48 PM Ankit Berde wrote: > Hi Gem5

[gem5-users] Re: How does an out of order pipeline implementation handle instructions (cmp, adds,cmn etc.) which update N,Z,C,V?

2022-03-29 Thread Jason Lowe-Power via gem5-users
Hi Tom, On Tue, Mar 29, 2022 at 9:39 AM tomjosekallooran--- via gem5-users < gem5-users@gem5.org> wrote: > Hi , > This may sound very generic, but i want to try some experiments with the > out of order implementation. I came across few scenarios, which are listed > below (any input would be

[gem5-users] Re: Problem with SimObject

2022-03-28 Thread Jason Lowe-Power via gem5-users
Hi Artyom, You're absolutely right that the tutorial needs to be updated! The website is also open source and managed via a git repo: https://gem5.googlesource.com/public/gem5-website/. Updating this would be a good way to get started contributing to gem5 :). By the way, for the namespace, you

[gem5-users] Re: gem5 and non volatile memory

2022-03-25 Thread Jason Lowe-Power via gem5-users
Hello Taiyu, I would suggest reaching out to the VANS authors. Since this project is not part of the gem5 repository, we have little control over the integration. Cheers, Jason On Thu, Mar 24, 2022 at 8:49 PM Taiyu Zhou via gem5-users < gem5-users@gem5.org> wrote: > Could you give me some

[gem5-users] Re: CXL protocol/model implementation

2022-03-25 Thread Jason Lowe-Power via gem5-users
Hi Zicong, 1. I personally don't believe that CXL in SE mode would be very interesting. From my point of view, CXL would be interesting only to capture the OS and system-level effects. That said, you may be able to test CXL.cache in SE mode. 2. To implement the different protocols: CXL.io: This

[gem5-users] Re: Issue with strange virtual address access

2022-03-22 Thread Jason Lowe-Power via gem5-users
Hi Tom, I'm not sure. Again, I'd add the Vma and the SyscallVerbose debug flags which may help figure it out. It's possible that's the address of a dynamically-loaded library as well. Also, this trace looks like it came from Arm instead of x86. I don't have as much experience looking at Arm

[gem5-users] Re: Building Old gem5 error

2022-03-22 Thread Jason Lowe-Power via gem5-users
Hello Abdelrahman, Unfortunately, it's incredibly difficult to keep the development environment for older versions of gem5 working. You may be able to find an old dockerfile in those gem5 repositories that could help to recreate the build environment. (I'm not sure if we were using docker at the

[gem5-users] Re: Issue with strange virtual address access

2022-03-22 Thread Jason Lowe-Power via gem5-users
Hi Liyan, This looks like a stack address to me, so it won't appear in the objdump. Since you're using SE mode, gem5 is controlling the physical address mappings (not the OS). You can use the "Vma" debug flag to see all of the virtual memory areas that gem5 creates/assigns. the "SyscallVerbose"

[gem5-users] Re: How do I disable most statistics in the stats.txt under Atomic CPU

2022-03-17 Thread Jason Lowe-Power via gem5-users
Hello, I don't believe there's a way to do that right now. However, in atomic mode, many stats *are* skipped as they are only accessed in the "timing" functions. I doubt it would make much performance difference. However, that's just a guess, and I could be wrong. Cheers, Jason On Wed, Mar 16,

[gem5-users] Re: Is thread lock not working under both SE and FS mode?

2022-03-14 Thread Jason Lowe-Power via gem5-users
Hi Meng, It depends on the ISA you're using and the configuration of the system. For instance, x86+classic caches is known to have some synchronization issues. The transactional memory support only works with Arm, and I'm not sure which memory system it requires. What system are you trying to

[gem5-users] Re: Running FS in example/gem5_library/x86-spec-cpu2017-benchmarks.py

2022-03-10 Thread Jason Lowe-Power via gem5-users
gem5? >- My understanding is that the FS simulation is significantly slow. >Any guidelines on how to make it as fast as possible? > > Above all, thanks a lot for taking time helping us. Much appreciated! > > > > > On Thu, Mar 10, 2022 at 7:01 AM Jason Lowe-Power

[gem5-users] Re: Running FS in example/gem5_library/x86-spec-cpu2017-benchmarks.py

2022-03-10 Thread Jason Lowe-Power via gem5-users
Hi Abdelrahman, >From the get error message, it says: "This error may be caused by a too restrictive setting in the file '/proc/sys/kernel/perf_event_paranoid' The default value was changed to 2 in kernel 4.6 A value greater than 1 prevents gem5 from making the syscall to perf_event_open"

[gem5-users] Re: M5 Fs utility workbegin

2022-03-09 Thread Jason Lowe-Power via gem5-users
ning first in KVM mode on a x86 host hoping to switch CPUs > once the work start event happens. Are magic ops unsupported in KVM mode? > > Thanks! > > > On Wednesday, March 9, 2022, 09:14:24 AM PST, Jason Lowe-Power via > gem5-users wrote: > > > Hi George, > >

[gem5-users] Re: M5 Fs utility workbegin

2022-03-09 Thread Jason Lowe-Power via gem5-users
Hi George, For workbegin/workend, they can be called from within applications if you link to the libm5 library. For instance, in the parsec resource here: https://resources.gem5.org/resources/parsec we use the m5_workbegin() function in the ROI hooks. See

[gem5-users] Re: Inquiry on the gem5 communities and forums

2022-02-18 Thread Jason Lowe-Power via gem5-users
Hi Jianda, There will also be a tutorial and workshop at ISCA in New York this year (June 11). More info coming soon! Cheers, Jason On Fri, Feb 18, 2022 at 8:21 AM Gabriel Busnot via gem5-users < gem5-users@gem5.org> wrote: > Hi and welcome Jianda, > > You are in the right place! Feel free to

[gem5-users] Re: Not able to access webpage to run_npb.py

2022-02-17 Thread Jason Lowe-Power via gem5-users
Hi David, Sorry for the confusion. We need to update that documentation! You can now find the script here: https://gem5.googlesource.com/public/gem5/+/refs/heads/stable/configs/example/gem5_library/x86-npb-benchmarks.py (or in configs/example/gem5_library in the gem5 repo). Cheers, Jason On

[gem5-users] Re: Does the gem5 v21.0.1.0 support to bootup with kernel 5.10 in Ruby-CHI and O3

2022-02-16 Thread Jason Lowe-Power via gem5-users
Hello, This specific setup has not been tested, as far as I know. I would also suggest using v21.2.1 as there have been lots of bugfixes to CHI in the past year. Cheers, Jason On Tue, Feb 15, 2022 at 6:23 PM Liyichao via gem5-users wrote: > Hi All: > > Does the gem5 v21.0.1.0 support

[gem5-users] Re: Run srsRAN code with gem5

2022-02-11 Thread Jason Lowe-Power via gem5-users
Hi Uma, Not all X86 vector instructions are implemented. What you're seeing is that pmovzxbw isn't implemented. Specifically, there's at least one version (as shown here https://www.felixcloutier.com/x86/pmovzx) which hasn't been implemented yet. I'm not sure which one. The `Vdq_Udq_or_Mq`

[gem5-users] Re: findOrCreate function

2022-02-09 Thread Jason Lowe-Power via gem5-users
Hi Scott, I think the answer is the same as the prior email. You need to register an exit callback to close the file stream :). See, for instance, the elastic trace code: https://gem5.googlesource.com/public/gem5/+/refs/heads/stable/src/cpu/o3/probe/elastic_trace.cc#103 Cheers, Jason On Wed,

[gem5-users] Re: Destructor for BaseCPU

2022-02-09 Thread Jason Lowe-Power via gem5-users
Hi Scott, If you want something to execute before gem5 is completed, you can call `registerExitCallback`. See http://doxygen.gem5.org/release/current/namespacegem5.html#abcf3056836ee522620e5b14d9392ea87 I *think* that will solve your problem, but let me know if not. I don't think there's a clean

[gem5-users] Re: Problems on creating HelloObject & re-compiling following tutorial

2022-02-02 Thread Jason Lowe-Power via gem5-users
Namespaces were recently added to gem5 and the documentation hasn't been updated, yet. We'll put that on the to do list. Cheers, Jason On Wed, Feb 2, 2022 at 6:11 AM Zhang Zhiyuan via gem5-users < gem5-users@gem5.org> wrote: > Dear gem5 faculties: > > Hi! I’ve been trying to follow the getting

[gem5-users] Re: Clarification minor CPU “in-order”

2022-01-29 Thread Jason Lowe-Power via gem5-users
Good question, Felix! The short answer is that since there are instructions that take multiple cycles to execute you need something like a scoreboard to track the dependencies. In the H book, you can see some details of this in Appendix C.5 (6th edition). If you happen to have the Patterson and

[gem5-users] Re: Compiling gem5 on ARM Based Host

2022-01-07 Thread Jason Lowe-Power via gem5-users
Hi Sam, I was wondering when this problem would come up again. Here's a Jira issue to track the same thing in a different context: https://gem5.atlassian.net/browse/GEM5-1003 Could you do something like `du -h build/ | sort -h` to see what objects are the biggest? I'm going to guess that there

[gem5-users] Re: some problem about IO device's write or read function's return tick

2021-12-27 Thread Jason Lowe-Power via gem5-users
Hello, If you are using *atomic* memory mode, then the tick number is mostly ignored. If you're using *timing* mode, then the tick number should be used by whatever object calls the read/write function and the delay is inserted there. Also, if your program doesn't have a direct dependence on the

[gem5-users] Re: RISCV Full System with Ruby

2021-12-27 Thread Jason Lowe-Power via gem5-users
Hi Fu, You can modify that file to import a Ruby-based cache hierarchy (e.g., MESI_Two_Level and MI_Example have been tested). Or, better yet, create your own run script. `riscv_fs.py` is just an *example* of how to use the standard library components. Cheers, Jason On Fri, Dec 24, 2021 at 7:57

[gem5-users] Re: Adding use of an external library

2021-12-20 Thread Jason Lowe-Power via gem5-users
Hi Elliot, You may be able to get some inspiration from the code in gem5/ext/*. This is where we have included external libraries. Cheers, Jason On Fri, Dec 17, 2021 at 6:21 PM Eliot Moss via gem5-users < gem5-users@gem5.org> wrote: > > I have an external library that I would like to link with

[gem5-users] Re: Deadlock with pthread and DerivO3CPU in SE mode

2021-12-16 Thread Jason Lowe-Power via gem5-users
ith full system mode? Or do I also need to use, e.g., ruby caches? > > Thanks, > Brian > > On Thu, Dec 16, 2021 at 9:23 AM Jason Lowe-Power > wrote: > >> Hi Brian, >> >> A few quick thoughts: >> 1. x86 + classic cache + multicore is not supported. There

[gem5-users] Re: Deadlock with pthread and DerivO3CPU in SE mode

2021-12-16 Thread Jason Lowe-Power via gem5-users
Hi Brian, A few quick thoughts: 1. x86 + classic cache + multicore is not supported. There is a changeset on gerrit (https://gem5-review.googlesource.com/c/public/gem5/+/52303) which may fix this, but it has not been tested widely. 2. SE mode + pthreads will likely not work in all circumstances.

[gem5-users] Re: Run Timed Simulation (Stop After Certain Time)

2021-12-08 Thread Jason Lowe-Power via gem5-users
and the other for the actual simulation. > > Thanks. > > -- > > *Best,Abdelrahman Hussein* > > > On Mon, Dec 6, 2021 at 8:57 AM Jason Lowe-Power > wrote: > >> Hi Abdelrahman, >> >> I think you have the right approach. Is the simulation not exit

[gem5-users] Re: Run Timed Simulation (Stop After Certain Time)

2021-12-06 Thread Jason Lowe-Power via gem5-users
Hi Abdelrahman, I think you have the right approach. Is the simulation not exiting after the warmup_inst instructions? Cheers, Jason On Sat, Dec 4, 2021 at 11:43 PM Abdelrahman S. Hussein via gem5-users < gem5-users@gem5.org> wrote: > Hello, > > I am trying to warm up my gem5 in order to train

[gem5-users] Re: fatal when adding a new CPU

2021-11-03 Thread Jason Lowe-Power via gem5-users
Hi Fengze, Yeah, there's a lot of complicated and undocumented things you need to do when initializing a CPU. Here's a couple of pointers that may help. However, this code was written a few years ago and is almost 4000 commits behind, so things have probably changed since then! Code:

[gem5-users] Re: RISCV Full System with Ruby

2021-11-02 Thread Jason Lowe-Power via gem5-users
Hello, Yes. MI_example and MESI_Two_Level have been tested with the RISC-V board in the components library. See https://gem5.googlesource.com/public/gem5/+/refs/heads/develop/configs/example/components-library/riscv_fs.py I am working on the CHI protocol. I have a WIP changeset that I could

[gem5-users] Re: m5 pesudo

2021-11-01 Thread Jason Lowe-Power via gem5-users
Hello, The m5 magic operations (either via magic instructions or addresses) will work with all CPU models. Cheers, Jason On Sat, Oct 30, 2021 at 8:31 PM Liyichao via gem5-users wrote: > Hi All: > > Does “m5 --addr 0x1001 exit” take effect in the O3 system? > > >

[gem5-users] Re: Vector Instructions Support

2021-10-29 Thread Jason Lowe-Power via gem5-users
wrote: > Hi > > Thanks for the information. I will check the code base for that. Do you > have any suggestions for the documentation regarding it ? > > > Regards > Nitesh > > On Thu, 28 Oct 2021 at 17:53, Jason Lowe-Power > wrote: > >> Hello, >> >

[gem5-users] Re: Vector Instructions Support

2021-10-28 Thread Jason Lowe-Power via gem5-users
Hello, For Arm, gem5 has SVE support and (some/most/all?) of the NEON instructions. For x86, we support most 128-bit SIMD instructions, but very few or no 256-bit or 512-bit SIMD instructions. I have heard of forks/groups that have implemented many of the x86 vector instructions, and I have heard

[gem5-users] Re: How to map elf section to physical memory

2021-10-26 Thread Jason Lowe-Power via gem5-users
Hi Jose, This is an interesting question! My quick suggestion would be to "hack" the loader/page table to skip the mapping portion when loading the elf section. I don't fully understand exactly what the underlying "problem" is. That said, we may be able to solve it "correctly" by generally

[gem5-users] Re: L2 or L3 cache interface

2021-10-25 Thread Jason Lowe-Power via gem5-users
Hi Fengze, No, there is no defined interface between different levels of the cache in Ruby. Ruby is a "black box" in some sense, with input on the CPU side and output on the memory side. See https://www.gem5.org/documentation/learning_gem5/part3/MSIintro/ and

[gem5-users] Re: Use xbar stat in BaseCPU

2021-10-22 Thread Jason Lowe-Power via gem5-users
Hi Victor, It's not super easy to access stats between SimObjects. I would suggest computing any and all formulas after running the simulation, not during the simulation loop. You can either parse the stats.txt or use the new python stats interface (

[gem5-users] Re: SPEC 2017 Benchmarks: Input Files Not Found

2021-10-18 Thread Jason Lowe-Power via gem5-users
Hi Reiko, I would guess that it's a permission issue as well. Maybe, by default, when booting the image it logs in as a regular user? What I would do is not pass the rcS script and log in interactively with the m5term (see util/term). Then, run the commands in the rcS file one at a time manually

[gem5-users] Re: Pseudo Instruction - m5_reset_stats() - Body Modification

2021-10-12 Thread Jason Lowe-Power via gem5-users
; On Mon, Oct 4, 2021 at 12:08 PM Jason Lowe-Power > wrote: > >> Hi Sampad, >> >> Here is where m5_reset_stats is implemented in the simulator: >> https://gem5.googlesource.com/public/gem5/+/refs/heads/stable/src/sim/pseudo_inst.cc#303 >> >> There are a l

[gem5-users] Re: Seg. Fault while "Creating a simple configuration script"

2021-10-08 Thread Jason Lowe-Power via gem5-users
Hello, Does the file configs/learning_gem5/part1/simple.py work for you? If so, then there is probably a small mistake in your configuration script. If this is the case, can you send your script (maybe off list)? I would like to understand the problem and improve the error message. Cheers, Jason

[gem5-users] Re: Porting a configuration file from gem5 v20 to gem5 v21

2021-10-06 Thread Jason Lowe-Power via gem5-users
Hi Ali, Is your guest code 32-bit Arm? If so, I think this could be the problem in SE mode: https://gem5.atlassian.net/browse/GEM5-1074 Cheers, Jason On Tue, Oct 5, 2021 at 7:45 AM Ali Ghandour via gem5-users < gem5-users@gem5.org> wrote: > In FS mode, full errror stack below: > > Traceback

[gem5-users] Re: Pseudo Instruction - m5_reset_stats() - Body Modification

2021-10-04 Thread Jason Lowe-Power via gem5-users
Hi Sampad, Here is where m5_reset_stats is implemented in the simulator: https://gem5.googlesource.com/public/gem5/+/refs/heads/stable/src/sim/pseudo_inst.cc#303 There are a large number of steps between when the guest code calls m5_reset_stats and when the above function executes, but this

[gem5-users] Re: Get Size of Stack and Heap

2021-09-30 Thread Jason Lowe-Power via gem5-users
Hi Ange, If you're using SE mode, you may be able to augment the allocation code to track the heap size. E.g., https://gem5.googlesource.com/public/gem5/+/refs/heads/stable/src/sim/mem_state.cc#108 In fact, the MemState object tracks both the stack and the heap, so you can get a lot of

[gem5-users] Re: gem5art, FS mode, panic: PerfKvmCounter (perf_event_paranoid is set to -1)

2021-09-23 Thread Jason Lowe-Power via gem5-users
es! Seems like quite a can of worms.It's almost > looking like it could be easier to partition a computer for Linux and start > over. Would you recommend that as an alternative? > > All th > > On Thu, Sep 23, 2021 at 1:36 PM Jason Lowe-Power via gem5-users < > gem5-use

[gem5-users] Re: gem5art, FS mode, panic: PerfKvmCounter (perf_event_paranoid is set to -1)

2021-09-23 Thread Jason Lowe-Power via gem5-users
Hi Reiko, The KVM CPU requires that the host platform supports KVM. Given that you're using WSL, this means that you need to have nested virtualization enabled and implemented on your WSL kernel.

[gem5-users] Re: Problems with Deprecated names are not supported by the compiler

2021-09-23 Thread Jason Lowe-Power via gem5-users
Hi Xihui, The error is "died with " I would guess you're out of memory or trying to compile too many files at once. But, it could be many different problems. If it's an issue with dependencies or your host, you can always use our docker images:

[gem5-users] Re: Problems with Deprecated names are not supported by the compiler

2021-09-20 Thread Jason Lowe-Power via gem5-users
Hi Xihui, That's just a warning and you can safely ignore it. The most recent hotfix release should remove this warning as well. Cheers, Jason On Sun, Sep 19, 2021 at 10:02 PM Xihui Yuan via gem5-users < gem5-users@gem5.org> wrote: > Hello everyone: > > I am a beginner with GEM5. >

[gem5-users] Re: --take-checkpoints flag

2021-09-08 Thread Jason Lowe-Power via gem5-users
k I've honed in on the source of the problem > -- namely, number of cpus. Is there a reason why having multiple CPUs in a > particular configuration would limit the simulator's ability to write a > checkpoint? > > Again, thank you for your help! > > Best, > Sam > > On Wed, Sep

[gem5-users] Re: Is it ok to remove `maxRoutingTableSizeCheck`?

2021-09-08 Thread Jason Lowe-Power via gem5-users
Hi Emil, You can remove that check. However, you should note that the classic caches aren't designed to support high-bandwidth operation. Also, this assert triggering could be a sign that there's infinite queuing somewhere (which is one reason why the classic caches aren't great for high

[gem5-users] Re: --take-checkpoints flag

2021-09-08 Thread Jason Lowe-Power via gem5-users
Hi Sam, Sorry for the frustration. Writing better documentation is always #2 on the priority list :(. I always tell people not to trust any of the "options" to fs.py and se.py. Those scripts have gotten so far beyond "out of hand" at this point that they are almost useless. They are trying to be

[gem5-users] Re: Query: Valgrind speed in FS

2021-09-07 Thread Jason Lowe-Power via gem5-users
Hi Sindhuja, Yes, there is an expectation that valgrind causes a slowdown. Let me give you a couple of suggestions. 1. Make sure you compile without tcmalloc (e.g., scons build//gem5.opt --without-tcmalloc). Using tcmalloc will make valgrind miss all allocations. 2. Use the suppressions file in

[gem5-users] Re: regarding building of dependencies

2021-09-02 Thread Jason Lowe-Power via gem5-users
Hello, It should be X86 (capitol X) instead of x86. You can see the files in gem5/build_opts for the different possibilities for default build variables. Cheers, Jason On Thu, Sep 2, 2021 at 3:58 AM Sravani Sravanam 20PHD7041 via gem5-users < gem5-users@gem5.org> wrote: > sir, > i am sravani

[gem5-users] Re: Collecting Two Sets of Data Within Same Simulation

2021-08-13 Thread Jason Lowe-Power via gem5-users
Hi Sam, This is a use case that I don't think we've thought about in the mainline gem5. I think the easiest solution would be to add some custom Statistics objects to track the info from the function you're interested in. Cheers, Jason On Wed, Aug 11, 2021 at 10:59 AM Thomas, Samuel via

[gem5-users] Re: 答复: gem5 v21.1 released!

2021-07-29 Thread Jason Lowe-Power via gem5-users
Hi Liyichao, We welcome contributions to the gem5 resources! Currently, we have full system resources available for x86 and one available for RISC-V. We don't have any Arm resources available right now, but that's only because we haven't had the time (or resources ;)) to get around to it. Again,

[gem5-users] Re: ARM KVM

2021-07-12 Thread Jason Lowe-Power via gem5-users
To use hardware-accelerated virtualization (i.e., KVM) your host and guest must have the same ISA (and the host must have virtualization extension). Cheers, Jason On Mon, Jul 12, 2021 at 12:17 PM Νικόλαος Ταμπουρατζής via gem5-users < gem5-users@gem5.org> wrote: > Dear gem5 community, > > I

[gem5-users] Re: Custom SimObject Causes Host Machine to Freeze

2021-07-06 Thread Jason Lowe-Power via gem5-users
Hi Sam, My suggestion would be to use gdb. You can run gem5 in gdb and then use ctrl-c to stop the execution and see where the program is getting stuck. Also, enabling debug flags (or just good ole printf debugging) can also be useful in these cases. Another option with gdb would be to put

[gem5-users] Re: question about RSCV-V implementation on Gem5

2021-07-05 Thread Jason Lowe-Power via gem5-users
See https://gem5.atlassian.net/browse/GEM5-618 On Sat, Jul 3, 2021 at 5:23 PM lovline via gem5-users wrote: > Hi, >We are working on an important project, and we want to use RSCV-V1.0 > vector instructions on Gem5. >But we cann't find any features or codes about RSCV-V on Gem5. >We

[gem5-users] Re: does gem5 have a C++ API?

2021-07-02 Thread Jason Lowe-Power via gem5-users
he > examples, > but hopefully at least 100x faster than this. > > What's the best supported mechanism for running many tiny simulations > w/o having to pay for the large python overhead? > Any examples? > > --kcc > > > > > > > On Thu, Jul 1, 202

[gem5-users] Re: does gem5 have a C++ API?

2021-07-01 Thread Jason Lowe-Power via gem5-users
Hello, It's somewhat possible. You can compile gem5 as a library (e.g., scons build//libgem5-opt.so). However, gem5 *is a python interpreter* and is configured via python scripts. Getting that to work with an external program is "exciting". It's possible to get python working, and there are other

[gem5-users] Re: gem5 + GPU support?

2021-06-30 Thread Jason Lowe-Power via gem5-users
Hi Adrian, The AMD GPU model has never been tested with Arm. I doubt the ROCm stack will compile/work with any ISA other than x86, unfortunately. For multi-GPU support see http://www.gem5.org/2020/05/30/enabling-multi-gpu.html Of course, multiple CPUs will work with no problem with or without

[gem5-users] Re: gem5 + GPU support?

2021-06-30 Thread Jason Lowe-Power via gem5-users
Hi Adrian, gem5 has support for AMD's GCN3 (compute) GPU in SE mode, and we're working on merging both Vega support (AMD's newer GPU ISA) and full system support. The status of these new features can be followed on Jira. Here's documentation on the current GPU support:

[gem5-users] Re: Fatal error while running multithreaded program in SE mode

2021-06-25 Thread Jason Lowe-Power via gem5-users
What version of gem5 are you using? I believe gem5-20.0+ has the getdents syscall implemented. I'm sure that 21.0 has the syscall implemented. Whether you're using Ruby or classic caches it shouldn't make any difference on whether the syscalls are implemented. Cheers, Jason On Fri, Jun 25, 2021

[gem5-users] Re: gem5 RISCV, issue on boot when mounting filesystem

2021-06-25 Thread Jason Lowe-Power via gem5-users
Hi everyone, These details on gem5-resources have also been tested multiple times. We have also gotten unmodified OpenSBI working with gem5 as well. Ayaz can provide more details if you need. https://gem5.googlesource.com/public/gem5-resources/+/refs/heads/stable/src/riscv-fs/ Cheers, Jason On

[gem5-users] Re: Understanding write timing in MemCtrl

2021-06-22 Thread Jason Lowe-Power via gem5-users
Hi Vincent, It depends on when/how you're ending the simulation. If you end the simulation at some particular tick, then you'll see writes left in the write queue. Just like a real machine, writes don't happen instantaneously, and at some point in time, there are writes sitting in the write

[gem5-users] Re: Memory-Intensive C Programs in SE Mode

2021-06-21 Thread Jason Lowe-Power via gem5-users
Hi Sam, Are the (virtual, physical?) addresses different when you use the larger arrays? I wonder if the underlying mmap or malloc calls are breaking in SE mode somehow. Maybe, after you allocate in your guest code you can print out the virtual address to make sure it looks reasonable. You can

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