[gem5-users] Re: Difference between using the Configuration Script vs Standard Library?

[Jason Lowe-Power via gem5-users]

Hi Kaze,

Thank you for reaching out and expressing your interest in gem5
simulations. I understand that you’re curious about the difference between
the configuration script and the standard library when executing the SE
binary with the same parameters.

gem5’s interface is primarily based on Python scripts. These scripts are
written by users like yourself to control the simulation. The standard
library, on the other hand, is a collection of Python classes that serve as
a wrapper for gem5’s models, which are written in C++.

The standard library Python classes are essentially instances of gem5’s
models, with specific parameters already set for you. This means that when
you’re using the standard library, you’re using pre-configured instances of
the models, which can simplify the process of setting up your simulation.

Therefore, when you want to create a simulation for a system you’re
interested in modeling, you should write a Python script that utilizes
these standard library Python classes. This approach allows you to leverage
the pre-set parameters of the standard library and focus more on the
specifics of your system model.

I hope this explanation helps clarify your confusion. If you have any more
questions or need further clarification, please don’t hesitate to ask.

Cheers,
Jason


On Sat, Apr 6, 2024 at 11:18 AM Kaze Kuma via gem5-users <
gem5-users@gem5.org> wrote:

> Hi, I recently started using Gem5 and playing around with the simulations
> using tte tutorials for reference, but I'm kinda confused on why and how
> the configuration script differs for output from using the standard library
> if using the same parameters for executing SE binary?
> If someone could explain, I'd greatly appreciate it!
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[gem5-users] Re: catching the traces of communication between the processors

[Jason Lowe-Power via gem5-users]

Note: this is the output from the gem5 GPT (
https://chat.openai.com/g/g-o3y1y4t8J-gem5-gpt/)

Certainly, Ojas!

To capture traces of communication between processors in your gem5
simulation, a more specialized approach involves using the Communication
Monitor component. This feature is designed to monitor and record various
types of communication events within the system, making it an ideal tool
for your needs.

Here's how you can utilize the Communication Monitor in gem5:

### 1. **Enable the Communication Monitor in Your Configuration**

The Communication Monitor needs to be explicitly enabled and configured in
your system definition. This usually involves modifying your Python
simulation script to include the monitor in the system interconnects or
between specific components that you're interested in observing.

For instance, if you're using a simple system with a few cores and want to
monitor the traffic between them, you would integrate the Communication
Monitor into the system's interconnects. This might look something like
adding a monitor component to the bus or directly between caches and
processors, depending on your system architecture.

### 2. **Configure the Monitor**

The Communication Monitor can be configured to capture various types of
data, such as packet transfers, latency information, and bandwidth usage.
You'll need to decide what information is relevant for your analysis and
configure the monitor accordingly. This could involve setting parameters
for what types of transactions to record, whether to capture all
transactions or only those that meet certain criteria, and how to log this
information.

### 3. **Run the Simulation**

With the Communication Monitor configured, run your simulation as usual.
The monitor will operate in the background, capturing data on the
communication patterns and events that occur during the simulation.

### 4. **Analyze the Results**

After the simulation, the Communication Monitor will produce output that
details the observed communication events. This output will typically be in
a form that can be easily analyzed, such as a CSV file or a series of log
entries. You can use this data to understand the communication patterns,
identify bottlenecks, and make informed decisions about optimizing your
system.

### 5. **Adjust and Iterate**

Based on your findings, you may want to adjust the configuration of the
Communication Monitor or the system itself to capture additional data or
focus on specific areas of interest. This iterative process can help refine
your understanding and optimize your system's performance.

### Additional Notes:

- Integrating the Communication Monitor requires some familiarity with
gem5's configuration scripts and potentially modifying existing system
definitions. If you're new to this, it might take some time to get used to
how these scripts work.
- The gem5 documentation and specific guides on the Communication Monitor
can provide more detailed instructions and examples on how to set up and
use this feature effectively.

Using the Communication Monitor offers a targeted approach to understanding
processor communication in your gem5 simulations, providing valuable
insights that can guide system optimization and research. If you have
further questions or need clarification on the setup, feel free to ask!

More sources: https://www.youtube.com/watch?v=TeHKMVOWUAY,
https://www.mail-archive.com/gem5-users@gem5.org/msg18792.html

On Fri, Feb 23, 2024 at 10:53 AM Flash Mobster via gem5-users <
gem5-users@gem5.org> wrote:

> I am new to GEM5, and I want to catch traces of communication between the
> processors in my defined system. How exactly can this be done? I read
> somewhere that --debug is needed for this. Can someone please tell me what
> should I do?
>
> thanks,
> Ojas
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[gem5-users] Re: Limit debug output to certain instruction address range

[Jason Lowe-Power via gem5-users]

Hi Hossam,

If you're using the stdlib, you can override the default ROI begin handler.
See the documentation here:
https://github.com/gem5/gem5/blob/stable/src/python/gem5/simulate/simulator.py#L145

If you're not using the stdlib, then look for where the code you're using
calls m5.stats.dump() and comment it out :)

Cheers,
Jason

On Wed, Feb 21, 2024 at 4:59 PM Hossam ElAtali 
wrote:

> Hi Jason,
>
> Thanks for the very quick response!
>
> I managed to surround the ROI with m5op instructions to issue WORKBEGIN
> and WORKEND events,  but now the stats.txt​ file is getting out of hand.
> It dumps stats every time the simulation pauses. Is there a way to make it
> not dump on every event or disable it altogether? I tried using the
> --stats-file​ command line option with an empty string but that caused a
> crash. I also tried truncating and/or deleting the file in the event
> handler in the config script (using the open and truncate python
> functions), but that did nothing (my guess is because the file is already
> open elsewhere).
>
> Thanks again!
>
> Best,
> Hossam
> --
> *From:* Jason Lowe-Power 
> *Sent:* Wednesday, February 21, 2024 1:59 PM
> *To:* The gem5 Users mailing list 
> *Cc:* Hossam ElAtali 
> *Subject:* Re: [gem5-users] Limit debug output to certain instruction
> address range
>
> Hi Hossam,
>
> >  Yet another option is a way to enable/disable debugging in the config
> script mid-simulation. This would allow me to exit the simulation using an
> m5op before the instructions, enable debugging in the config script,
> continue, exit using an m5op after the instructions, disable debugging, etc.
>
> You can definitely do this.
>
> You can use the m5.trace.enable()  and m5.trace.disable() functions in
> python to enable and disable the debug output. You can use m5 ops to exit
> the simulation as you mentioned as well and then call these functions.
>
> Cheers,
> Jason
>
> On Wed, Feb 21, 2024 at 10:46 AM Hossam ElAtali via gem5-users <
> gem5-users@gem5.org> wrote:
>
> Hi,
>
> I'm currently experimenting with Spectre on gem5, and I'm dumping
> debugging output using the O3PipeView flag. However, I get a lot of output
> for instructions that are not relevant to the attack sequence. I was
> wondering if it's possible to limit the debugging output to a certain
> instruction address range. I know I can limit it to a tick range, but I'd
> like to dump every instance of the attack, not just a specific one. I have
> the instruction addresses for the attack and it would be great if I can
> just use that.
>
> Another option would be to dynamically enable and disable debugging output
> (or the O3PipeView flag, at least) using an m5op.
>
> Yet another option is a way to enable/disable debugging in the config
> script mid-simulation. This would allow me to exit the simulation using an
> m5op before the instructions, enable debugging in the config script,
> continue, exit using an m5op after the instructions, disable debugging, etc.
>
> Any help is greatly appreciated. Thank you.
>
> Best,
> Hossam
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>
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[gem5-users] Re: Can I use RiscvO3CPU with TSO?

[Jason Lowe-Power via gem5-users]

Hello,

That *should* work, but my confidence isn't very high. I suggest running
tests to see if you can produce TSO and non-TSO executions with and without
the option.

Cheers,
Jason

On Thu, Feb 15, 2024 at 12:32 PM Z HW via gem5-users 
wrote:

>
> I know that RISC-V assumes RVWMO. But if I want to run a TSO RISC-V
> implementation, can I simply set needsTSO = True in the RiscvO3CPU
> configuration and be done, or am I overlooking some details about using TSO
> in RISC-V?
>
> I need TSO because I want to enforce load->load, load->store ordering by
> default in my program and don't want to use fences.
>
> Thanks!
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[gem5-users] Re: Executing Binary Code in FS without a Kernel

[Jason Lowe-Power via gem5-users]

Hi Alain,

I'm the gem5-GPT bot, here to assist with your queries about the gem5
simulator. Please note that while I aim to provide accurate information, my
responses could be wrong or may have been slightly edited for clarity. You
can access the gem5-GPT on chat.openai.com/g/g-o3y1y4t8J-gem5-gpt if you
subscribe to chatGPT.

Welcome to the world of gem5, Alain! Let's address your inquiries one by
one:

1. **Full System (FS) Mode and the Requirement of a Kernel**:
   In gem5's Full System (FS) mode, the simulation environment is designed
to emulate an entire computer system, including processors, memory, and I/O
devices. This mode indeed requires a kernel, as it simulates the hardware
and software interactions that occur in a real system. The kernel is
responsible for managing the hardware resources, including CPU scheduling,
memory management, and the handling of I/O operations. Therefore, to run
binary code in FS mode, you must have an operating system kernel (such as
Linux) loaded and configured to bootstrap the system and execute your
binary code.

2. **Mounting I/O Devices, Including Disk Images**:
   In FS mode, the mounting and management of I/O devices, including disk
images, are typically handled by the kernel. The kernel uses device drivers
to interact with the hardware simulated by gem5, such as disk drives. You
can specify disk images in your gem5 simulation setup, and these will be
recognized as physical disks by the simulated kernel, which can then mount
the filesystems contained within them, similar to how a real system
operates.

   However, you do have the ability to configure certain aspects of how
these devices are presented to the simulated system through gem5's
configuration scripts. For example, you can specify the disk image to use,
the type of disk (e.g., IDE, SATA), and the connection point (e.g., primary
master) in the system's configuration file. This setup is part of the
simulation environment configuration and is done before starting the
simulation.

To summarize, running assembly benchmark code that accesses memory
addresses pre-dumped on a RAW disk image in FS mode requires:
- An operating system kernel to manage hardware interactions, including
those with the disk image.
- Configuration of the gem5 simulation environment to include the disk
image as part of the simulated system's hardware, which the kernel will
then manage.

If you're looking to run binaries without involving a full operating system
kernel, gem5's System Call Emulation (SE) mode is what you're looking for.
SE mode allows you to run user-level applications directly on gem5, with
the simulator providing a minimal environment to handle system calls made
by the application. Here's a detailed overview of SE mode and its
implications for your project:

### SE Mode Overview

- **Direct Execution of Binaries**: SE mode enables the direct execution of
compiled binary applications without the need for a full operating system.
This mode is particularly useful for running benchmarks or specific
application tests where the overhead and complexity of simulating an entire
OS are unnecessary.

- **System Call Emulation**: gem5 in SE mode emulates the system calls that
the application makes. This emulation is handled internally by gem5, which
intercepts system calls and provides the necessary responses, simulating
the effect of having an OS handle these calls. This includes calls for file
I/O, memory allocation, and process control, among others.

- **Simplified I/O and Filesystem Interaction**: Although SE mode can
emulate system calls related to file I/O, the way it handles disk images
and I/O devices is different from FS mode. You can specify input and output
files for your application through gem5's command-line options, but the
direct simulation of disk images as block devices (like in FS mode) is not
supported. Instead, you would typically use virtual filesystems or specify
file paths that gem5 will redirect to real files on your host system.

### Running Binaries in SE Mode

To run a binary in SE mode, you'll generally follow these steps:

1. **Compile Your Binary**: Ensure your benchmark or application is
compiled for the target architecture you intend to simulate (e.g., ARM,
x86).

2. **Set Up Your gem5 Simulation Script**: Configure a gem5 simulation
script to run in SE mode. This script specifies the binary to execute,
along with any arguments or environment variables needed by the application.

3. **Specify File Inputs/Outputs**: If your application expects to read
from or write to files, you can use gem5's options to map these files
within the simulation environment. This allows your application to interact
with files as if it were running on a real system.

4. **Run the Simulation**: Execute your simulation script with gem5, which
will start the application in SE mode, handle its system calls, and
simulate its execution on the specified architecture.

### Limitations and Considerations

- **Limited Device 

[gem5-users] Re: Limit debug output to certain instruction address range

[Jason Lowe-Power via gem5-users]

Hi Hossam,

>  Yet another option is a way to enable/disable debugging in the config
script mid-simulation. This would allow me to exit the simulation using an
m5op before the instructions, enable debugging in the config script,
continue, exit using an m5op after the instructions, disable debugging, etc.

You can definitely do this.

You can use the m5.trace.enable()  and m5.trace.disable() functions in
python to enable and disable the debug output. You can use m5 ops to exit
the simulation as you mentioned as well and then call these functions.

Cheers,
Jason

On Wed, Feb 21, 2024 at 10:46 AM Hossam ElAtali via gem5-users <
gem5-users@gem5.org> wrote:

> Hi,
>
> I'm currently experimenting with Spectre on gem5, and I'm dumping
> debugging output using the O3PipeView flag. However, I get a lot of output
> for instructions that are not relevant to the attack sequence. I was
> wondering if it's possible to limit the debugging output to a certain
> instruction address range. I know I can limit it to a tick range, but I'd
> like to dump every instance of the attack, not just a specific one. I have
> the instruction addresses for the attack and it would be great if I can
> just use that.
>
> Another option would be to dynamically enable and disable debugging output
> (or the O3PipeView flag, at least) using an m5op.
>
> Yet another option is a way to enable/disable debugging in the config
> script mid-simulation. This would allow me to exit the simulation using an
> m5op before the instructions, enable debugging in the config script,
> continue, exit using an m5op after the instructions, disable debugging, etc.
>
> Any help is greatly appreciated. Thank you.
>
> Best,
> Hossam
> ___
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[gem5-users] Re: How to suspend FS simulation after certain number of ticks

[Jason Lowe-Power via gem5-users]

Hello,

Unfortunately, we don't have enough time to answer all questions in depth.
You may be able to find more help on either the gem5 slack
 or the gem5 youtube channel
. If you have access to ChatGPT Plus, you
can also use the gem5 GPT .
In fact, we have found that most of the LLMs do a good job answering
gem5-related questions.

In the meantime, here is the output from the gem5 GPT for your question.
This answer has not been checked for correctness, but our experience is
that the answers from the gem5 GPT at a minimum point in the right
direction.

Suspending and resuming a Full System (FS) simulation in gem5, similar to
what you've described for System-call Emulation (SE) mode, is indeed
possible. In FS mode, you can control the simulation flow using the Python
configuration scripts, just as you do in SE mode. However, there are some
nuances to consider when dealing with FS simulations.

For your specific use case, where you want to suspend the simulation after
a certain number of ticks, retrieve the `stats.txt` file, and then resume,
you can follow these steps:

1. **Modify the Python Script**:
   - Open the `/gem5/configs/example/riscv/fs_linux.py` script.
   - In this script, you can insert a loop that calls `m5.simulate()` for a
specified number of ticks. After each `m5.simulate()` call, the script will
regain control, allowing you to perform operations like dumping statistics.
   - Here's an example of how you might modify the script:

 ```python
 import m5
 from m5.objects import *

 # existing configuration code...

 num_ticks = 1e9  # Example: 1 billion ticks
 while m5.curTick() < num_ticks:
 m5.simulate(100)  # simulate for 1 million ticks at a time
 print("Current tick:", m5.curTick())
 m5.stats.dump()  # dump the stats
 ```

   - This script will now run the simulation in chunks of 1 million ticks,
dumping the statistics after each chunk.

2. **Dumping Statistics**:
   - The `m5.stats.dump()` call will update the `stats.txt` file. Make sure
you have set up your statistics correctly in the simulation configuration
so that they are captured and written to the file.

3. **Resuming the Simulation**:
   - The loop will automatically continue the simulation until it reaches
the specified number of ticks. There's no need for explicit "resume"
commands, as `m5.simulate()` both starts and resumes the simulation.

4. **Periodic Checkpoints (Optional)**:
   - If you want to be able to resume the simulation from a particular
point, not just dump statistics, consider using checkpoints. You can create
a checkpoint at each loop iteration or at

specific intervals. Here's how you can add checkpoint creation:

   ```python
   checkpoint_interval = 1e7  # Example: every 10 million ticks
   next_checkpoint = checkpoint_interval

   while m5.curTick() < num_ticks:
   m5.simulate(min(checkpoint_interval, num_ticks - m5.curTick()))
   print("Current tick:", m5.curTick())
   m5.stats.dump()  # dump the stats

   if m5.curTick() >= next_checkpoint:
   m5.checkpoint('checkpoint%d' % (m5.curTick()))
   next_checkpoint += checkpoint_interval
   ```

   - This will create a checkpoint file every 10 million ticks (or at the
specified interval).

5. **Considerations for FS Mode**:
   - In FS mode, especially with complex simulations, be aware that there
might be additional complications, such as device states and interactions
with the simulated OS. Always test your modified script to ensure that it
behaves as expected.

6. **Running the Modified Script**:
   - Once you've modified your `fs_linux.py` script, run it as you normally
would to start the simulation.

By following these steps, you should be able to achieve your goal of
suspending the FS simulation at specific tick intervals, dumping the stats,
and then resuming the simulation. Remember that gem5 is a complex tool, and
small changes in the simulation script can have significant impacts on the
behavior and performance of your simulation, so careful testing and
validation of your modified script are recommended.

On Tue, Jan 16, 2024 at 1:16 AM elio.vinciguerra--- via gem5-users <
gem5-users@gem5.org> wrote:

> Or, at least, I would need to do it in such a way as to have the
> historical progression of the "stats.txt" file during the simulation. So I
> need to suspend the simulation at a certain tick, get the "stats.txt" file,
> resume the simulation, or I need a solution that allows me to dump at a
> certain tick.
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[gem5-users] Re: Can CloudSuite Run on FullSystem Simulation

[Jason Lowe-Power via gem5-users]

Hello,

Note: the output below is from the gem5-GPT. If you have chatGPT Plus you
can access this GPT/bot at https://chat.openai.com/g/g-o3y1y4t8J-gem5-gpt.
I've made some inline comments as well.

Hello!

Regarding your queries about running CloudSuite on gem5 in Full System (FS)
mode with x86 ISA:

### Q1: Simulating CloudSuite in Full System Simulation

Yes, gem5 can simulate the CloudSuite benchmark suite in Full System
simulation mode. Here's what you need to know:

- **Full System (FS) Simulation**: In FS mode, gem5 simulates an entire
machine including the processor, memory system, and I/O devices. This mode
is more comprehensive and suitable for complex benchmarks like CloudSuite.

- **x86 ISA Support**: gem5 supports various ISAs, including x86. Ensure
you have the correct configuration for x86 to accurately simulate the
environment CloudSuite expects.

- **Benchmark Compatibility**: CloudSuite, being a collection of
applications designed to mimic cloud computing workloads, should be
compatible with gem5's FS mode. However, the complexity of these benchmarks
might require specific configurations in gem5, especially regarding the
system's memory, network, and I/O setups.

- **Preparation**: You'll need to prepare disk images with the CloudSuite
software installed. This step is crucial as gem5 simulates from the booting
of an OS. Ensure your disk image has everything needed for CloudSuite to
run.

### Q2: Using Docker in Simulated System in FS Mode

Running Docker inside a simulated system in gem5's FS mode presents
additional complexity:

- **Feasibility**: Technically, it's feasible to run Docker inside gem5's
FS mode as long as the simulated system meets Docker's requirements. This
includes kernel compatibility, necessary kernel modules, and sufficient
system resources.

- **Performance Considerations**: Be aware that running Docker, which adds
additional layers of abstraction and resource requirements, might
significantly slow down the simulation. gem5 models systems at a very
detailed level, and the added complexity of Docker containers could impact
performance. [Editor's note: Running your app in docker shouldn't slow the
simulation down much if at all]

- **Configuration and Limitations**: Ensure that the simulated environment
(including the kernel and hardware configurations) supports Docker. Some
features used by Docker, like certain network configurations or specific
kernel modules, might not be fully supported in gem5's simulated
environment.

- **Debugging and Troubleshooting**: If you encounter issues, utilize
debugging techniques like `DPRINTF` in C++ or `print()` in Python within
gem5 to diagnose problems. Be prepared for a potentially complex debugging
process given the intricacies of both Docker and FS simulation.

 Recommendations:

1. **Start Simple**: Before attempting to run CloudSuite with Docker in FS
mode, start with simpler benchmarks to ensure your gem5 setup is correctly
configured.

2. **Documentation and Community Support**: Utilize gem5 documentation and
community forums for specific guidance on complex setups like yours.

3. **Incremental Approach**: Gradually build your simulation complexity.
Start with basic FS simulation, then introduce CloudSuite, and finally
attempt Docker integration.

Feel free to ask more specific questions if you encounter particular issues
or need guidance on specific aspects of setting up or running your
simulation!

On Thu, Dec 21, 2023 at 3:35 AM Abdelrahman S. Hussein via gem5-users <
gem5-users@gem5.org> wrote:

> Hello,
>
> I am trying to run CloudSuite on FullSystem Simulation using x86 ISA.
>
> Q1) I would like to know if gem5 can simulate such a benchmark suite
> (CloudSuite) in Full System simulation.
>
> Q2) Also, I would like to know if starting/using Docker inside the
> simulated system in the FS mode is supported.
>
>
> Thanks.
>
> --
>
> *Best,Abdelrahman Hussein*
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[gem5-users] Re: Adding 9p support to the riscv-fs platform not working

[Jason Lowe-Power via gem5-users]

Hi Thilo,

My guess is that you need to add a node to the device tree. I would look at
the device tree generated for Arm and see if you can pattern match what you
need to add for RISC-V.

Cheers,
Jason

On Mon, Oct 2, 2023 at 1:12 AM Thilo Voertler via gem5-users <
gem5-users@gem5.org> wrote:

> Hi all,
>
>
>
> I’m trying to add support for 9p to the riscv-fs platform
> (configs/example/gem5_library/riscv-fs.py) similar to the way it was done
> for arm systems using the def attach_9p function
> (configs/common/FSConfig.py).
>
> Summary:
>
>
>
> When trying to mount on the guest I get an error
>
> mount -t 9p -o
> trans=virtio,version=9p2000.L,aname=/gem5rundir/m5out/9p/share gem5 /mnt/9p
>
> mount: mounting gem5 on /mnt/9p failed: No such file or directory
>
>
>
> The reason seems to be that VirtIO9PDiod device is not set up correctly
> under my Platform or Linux so that Linux can find the gem5 tag used for
> sharing.
>
>
>
> Details:
>
> I created my own board, which derives from the RiscvBoard and overwrites
> the function:
>
>
>
> class COSRiscvBoard(RiscvBoard):
>
> @overrides(AbstractSystemBoard)
>
> def _setup_io_devices(self) -> None:
>
> super()._setup_io_devices()
>
> self.add_riscv_9p()
>
> def add_riscv_9p(self):
>
> print(f"Function _setup_board Adding 9p device to platform")
>
> self.viopci = PciVirtIO(pci_bus=0, pci_dev=1, # Hardcoded for the
> platform, Ethernet in RiscV Board is 0
>
>pci_func=0, InterruptPin=1,
>
>InterruptLine=1)
>
> self.viopci.vio = VirtIO9PDiod()
>
> viodir = os.path.realpath(os.path.join(m5.options.outdir, "9p"))
>
> self.viopci.vio.root = os.path.join(viodir, "share")
>
> self.viopci.vio.socketPath = os.path.join(viodir, "socket")
>
> os.makedirs(self.viopci.vio.root, exist_ok=True)
>
> if os.path.exists(self.viopci.vio.socketPath):
>
> os.remove(self.viopci.vio.socketPath)
>
>
>
> self.viopci.host = self.platform.pci_host
>
> self.viopci.pio = self.iobus.mem_side_ports
>
> self.viopci.dma = self.iobus.cpu_side_ports
>
>
>
> I rebuilt the Linux with virtio9p support as described in
> http://old.gem5.org/WA-gem5.html under guest system requirements. During
> boot I see the new attached virtio-pci device (in Addition to the Ethernet
> device of the platfrom).
>
> [1.824575] pci-host-generic 3000.pci: host bridge /soc/pci ranges:
>
> [1.825257] pci-host-generic 3000.pci:   No bus range found for
> /soc/pci, using [bus 00-ff]
>
> [1.826709] pci-host-generic 3000.pci:   IO
> 0x002f00..0x002f00 -> 0x00
>
> [1.827637] pci-host-generic 3000.pci:  MEM
> 0x004000..0x007fff -> 0x00
>
> [1.899228] pci-host-generic 3000.pci: ECAM at [mem
> 0x3000-0x3fff] for [bus 00-ff]
>
> [1.902419] pci-host-generic 3000.pci: PCI host bridge to bus
> :00
>
> [1.902923] pci_bus :00: root bus resource [bus 00-ff]
>
> [1.903470] pci_bus :00: root bus resource [io  0x-0x]
>
> [1.904121] pci_bus :00: root bus resource [mem
> 0x4000-0x7fff] (bus address [0x-0x3fff])
>
> [1.905119] pci :00:00.0: [8086:1075] type 00 class 0x02
>
> [1.906011] pci :00:00.0: reg 0x10: [mem 0x4000-0x4001]
>
> [1.906941] pci :00:00.0: reg 0x30: [mem 0x4000-0x47ff pref]
>
> *[1.911587] pci :00:01.0: [1af4:1000] type 00 class 0xff*
>
> *[1.912321] pci :00:01.0: reg 0x10: [io  0x-0x001f]*
>
> [1.913207] pci :00:01.0: reg 0x30: [mem 0x4000-0x47ff pref]
>
> [1.923427] pci :00:00.0: BAR 0: assigned [mem
> 0x4000-0x4001]
>
> [1.924118] pci :00:00.0: BAR 6: assigned [mem
> 0x4002-0x400207ff pref]
>
> [1.924809] pci :00:01.0: BAR 6: assigned [mem
> 0x40020800-0x40020fff pref]
>
> [1.925486] pci :00:01.0: BAR 0: assigned [io  0x-0x001f]
>
>
>
> However I get an error when loading the virtio-pci driver
>
> [1.939684] virtio-pci :00:01.0: enabling device ( -> 0001)
>
> [1.940263] virtio-pci :00:01.0: virtio_pci: leaving for legacy
> driver
>
> [1.940742] virtio-pci: probe of :00:01.0 failed with error -12
>
> There is also no device that provides the gem5 tag under
> /sys/bus/virtio/drivers/9pnet_virtio/virtio/mount_tag files (
> https://www.kernel.org/doc/Documentation/filesystems/9p.txt)
>
> root@UCanLinux:~ # ls /sys/bus/virtio/drivers/9pnet_virtio/
>
> bindmodule  uevent  unbind
>
> I also checked that diod is in the path and I get message that it was
> started.
>
>
>
> Anyone an idea why it is not working or what I can try to run it again
>
>
>
> Best Regards,
>
>
>
> Thilo
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[gem5-users] Re: Sharing cache lines at memory level

[Jason Lowe-Power via gem5-users]

Hi Arteen,

This is dependent on the Ruby coherence protocol you are using. It sounds
like you're using MESI_Three_Level or MESI_Two_Level in which the LLC is a
single logical cache that is banked between different instances. If you
want something more like "cluster-private" LLC slices, then you'll have to
use a different coherence protocol. CHI may be the most flexible for your
use case.

See the following documentation for more information
https://www.gem5.org/documentation/general_docs/ruby/
https://www.gem5.org/documentation/general_docs/ruby/CHI/

In the sidebar you can find descriptions of each of the other protocols as
well.

Cheers,
Jason

On Sun, Sep 17, 2023 at 11:32 AM Arteen Abrishami via gem5-users <
gem5-users@gem5.org> wrote:

> Hello everyone,
>
> I’m an undergraduate student working on a project where I am to evaluate a
> hardware accelerator my PhD student is working on in a chiplet-based
> system. We are running garnet2.0, and it would be infeasible to port it to
> garnet3.0.
>
> So far, I’ve had success configuring a chiplet configuration in Python and
> I’ve also been able to achieve a 1:n (n chiplets) memory to LLC mapping.
> Unfortunately, we found that there was deadlock under certain workloads.
> This led to the discovery that cache lines were not able to be shared
> across multiple chiplets (from memory -> cache).
>
> To simulate accurately, this is a requirement. I’ve been attempting to
> look into this issue, but I wanted to ask here for insight. I was able to
> find success with creating “cluster-private” LLC chiplets with built-in
> gem5 configurations. It doesn’t seem likely this feature would be provided
> without also allowing cache lines to be shared across the clusters.
>
> Could anyone point me in the right direction?
>
> Thanks,
> Arteen
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[gem5-users] Re: Libthreads for Gem5

[Jason Lowe-Power via gem5-users]

Hi George,

You can use pthreads. There's no need for m5threads anymore. The only
wrinkle is that you have to make sure the cross-compiled dynamic libraries
are in the right place. You can use the "redirect paths" option to map a
path on the host to a different location in the guest (like volumes in
docker).

Cheers,
Jason

On Thu, Sep 14, 2023 at 10:29 AM George Michelogiannakis via gem5-users <
gem5-users@gem5.org> wrote:

> Good morning everyone,
>
> Does anyone know if "m5threads" is available for RISC-V? I'm trying to
> compile an OpenMP code for RISC-V, hopefully avoiding FS.
>
> Thank you
>
>
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[gem5-users] Re: Generate Multiple Trace Files for Multi-Threaded Workloads on FS

[Jason Lowe-Power via gem5-users]

Hi Abdelrahman,

Thank you for your questions on the mailing list. I will try to answer them
as best as I can.

- The trace CPU model was not designed to support multithreaded
applications or multiple cores. It was only tested with single-threaded
benchmarks in both SE and FS mode. Therefore, generating multiple trace
files for different threads/cores may not work as expected or may cause
errors.
- The O3 CPU is capable of traces, but I don't know if/how that will work
with multiple cores. You'll have to dig in and modify the code, most likely.
- Instructions should already have that information (i.e., the StaticInst
class). You can extend the trace formats as well by modifying that code.

Cheers,
Jason

On Fri, Sep 8, 2023 at 5:19 PM Abdelrahman S. Hussein via gem5-users <
gem5-users@gem5.org> wrote:

> Hi,
>
> I am seeking to generate multiple trace files for multi-threaded workloads
> that run in FS (Full-System simulation mode). My plan is to configure the
> simulation to have multiple cores, boot the image, run the workload, and
> record the traces of instructions that run on each core, such that each
> core/thread has its own trace file. My end goal is to have a number of
> trace files, each represent a core or a thread.
>
> Questions:
>
>- Is gem5 capable of generating multiple trace files?
>- I am checking the Trace CPU Model page on gem5
>
>website. It has this statement "The traces have been developed for
>single-threaded benchmarks simulating in both SE and FS mode". Does this
>mean generating multiple trace files for different threads/cores
>is unsupported by gem5?
>- Is the O3 CPU capable of recording such traces? The goal is to
>generate traces using an Out-of-Order superscalar CPU.
>- I may have to add a few more fields to the instruction class, such
>as a boolean variable to check if the instruction is a branch for example.
>which file(s) should I look at?
>
>
> Looking forward to your answer.
>
> Thanks,
> ~Abdelrahman
>
> --
>
> *Best,Abdelrahman Hussein*
>
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[gem5-users] Re: can't run riscv simulation with any CPU model except Atomic

[Jason Lowe-Power via gem5-users]

Hello,

These scripts are tested nightly, so they should be working. How long did
you wait for the terminal output? It can take 15-30 minutes before you see
any output.

Cheers,
Jason

On Wed, Aug 23, 2023 at 5:00 AM oe-fans via gem5-users 
wrote:

> hi, all
>
> I built gem5 v23.0.1.0, I can run configs/example/lupv/run_lupv.py with
> atomic CPU model successful. But when I run it with TIMING model, there is
> nothing appear in m5term.
> I try configs/example/gem5_library/riscv-fs.py or riscvmatched-fs.py,
> neither of them can boot.
>
> What's wrong with my gem5 build? Are there anything I missing?
>
>
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[gem5-users] Re: Memory allocation when using heterogeneous memory controllers

[Jason Lowe-Power via gem5-users]

Hi Jaeyong,

No, there's no way to distinguish the memory types in SE mode. You will
have to modify the memory allocator or use `Process.map` (
https://github.com/gem5/gem5/blob/develop/src/sim/Process.py#L39) to map
specific virtual addresses to physical addresses. If you use `map` you can
then use `mmap` in your guest application to map specific virtual addresses.

In FS mode, you would have to somehow declare different NUMA nodes for the
different memory types (e.g., via the device tree). Then, you could use
`numactrl` or `libnuma` to allocate in specific NUMA nodes.

Cheers,
Jason

On Sun, Aug 20, 2023 at 11:12 PM 이재용 via gem5-users 
wrote:

> As far as I know, gem5 supports heterogeneous memory controllers
> (src/mem/hetero_mem_ctrl.cc), which can have both DRAM and NVM devices
> attached to them.
>
> Let's say I allocate 0-512-MiB of physical addresses for DRAM and
> 512-MiB-1024-MiB for NVM.
>
> Is there a way to distinguish between DRAM and NVM regions when running a
> program in SE-Mode?
> For example, I want to keep my program code and stack in DRAM and dynamic
> memory (allocated via malloc) in NVM. Do I need to modify gem5's memory
> allocator to do this?
>
>
>
> Best,
> Jaeyong Lee
>
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[gem5-users] Re: How to solve "AttributeError: Can't resolve proxy" error when l1icache is replaced with new module

[Jason Lowe-Power via gem5-users]

Hi Shaikhul,

I think that you have somehow unset the `assoc` parameter (or set it to
None) in the cache. Can you provide us the exact script you're running, the
command line that you use to run, the information about the gem5 build
(variant used), the version of gem5 you're using, and any modifications you
have made to gem5?

Thanks,
Jason

On Wed, Aug 16, 2023 at 1:13 PM Khan Shaikhul Hadi via gem5-users <
gem5-users@gem5.org> wrote:

> I have my dedicated controller module that have L1Icache as member
> function (I want to interfere with all incoming and outgoing request and
> response from cache and may modify based on some algorithm) with similler
> parameter and port structure.  In PrivateL1SharedL2CacheHierarchy cache
> hierarchy, I wanted to change the L1Cache with This Controller module. When
> I run my configuration, I encountered this error:
>
> Error in unproxying param 'assoc' of board.cache_hierarchy.l1icaches0.tags
> AttributeError: Can't resolve proxy 'assoc' of type 'Int' from
> 'board.cache_hierarchy.l1icaches0.tags'
>
> Anyone have any idea how I could solve this?
>
> Note: To me it seems like, gem5 trying to create the structure of the
> system where the board trying to find the l1icaches0 directory and trying
> to get tag value from there. I could not find where it was happening. Also,
> I have found some questions where others faced the same type of error ( not
> exactly the same error) and creating a subsystem may resolve it. But I
> could not find any resources on how this subsystem structure works in gem5
> and how to make your own subsystem. Any known resources on that?
>
> Best
> Shaikhul
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[gem5-users] Re: Prefetching during instruction decode

[Jason Lowe-Power via gem5-users]

Hi Pedro,

On quick suggestion: It may make sense to put the prefetcher in the CPU
model code (e.g., during the decode stage in the O3CPU) instead of in the
decode logic of the ISA. After you get the `StaticInst` from the decoder,
you should be able to push prefetch requests into the instruction cache
from there. Hopefully this helps some.

Cheers,
Jason

On Wed, Aug 16, 2023 at 11:21 AM Pedro Corrêa Rigotto via gem5-users <
gem5-users@gem5.org> wrote:

> For my research, I need to do some instruction prefetching during the
> decoding step of specific instructions, which are not memory access
> instructions. I am using Syscall Emulation mode, and I'm studying the x86,
> ARM and RISC-V ISAs, however I will use whichever one works for this
> purpose. I tried looking into the gem5 code to figure out how to do this,
> however I encountered a big roadblock, since most of the code which deals
> with instruction decoding and execution is generated by the compiler. I was
> wondering if anyone knows a way to do this, or knows some reference of
> someone who did prefetching research on gem5. Any help would be much
> appreciated.
>
> Best regards,
> Pedro Corrêa Rigotto
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[gem5-users] Re: RISCV Vector Extension in gem5

[Jason Lowe-Power via gem5-users]

Hello,

No, we don't have any explicit documentation on this. I think that the
fault-only-first are the few instructions that are not implemented.

Cheers,
Jason

On Thu, Aug 3, 2023 at 10:25 PM X BJ  wrote:

> Hello,
>
> Thank you very much, it is exactly what I need !
>
> BTW, is there a instruction list that supported ? Because I notice that
> vector load unit-stride fault-only-first is not supported, I'm wondering if
> there is a list/site/doc about instructions and other stuff in RVV 1.0.
> Thanks again !
>
> Best regards
> xbj
>
> --
> *发件人:* Jason Lowe-Power 
> *发送时间:* 2023年8月3日 22:33
> *收件人:* The gem5 Users mailing list 
> *抄送:* 谢 佰杰 
> *主题:* Re: [gem5-users] RISCV Vector Extension in gem5
>
> Hello,
>
> Initial RVV support was just merged today! See
> https://github.com/gem5/gem5/pull/83
>
> On Thu, Aug 3, 2023 at 12:29 AM 谢 佰杰 via gem5-users 
> wrote:
>
> Hi all,
> I found that both rivosInc and RALC888 used to work on  RISC-V Vector
> Extension in gem5, but both of them seem to be busy with other things,
> leaving  gem5-rvv 1.0 undone.
> I'm wondering what is the status/plan about RISCV-V Vector Extension in
> gem5 ?
>
> Thanks + regards
> xbj
>
>
>
>- [GEM5-1212] Add RISC-V vector support (RVV) version 1.0 - Jira
>(atlassian.net) 
>
>
>- RALC88/gem5: This is an read-only mirror of the gem5 simulator. The
>upstream repository is stored in https://gem5.googlesource.com, code
>reviews should be submitted to https://gem5-review.googlesource.com/. The
>mirrors are synchronized every 15 minutes. (github.com)
>
>
>
>
>
>
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[gem5-users] Re: RISCV Vector Extension in gem5

[Jason Lowe-Power via gem5-users]

Hello,

Initial RVV support was just merged today! See
https://github.com/gem5/gem5/pull/83

On Thu, Aug 3, 2023 at 12:29 AM 谢 佰杰 via gem5-users 
wrote:

> Hi all,
> I found that both rivosInc and RALC888 used to work on  RISC-V Vector
> Extension in gem5, but both of them seem to be busy with other things,
> leaving  gem5-rvv 1.0 undone.
> I'm wondering what is the status/plan about RISCV-V Vector Extension in
> gem5 ?
>
> Thanks + regards
> xbj
>
>
>
>- [GEM5-1212] Add RISC-V vector support (RVV) version 1.0 - Jira
>(atlassian.net) 
>
>
>- RALC88/gem5: This is an read-only mirror of the gem5 simulator. The
>upstream repository is stored in https://gem5.googlesource.com, code
>reviews should be submitted to https://gem5-review.googlesource.com/. The
>mirrors are synchronized every 15 minutes. (github.com)
>
>
>
>
>
>
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[gem5-users] Re: ARM KVM Switch + Restoration

[Jason Lowe-Power via gem5-users]

This should work... can you provide an example script and specific commands
to reproduce the error?

Thanks,
Jason

On Tue, Aug 1, 2023 at 11:24 AM AbdelQader AlKilany via gem5-users <
gem5-users@gem5.org> wrote:

> Hello gem5 users,
>
>
>
> I was wondering if it is possible to start a FS ARM simulation using KVM,
> switch to another CPU type such as Atomic, then restore the CPU
> type(Atomic), and maybe even switch again to O3.
>
>
>
> I have tried to do this using the standard library but I have encountered
> some errors such as:
>
>
>
> build/ALL/sim/serialize.hh:379: fatal: fatal condition !paramInImpl(cp,
> name, param) occurred: Can't unserialize 'board.processor.start.core:_pid'
>
>
>
>
>
> I am using:
>
> platform VExpress_Gem5_V1 (since it’s the only one I found to work with
> KVM)
>
> release ArmRelease.for_kvm()
>
>
>
> I used this for both the checkpointing and restoring simulations (I found
> the release worked for non KVM CPUs when not restoring).
>
> Thank you for any help!
>
> Abdal
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[gem5-users] Re: Unable to boot Linux in FS mode

[Jason Lowe-Power via gem5-users]

Hi Zhenwen,

The actual error is one line higher in the kernel output:
`/lib/x86_64-linux-gnu/libc.so.6: CPU ISA level is lower than required`

I believe we fixed the incompatibility of gem5-x86 with newer kernels in
gem5-v22.1, but it is definitely fixed in gem5-v23.0. I suggest either
updating gem5 or downgrading your kernel and Ubuntu image to something
older.

See https://gem5-review.googlesource.com/c/public/gem5/+/64831 and
https://gem5-review.googlesource.com/c/public/gem5/+/65492

Cheers,
Jason

On Thu, Jul 27, 2023 at 9:40 PM Zhewen Hu via gem5-users <
gem5-users@gem5.org> wrote:

> Hello,
>
> My OS is Ubuntu 22 and I am using gem5 v22.0.0.1, when I boot a Ubuntu 22
> image I got error:
> *Kernel panic - not syncing: Attempted to kill init! exitcode=0x7f00*
>
> Attached are the logs, could anyone help to find the problem?
>
> Thanks in advance.
>
> Best regards,
> Zhenwen Hu
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[gem5-users] Re: Using Traffic Generators with Ruby

[Jason Lowe-Power via gem5-users]

Hi Vishnu,

I do not believe there is any way to direct traffic to a particular message
buffer (e.g, `requestToDir`). Ruby is in some sense a "black box" that only
has port inputs (which are directed to a sequencer) and port output (via
`requestToMemory`).

That said, this is a cool idea! I would encourage you to develop this
support if it's something that you would find useful for your work. In
fact, I think this support could be very useful upstream for testing!

Cheers,
Jason

On Wed, Jul 26, 2023 at 5:52 AM VISHNU RAMADAS via gem5-users <
gem5-users@gem5.org> wrote:

> Hi,
>
> I have a few traces that I recorded at the input port of the directory
> (CHI protocol). I would like to replay these by injecting them directly
> into the Ruby network/directory. Requests in these traces contain
> information about the type of coherent request/snoop response they send and
> I want to inject traffic that includes this. Looking around, I found that
> the Garnet standalone protocol does something similar since all it does is
> inject traffic into the network. Is combining the Garnet standalone
> protocol with the CHI model the only way to send messages to the
> directory? Or are there other approaches that directly inject coherent
> traffic into the directory (without the need for a sequencer or dummy
> cache)?
>
> Thanks,
> Vishnu
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[gem5-users] Re: stopping simulation via ThreadContext::halt()

[Jason Lowe-Power via gem5-users]

Hi David,

I think you want to call the function `exitSimLoopNow` or `exitSimLoop`.
You can call this function from an instruction implementation, (e.g.,
halt), I believe.

See https://github.com/search?q=repo%3Agem5%2Fgem5+exitSimLoop+=code

Cheers,
Jason

On Wed, Jul 26, 2023 at 9:39 AM David Bears via gem5-users <
gem5-users@gem5.org> wrote:

> Hello,
>
> I am trying to create a fault which will stop the simulation. I tried
> calling ThreadContext::halt from within FaultBase::invoke (or rather a
> subclass of FaultBase). This successfully stops simulation of the CPU,
> but then it endlessly simulates memory refreshes.
>
> So how should I properly shut down the simulated system so that the
> gem5.opt process finishes? Do I have to do something in addition to
> calling ThreadContext::halt? Is ThreadContext::halt the wrong tool for
> the job? Or perhaps do I have something else set up wrong?
>
> For context, I implemented most of the NIOS II ISA in gem5, and I am
> running an executable which is designed to run on bare metal. There is a
> particular 'magic' instruction which signals that the executable is
> finished, and I want to stop the simulation sometime after committing
> such an instruction.
>
> Thanks is advance,
> David
>
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[gem5-users] Re: Facing issue while trying to use PARSEC benchmark using Gem5

[Jason Lowe-Power via gem5-users]

Hi Abhinav,

I would suggest using the most recent version of gem5 (v23.0) and use the
gem5-resources version of parsec. See
https://resources.gem5.org/resources/x86-parsec/example?database=gem5-resources=1.0.0
for an example using parsec.

Cheers,
Jason

On Thu, Jul 27, 2023 at 2:14 AM Abhinav Kumar via gem5-users <
gem5-users@gem5.org> wrote:

> Hi everyone,
> I'm trying to run the PARSEC benchmark using gem5. I followed the tutorial
> on the site. But, currently I'm facing one issue, the simerr file  contains
> the following:
> Traceback (most recent call last):
>   File "", line 1, in 
>   File "build/X86/python/m5/main.py", line 457, in main
>   File "configs-parsec-tests/run_parsec.py", line 49, in 
> from system import *
>   File "/home/user-name/parsec-tests/configs-parsec-tests/system.py", line
> 37, in 
> class MySystem(LinuxX86System):
> NameError: name 'LinuxX86System' is not defined"
> I have downloaded the system configuration file from
> https://github.com/darchr/gem5art/tree/master/docs/gem5-configs/configs-parsec-tests/system
>  .
> Can you guys please help me with this?
>
> Regards,
> Abhinav
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[gem5-users] Re: Inquiry about using RiscvTimingSimpleCPU to connect with TLM memory in Gem5

[Jason Lowe-Power via gem5-users]

Hi Zitai,

You should be able to use any CPU model with the TLM interface. You can
write your own configuration file / run script that creates a
TimingSimpleCPU and connects the I/D ports to the TLM interface.

Cheers,
Jason

On Thu, Jul 27, 2023 at 2:44 AM 泰。 via gem5-users 
wrote:

> Hi：
>
> I am a Gem5 user and currently working on system-level modeling and
> simulation using Gem5. I have encountered an issue and would greatly
> appreciate your assistance and advice.
>
> Currently, I am *using tlm_slave.py to connect with TLM memory
> successfully*. However, I noticed that when using tlm_slave.py, it
> requires pairing with the _TrafficGen CPU which is not a conventional CPU
> model; instead, it is a special module used for generating memory system
> stimuli. I would like to use the traditional processor simulator 
> *RiscvTimingSimpleCPU
> instead of the _TrafficGen CPU* to conduct more realistic
> instruction-level simulation.
>
> I am not familiar with the method of connecting RiscvTimingSimpleCPU with
> TLM memory and would like to inquire whether it is possible to achieve this
> configuration and what specific steps need to be taken.
>
> During the configuration process, would I need to modify the interface of
> RiscvTimingSimpleCPU or perform other customizations? Is the workload
> significant?
>
> Thank you very much for your help and guidance!
>
> Best regards,
>
> Zitai
>
>
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[gem5-users] Re: potential error in gem5 simulation?

[Jason Lowe-Power via gem5-users]

There's a lot of information missing in your email, but I'll make some
guesses and try to help.

If you're using x86 and you compiled lbm on your host, then most likely it
is using SSE/AVX/vector instructions that may not be implemented or
implemented incorrectly in gem5. I would expect to see warnings about
unimplemented instructions, but I don't see them in your output.

One possible way to check is to recompile without vector instructions and
try that binary.

Finally, there are a number of warnings about unimplemented syscalls. I
don't think any of those would cause a problem, but using FS mode could
improve the fidelity of your simulation.

Cheers,
Jason

On Sat, Jul 22, 2023 at 5:59 AM An Chow Lai via gem5-users <
gem5-users@gem5.org> wrote:

> To whom it may concern,
>
> I'm new to gem5, I just downloaded gem5 to simulate some spec benchmarks,
> but I encountered something which seems not making sense;
> basically, the outcome of the program simulated by gem5 does not match the
> outcome of the same program run directly on the machine. The results of two
> runs are shown below.
> I hope I can get help/corrections from you guys. Thank you.
>
> Sincerely yours,
> An-Chow
>
> direct run (which is expected and looks correct to me):
> -
> ../../exe/lbm_r_base.mytest-m64 30 reference.dat 0 0 100_100_130_ldc.of
> MAIN_printInfo:
>grid size  : 100 x 100 x 130 = 1.30 * 10^6 Cells
>nTimeSteps : 30
>result file: reference.dat
>action : nothing
>simulation type: lid-driven cavity
>obstacle file  : 100_100_130_ldc.of
>
> LBM_showGridStatistics:
>nObstacleCells:  112539 nAccelCells:   18432 nFluidCells: 1169029
>minRho: 1.00 maxRho: 1.00 Mass: 1.30e+06
>minU  : 0.00 maxU  : 0.00
>
> LBM_showGridStatistics:
>nObstacleCells:  112539 nAccelCells:   18432 nFluidCells: 1169029
>minRho: 0.998947 maxRho: 1.001139 Mass: 1.30e+06
>minU  : 0.00 maxU  : 0.003548
>
> gem5 simulated run (which does not match the direct run above):
> --
> ~/Work/gem5/build/X86/gem5.opt
> ~/Work/gem5/configs/deprecated/example/se.py
> --cmd="../../exe/lbm_r_base.mytest-m64" --option="30  reference.dat 0 0
> 100_100_130_ldc.of" --mem-size=8GB
> gem5 Simulator System.  https://www.gem5.org
> gem5 is copyrighted software; use the --copyright option for details.
>
> gem5 version 23.0.0.1
> gem5 compiled Jul 22 2023 09:57:33
> gem5 started Jul 22 2023 12:50:00
> gem5 executing on Oreo-II, pid 62021
>
> warn: The `get_runtime_isa` function is deprecated. Please migrate away
> from using this function.
> warn: The se.py script is deprecated. It will be removed in future
> releases of  gem5.
> warn: The `get_runtime_isa` function is deprecated. Please migrate away
> from using this function.
> Global frequency set at 1 ticks per second
> warn: No dot file generated. Please install pydot to generate the dot file
> and pdf.
> src/base/statistics.hh:279: warn: One of the stats is a legacy stat.
> Legacy stat is a stat that does not belong to any statistics::Group. Legacy
> stat is deprecated.
> system.remote_gdb: Listening for connections on port 7000
>  REAL SIMULATION 
> src/sim/simulate.cc:194: info: Entering event queue @ 0.  Starting
> simulation...
> src/sim/mem_state.cc:443: info: Increasing stack size by one page.
> src/sim/syscall_emul.cc:74: warn: ignoring syscall set_robust_list(...)
> src/sim/syscall_emul.cc:74: warn: ignoring syscall rseq(...)
> src/sim/syscall_emul.cc:74: warn: ignoring syscall mprotect(...)
> src/sim/syscall_emul.cc:74: warn: ignoring syscall mprotect(...)
> src/sim/syscall_emul.cc:74: warn: ignoring syscall mprotect(...)
> src/sim/syscall_emul.cc:74: warn: ignoring syscall mprotect(...)
> MAIN_printInfo:
>grid size  : 100 x 100 x 130 = 1.30 * 10^6 Cells
>nTimeSteps : 30
>result file: reference.dat
>action : nothing
>simulation type: lid-driven cavity
>obstacle file  : 100_100_130_ldc.of
>
> LBM_showGridStatistics:
>nObstacleCells:  112539 nAccelCells:   18432 nFluidCells: 1169029
>minRho: 0.00 maxRho: 0.00 Mass: 0.00e+00
>minU  : 0.17 maxU  : 0.235702
>
> LBM_showGridStatistics:
>nObstacleCells:  112539 nAccelCells:   18432 nFluidCells: 1169029
>minRho: 0.00 maxRho: 0.00 Mass: 0.00e+00
>minU  : -nan maxU  :  inf
>
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[gem5-users] Re: Question about pulling in the latest version of gem5 with the bootcamp 2022 files.

[Jason Lowe-Power via gem5-users]

Hi Nick,

You should be able to `cd` to the gem5 directory, set up a remote to the
new github location (`git remote add upstream https://github.com/gem5/gem5`)
then checkout stable (`git checkout upstream/stable`). (Note: commands off
the top of my head and may have mistakes.)

That said, be careful as some of the python/stdlib APIs will have changed.
So, some of the examples may need to be updated.

Cheers,
Jason

On Sat, Jul 22, 2023 at 12:55 PM Beser, Nicholas D. via gem5-users <
gem5-users@gem5.org> wrote:

> I am using the bootcamp examples to teach my computer architecture class
> about gem5. I would like to pull in the latest version of gem5 from the
> github location. The command I am using is:
>
>
>
> git clone --recursive
> https://github.com/gem5bootcamp/gem5-bootcamp-env.git
>
>
>
> When I compile gem5, Instead of version 23, I am getting gem5 version
> 22.0.0.0. Is there a recommended way of getting the latest version?
>
>
>
> Nick
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[gem5-users] Re: Meltdown simulation & analysis in FS mode using fs.py

[Jason Lowe-Power via gem5-users]

Hi Robin,

This may be helpful:
http://www.lowepower.com/jason/visualizing-spectre-with-gem5.html

For `warn: instruction 'palignr_Vdq_Wdq_Ib' unimplemented`, this is an AVX
(or SSE) instruction that gem5 doesn't implement.

Overall, I'm not sure if gem5 is vulnerable to meltdown. I think that the
instruction is squashed when the TLB detects a page table fault and it does
not proceed to memory. You can check the O3 code to be sure, though.

Cheers,
Jason

On Thu, Jul 20, 2023 at 2:52 AM reverent.green--- via gem5-users <
gem5-users@gem5.org> wrote:

> Hello everyone,
>
> I am currently working on a meltdown simulation & analysis using the fs.py
> script. Using se.py is not possible, because there is no kernel space
> mapping.
> As for the meltdown test code, I'm using this repo:
> https://github.com/IAIK/meltdown
>
> After playing a bit with the multiple parameter options, my current
> command line call is:
> "./build/X86/gem5.opt configs/example/fs.py --cpu-type=X86O3CPU
> --bp-type=LTAGE --caches --l2cache -n 8 --kernel=fs_stuff/vmlinux-5.4.49
> --disk-image=fs_stuff/x86-ubuntu.img --script=fs_stuff/test"
>
> As you can see here, I am using the X86O3CPU and the branch predictor
> LTAGE (mainly because spectre only works using LTAGE). In theory, this
> should work and the test binary is executed in the simulation, but
> unfortunately the simulation either stops right before the leak or during
> the leakage (not at an exact point everytime, sometimes 1 char, sometimes 4
> chars). The simulation does not abort by itself but looks like it's stuck
> somewhere. I waited for over one hour, but there was no extra char leaked.
> First I thought something is missing to even leak anything here, but after
> some tries do in fact leak some parts of the secret before stopping, there
> should be another problem.
>
> When the meltdown code is executed, the console log is spammed with "warn:
> instruction 'palignr_Vdq_Wdq_Ib' unimplemented"". At first I thought this
> could be the missing piece, but even with these warnings, some parts of the
> secret were leaked in some tries.
> My first goal is to get the complete leak in the result including a normal
> exit of the gem5 simulation.
>
> Does anyone here have an idea or experience at this topic? It would be
> very helpful to discuss possible problems and solutions.
>
> Thank you very much in advance.
>
> Kind regards
> Robin
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[gem5-users] Re: Adding a delay of certain ticks in gem5

[Jason Lowe-Power via gem5-users]

Hi John,

The following may be helpful:

https://gem5bootcamp.github.io/gem5-bootcamp-env/modules/developing%20gem5%20models/events/
https://www.youtube.com/watch?v=OcXA1D4b1RA=3868s

Cheers,
Jason

On Thu, Jul 6, 2023 at 9:53 AM Eliot Moss via gem5-users <
gem5-users@gem5.org> wrote:

> On 7/6/2023 11:12 AM, John Smith via gem5-users wrote:
> > Greetings,
> > If I want to, for example, add a delay of 100 ticks before a line of
> code executes in the function
> > handleTimingReqMiss() in cache.cc, how do I go about doing that?
>
> Generally speaking, you'll have to schedule an event and then do the
> rest of the work in the event handler - something like that.  You can't
> just suspend code in the middle.  You'll probably need to break things
> into two functions to accomplish this.
>
> EM
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[gem5-users] Re: Hi does gem5 Ruby support pthreads lock and unlock

[Jason Lowe-Power via gem5-users]

Full system mode is fully supported for RISC-V. There should not be any
problems with running pthreads on RISC-V.

(Side note: There could be a small bug in the RISC-V atomic instructions...
we're looking into it, but haven't been able to track it down.)

Cheers,
Jason

On Thu, Jun 29, 2023 at 4:05 AM Srikanta Chaitanya via gem5-users <
gem5-users@gem5.org> wrote:

> Thanks for the reply.
>
> On Thu, Jun 29, 2023, 2:11 PM Víctor Soria  wrote:
>
>> Hi Srikanta,
>>
>> In the past, I've been able to run pthreads mutex with ruby using Arm
>> and FS mode. By default, pthreads use syscalls to the OS to sleep or
>> wake up threads. As far as I know, FS does not work with RISCV.
>> Therefore, you could try to select the pthread mutex type to spinlock to
>> avoid having sleeps and wakes up from the OS. Notice that if you set
>> spinlock, you should never instantiate more threads than cores
>> (oversuscription). Otherwise you can have temporal deadlocks and
>> starvation.
>>
>> Regards,
>>
>> Víctor.
>>
>> On 29/6/23 9:03, Srikanta Chaitanya via gem5-users wrote:
>> > Hi ,
>> > I am running pthreads matmul program for riscv in se mode , but with
>> > lock and unlock instructions I am getting read error in Ruby ..
>> > Do i have to compile with mthreads ..
>> >
>> > Thanks
>> > Chaitanya
>> >
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[gem5-users] Re: simulate a multi-core processor with Gem5

[Jason Lowe-Power via gem5-users]

Hello,

You may also find the "Learning gem5" documentation
https://www.gem5.org/documentation/learning_gem5/introduction/ and the
bootcamp videos
https://www.youtube.com/playlist?list=PL_hVbFs_loVSaSDPr1RJXP5RRFWjBMqq3
useful.

Cheers,
Jason

On Tue, Jun 20, 2023 at 10:49 AM Eliot Moss via gem5-users <
gem5-users@gem5.org> wrote:

> On 6/20/2023 10:41 AM, 中国石油大学张天 via gem5-users wrote:
> > How to simulate a multi-core processor with Gem5, such as how to write
> configuration files? For
> > example, in the following form:
>
> You don't write config files.  You write python code that creates
> instances of python classes.  The gem5 system will instantiate the
> corresponding C++ classes and connect everything together as the
> python objects indicate.
>
> Regards - EM
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[gem5-users] Re: About Risc-V custom ISA

[Jason Lowe-Power via gem5-users]

Hello,

I believe you would have to modify your compiler to emit the instruction to
avoid using embedded assembly.

Cheers,
Jason

On Tue, Jun 20, 2023 at 10:36 AM 中国石油大学张天 via gem5-users <
gem5-users@gem5.org> wrote:

> When I have customized a RISC-V instruction, I want to know how to make
> the load program execute it naturally, without using embedded assembly? At
> present, I only know how to use embedded assembly to force this custom
> instruction to run.
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[gem5-users] Re: Writing a script to run multiple simulations at once

[Jason Lowe-Power via gem5-users]

Hi all,

You can use python multiprocessing with gem5. See
https://github.com/gem5/gem5/tree/develop/src/python/gem5/utils/multiprocessing
for details.

So, in theory, you can create scripts such that you can run `./gem5 run.py`
which will run a set of different experiments. You could potentially even
send a subset of stats back to the main `run.py` script for
post-processing, though I haven't tested that, yet.

We are planning to add extensions to the simulator module to make this more
user friendly in gem5 23.1 (the release after gem5 23.0).

Cheers,
Jason

On Wed, Jun 14, 2023 at 11:01 AM Eliot Moss via gem5-users <
gem5-users@gem5.org> wrote:

> On 6/14/2023 11:30 AM, Derek Christ wrote:
> > Hello Eliot Moss,  [one ell please]
>
> > a shared Python file with parameter settings sounds useful.
>
> > What I meant with running gem5 without the gem5 executable was to use the
> > compiled library directly from the Python configuration script.
>
> > From what I have seen, the gem5 executable sets up some internal state
> and
> > then directly calls the embedded Python interpreter to launch the
> > user-provided script.
>
> > But as I see it there is no technical reason why it shouldn't be
> possible to
> > call this setup routine directly from Python. This would reduce the
> > complexity to only one single Python script.
>
> Well, there may remain value to having a standard setup/run script that
> invokes a user supplied script.  It helps keep gem5 per se separate from
> the
> user's setup / configuration - a principle of modularity.
>
> A quick look at main.cc suggests you may be right that this *could* be
> done,
> though I have no idea what those various setup functions do and whether
> any of
> that would be hard to do from python.  What I suppose I am missing is the
> motivation - why such a change would be substantially better.  My
> applications
> tend to be quite complex and I find I need the layers of script, for
> various
> reasons.  Maybe this has more to do with preference to write in python vs
> bash
> scripts vs C++ code.
>
> gem5 is not currently packaged as a library, I don't think, though I
> suppose
> it could be.  Given the amount of existing projects and infrastructure, one
> would need to continue to support the current way of doing things as well.
> This might further complicate the system and its maintenance - one hopes by
> not very much.
>
> HTH - EM
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[gem5-users] Re: [EXT] Re: Question about running the hpca-2023 tutorial

[Jason Lowe-Power via gem5-users]

Hi Nick,

I think you have a typo. It's `gcr.io` as in "google *c*ontainer registry."
I believe you have an "e" instead of a "c" in your URL.

Cheers,
Jason

On Sat, Jun 10, 2023 at 7:52 AM Beser, Nicholas D. via gem5-users <
gem5-users@gem5.org> wrote:

> Bobby,
>
>
>
> I tried your recommendation for docker and got an error:
>
>
>
> $ docker pull ger.io/gem5-test/gem5-tutorial-env:latestError response
> from daemon: Get "https://ger.io/v2/": tls: failed to verify certificate:
> x509: certificate is valid for *.github.com, github.com, not ger.io
>
>
>
> I have confirmed that I have docker installed and running. Is there a
> certificate procedure for get.io?
>
>
>
> Nick
>
>
>
> *From:* Bobby Bruce 
> *Sent:* Friday, June 9, 2023 12:00 PM
> *To:* Beser, Nicholas D. 
> *Cc:* The gem5 Users mailing list ; Ayaz Akram <
> yazak...@ucdavis.edu>; Thiago Rodrigues 
> *Subject:* Re: [gem5-users] [EXT] Re: Question about running the
> hpca-2023 tutorial
>
>
>
> *APL external email warning: *Verify sender bbr...@ucdavis.edu before
> clicking links or attachments
>
>
>
> Hey Nick,
>
>
>
> The GUI work was basically just a prototype. We had ambitions to properly
> incorporate it into the project but we lacked the resources to do so. It
> should really be archived until someone wants to revive it. So I’m not
> surprised it doesn’t work. We don’t recommend using it.
>
>
>
> The RELEASE-NOTES.md file, in the root of the gem5 repository (
> https://gem5.googlesource.com/public/gem5/+/refs/heads/stable/RELEASE-NOTES.md)
> should highlight all the major changes introduced in gem5 released. API
> changes should be noted there.
>
>
>
> A VM should work fine, but if you want to try something more light-weight,
> you could use Docker. The Docker image for the container we ran the
> Bootcamp in, via Codespaces, is gcr.io/gem5-test/gem5-tutorial-env:latest.
> So all you need to do is:
>
>
>
> ```
>
> docker pull gcr.io/gem5-test/gem5-tutorial-env:latest
>
> docker run -u $UID:$GID —volume :/gem5 —rm -it
> gcr.io/gem5-test/gem5-tutorial-env:latest
>
> # from here you’re in the docker container and the gem5 repo is mounted to
> “/gem5”
>
> ```
>
>
>
> (The sources for this docker image is in the Bootcamp repo, here:
> https://github.com/gem5bootcamp/gem5-bootcamp-env/tree/main/docker).
>
>
>
> Kind regards,
>
> Bobby
>
>
>
> --
> Dr. Bobby R. Bruce
> Room 3050,
> Kemper Hall, UC Davis
> Davis,
> CA, 95616
>
> web: https://www.bobbybruce.net
>
>
>
> On Jun 9, 2023, at 6:08 AM, Beser, Nicholas D. 
> wrote:
>
>
>
> Bobby,
>
>
>
> Thank you for your reply. I am making my way through the Bootcamp 2022
> videos and slides. So far everything seems to be working. I had already
> planned to use visual studio code as a student interface for GPU
> programming with the Jetson Orin Nano systems, so I will try to use that
> with the gem5 programming exercises. I have gem5 running on a VM system for
> my initial checkout, and we try to port it to the Jetson for the class.
>
>
>
> Is there a change document that describes the API changes? I will take a
> look at the Obtain resources to make sure my examples are current. I don’t
> recall seeing anything odd yet.
>
>
>
> I will have a challenge getting a week of viewgraphs down to two lectures,
> but my plan is to have a basic tutorial, a lecture on concurrency and
> coherence. and three discussion forums that will allow the student
> experiment and generate studies. This is an on line class, and I am
> integrating gem5 into a basic outline that follows Patterson and Hennessy’s
> book on Computer Architecture (A quantitative approach).
>
>
>
> I think the only part of Gem5 that I could not get working was the GUI
> work. I don’t think it has been updated.
>
>
>
> Nick
>
>
>
> *From:* Bobby Bruce 
> *Sent:* Thursday, June 8, 2023 9:07 PM
> *To:* The gem5 Users mailing list 
> *Cc:* Ayaz Akram ; Thiago Rodrigues <
> thiagor...@gmail.com>; Beser, Nicholas D. 
> *Subject:* Re: [gem5-users] [EXT] Re: Question about running the
> hpca-2023 tutorial
>
>
>
> *APL external email warning: *Verify sender bbr...@ucdavis.edu before
> clicking links or attachments
>
>
>
> Sorry for a very late reply, but for the sake of clarification:
>
>
>
> Yes, I believe you should have cloned the bootcamp 2022 recurisively. I
> think both the issues highlighted in this thread were due to running a
> newer version of gem5 on top of older config scripts and resources which
> used the older API.
>
>
>
> There wasn’t much that went wrong when we used the 2022 Bootcamp repo with
> a class of 50 last year. There may be bugs but I don’t think anything
> should be glaringly broken. I think we did the gem5 Bootcamp with v22.0 of
> gem5, and v22.1 was released in December of last year, so be careful. There
> were quite a few API chances between these released. The “Obtain_resources”
> change was definitely one.
>
>
>
> I’m sorry for all the trouble your having with it. If you run into any
> additional problems please reach out to me 

[gem5-users] Re: [EXT] Re: Question about running the hpca-2023 tutorial

[Jason Lowe-Power via gem5-users]

Hi Nick,

For teaching you may be able to get some inspiration from my class
assignments. Specifically, assignment 5 is about coherence:
https://jlpteaching.github.io/comparch/modules/gem5/assignment5/

All of the code for my assignments can be found here under different
branches for each assignment:
https://github.com/jlpteaching/gem5-assignment-template

Cheers,
Jason

On Fri, Jun 9, 2023 at 9:08 AM Beser, Nicholas D. via gem5-users <
gem5-users@gem5.org> wrote:

> I will take a look at docker. I need to work up getting gem5 running on
> the Jetson Nano. I am not sure if docker works on the Nano.
>
>
>
> Nick
>
>
>
> *From:* Bobby Bruce 
> *Sent:* Friday, June 9, 2023 12:00 PM
> *To:* Beser, Nicholas D. 
> *Cc:* The gem5 Users mailing list ; Ayaz Akram <
> yazak...@ucdavis.edu>; Thiago Rodrigues 
> *Subject:* Re: [gem5-users] [EXT] Re: Question about running the
> hpca-2023 tutorial
>
>
>
> *APL external email warning: *Verify sender bbr...@ucdavis.edu before
> clicking links or attachments
>
>
>
> Hey Nick,
>
>
>
> The GUI work was basically just a prototype. We had ambitions to properly
> incorporate it into the project but we lacked the resources to do so. It
> should really be archived until someone wants to revive it. So I’m not
> surprised it doesn’t work. We don’t recommend using it.
>
>
>
> The RELEASE-NOTES.md file, in the root of the gem5 repository (
> https://gem5.googlesource.com/public/gem5/+/refs/heads/stable/RELEASE-NOTES.md)
> should highlight all the major changes introduced in gem5 released. API
> changes should be noted there.
>
>
>
> A VM should work fine, but if you want to try something more light-weight,
> you could use Docker. The Docker image for the container we ran the
> Bootcamp in, via Codespaces, is gcr.io/gem5-test/gem5-tutorial-env:latest.
> So all you need to do is:
>
>
>
> ```
>
> docker pull gcr.io/gem5-test/gem5-tutorial-env:latest
>
> docker run -u $UID:$GID —volume :/gem5 —rm -it
> gcr.io/gem5-test/gem5-tutorial-env:latest
>
> # from here you’re in the docker container and the gem5 repo is mounted to
> “/gem5”
>
> ```
>
>
>
> (The sources for this docker image is in the Bootcamp repo, here:
> https://github.com/gem5bootcamp/gem5-bootcamp-env/tree/main/docker).
>
>
>
> Kind regards,
>
> Bobby
>
>
>
> --
> Dr. Bobby R. Bruce
> Room 3050,
> Kemper Hall, UC Davis
> Davis,
> CA, 95616
>
> web: https://www.bobbybruce.net
>
>
>
> On Jun 9, 2023, at 6:08 AM, Beser, Nicholas D. 
> wrote:
>
>
>
> Bobby,
>
>
>
> Thank you for your reply. I am making my way through the Bootcamp 2022
> videos and slides. So far everything seems to be working. I had already
> planned to use visual studio code as a student interface for GPU
> programming with the Jetson Orin Nano systems, so I will try to use that
> with the gem5 programming exercises. I have gem5 running on a VM system for
> my initial checkout, and we try to port it to the Jetson for the class.
>
>
>
> Is there a change document that describes the API changes? I will take a
> look at the Obtain resources to make sure my examples are current. I don’t
> recall seeing anything odd yet.
>
>
>
> I will have a challenge getting a week of viewgraphs down to two lectures,
> but my plan is to have a basic tutorial, a lecture on concurrency and
> coherence. and three discussion forums that will allow the student
> experiment and generate studies. This is an on line class, and I am
> integrating gem5 into a basic outline that follows Patterson and Hennessy’s
> book on Computer Architecture (A quantitative approach).
>
>
>
> I think the only part of Gem5 that I could not get working was the GUI
> work. I don’t think it has been updated.
>
>
>
> Nick
>
>
>
> *From:* Bobby Bruce 
> *Sent:* Thursday, June 8, 2023 9:07 PM
> *To:* The gem5 Users mailing list 
> *Cc:* Ayaz Akram ; Thiago Rodrigues <
> thiagor...@gmail.com>; Beser, Nicholas D. 
> *Subject:* Re: [gem5-users] [EXT] Re: Question about running the
> hpca-2023 tutorial
>
>
>
> *APL external email warning: *Verify sender bbr...@ucdavis.edu before
> clicking links or attachments
>
>
>
> Sorry for a very late reply, but for the sake of clarification:
>
>
>
> Yes, I believe you should have cloned the bootcamp 2022 recurisively. I
> think both the issues highlighted in this thread were due to running a
> newer version of gem5 on top of older config scripts and resources which
> used the older API.
>
>
>
> There wasn’t much that went wrong when we used the 2022 Bootcamp repo with
> a class of 50 last year. There may be bugs but I don’t think anything
> should be glaringly broken. I think we did the gem5 Bootcamp with v22.0 of
> gem5, and v22.1 was released in December of last year, so be careful. There
> were quite a few API chances between these released. The “Obtain_resources”
> change was definitely one.
>
>
>
> I’m sorry for all the trouble your having with it. If you run into any
> additional problems please reach out to me directly.
>
>
>
> --
> Dr. Bobby R. Bruce
> Room 3050,
> 

[gem5-users] Re: Multi-level TLB is implemented in performance

[Jason Lowe-Power via gem5-users]

There is not a multi-level TLB model in mainline gem5.

Cheers,
Jason

On Thu, May 18, 2023 at 5:43 AM Arun Kavumkal via gem5-users <
gem5-users@gem5.org> wrote:

> Hi,
> Can anyone please tell me whether a multi-level TLB implementation is
> currently available for x86?
>
> Thanks
> Arun
>
> On Wed, Oct 28, 2020 at 9:01 PM Jason Lowe-Power via gem5-users <
> gem5-users@gem5.org> wrote:
>
>> Yes, this is possible, and I believe it's already implemented for Arm.
>>
>> The best place to start is src/arch//tlb.cc
>>
>> Cheers,
>> Jason
>>
>> On Wed, Oct 28, 2020 at 1:27 AM Laney Laney via gem5-users <
>> gem5-users@gem5.org> wrote:
>>
>>> Hi,all. I would like to know if it is possible to implement multi-level
>>> TLB on gem5 performance by modeling the latency of TLB. If so, which files
>>> or functions should I start with?
>>> ___
>>> gem5-users mailing list -- gem5-users@gem5.org
>>> To unsubscribe send an email to gem5-users-le...@gem5.org
>>> %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
>>>
>> ___
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>> To unsubscribe send an email to gem5-users-le...@gem5.org
>> %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
>
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[gem5-users] Re: Full System + external memory

[Jason Lowe-Power via gem5-users]

Hi Jonathan,

You can put the bridge wherever you would like. For MMIO things, you can
put it after the point of coherence, which is where we usually put the "I/O
crossbar."

You can poke around in configs/examples and util/systemc for some examples.

Cheers,
Jason

On Wed, Apr 26, 2023 at 4:30 PM Jonathan Kang  wrote:

> Thanks!
>
>
>
> Would you have an example of how to instantiate this bridge? Also, I
> imagine this bridge is right after the CPU I and D side ports and before
> any membus that Gem5 has internally right?
>
>
>
> *From: *Jason Lowe-Power 
> *Date: *Wednesday, April 26, 2023 at 4:27 PM
> *To: *The gem5 Users mailing list 
> *Cc: *Jonathan Kang 
> *Subject: *Re: [gem5-users] Full System + external memory
>
> Hi Jonathan, Absolutely! You can set up a "bridge" which will take a
> subset of addresses and route to a different gem5 port. If you can convert
> from the port interface to the AXI, then it should "just work". Note that
> there
>
> Hi Jonathan,
>
>
>
> Absolutely! You can set up a "bridge" which will take a subset of
> addresses and route to a different gem5 port. If you can convert from the
> port interface to the AXI, then it should "just work". Note that there are
> also already bindings to SystemC/TLM in gem5 as well that could serve as
> good examples.
>
>
>
> Cheers,
>
> Jason
>
>
>
> On Wed, Apr 26, 2023 at 11:44 AM Jonathan Kang via gem5-users <
> gem5-users@gem5.org> wrote:
>
> I’m looking to integrate a Gem5 full system model with some of our
> internal IP. The IP and memory (caches) will be memory mapped. So I’d like
> it if the Gem5 full system could handle some parts of the system (file IO,
> system calls) but route requests to certain memory address regions to an
> external port (I’ve taken care of the conversion from Gem5 port to AXI
> SystemC). Is this possible?
>
> ___
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> To unsubscribe send an email to gem5-users-le...@gem5.org
>
>
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[gem5-users] Re: Full System + external memory

[Jason Lowe-Power via gem5-users]

Hi Jonathan,

Absolutely! You can set up a "bridge" which will take a subset of addresses
and route to a different gem5 port. If you can convert from the port
interface to the AXI, then it should "just work". Note that there are also
already bindings to SystemC/TLM in gem5 as well that could serve as good
examples.

Cheers,
Jason

On Wed, Apr 26, 2023 at 11:44 AM Jonathan Kang via gem5-users <
gem5-users@gem5.org> wrote:

> I’m looking to integrate a Gem5 full system model with some of our
> internal IP. The IP and memory (caches) will be memory mapped. So I’d like
> it if the Gem5 full system could handle some parts of the system (file IO,
> system calls) but route requests to certain memory address regions to an
> external port (I’ve taken care of the conversion from Gem5 port to AXI
> SystemC). Is this possible?
> ___
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> To unsubscribe send an email to gem5-users-le...@gem5.org
>
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[gem5-users] Re: I really want these files for old x86 gem5

[Jason Lowe-Power via gem5-users]

Hi Xiang,

I would advise against using such old resources for current research. Using
an OS from a decade ago may not give you results that are accurate for
today's systems.

For "linux-bigswap2.img", this is just an empty disk image that was used as
swap space. You can probably use an empty file and it will probably work.
If that doesn't work, then you could create an empty disk image that is
formatted to be linux swap with qemu.

Cheers,
Jason

On Tue, Apr 25, 2023 at 7:44 AM Xiang Li via gem5-users 
wrote:

> I have to say thanks to Bobby Bruce! I saw you replied my email yesterday.
> But I didn't see it in my email list, so sorry about that.
> https://www.mail-archive.com/gem5-users@gem5.org/msg21437.html  That's
> the mails.
> I'm trying to use gem-gpu,  https://github.com/gem5-gpu, I don't know
> which version of gem5 they used. But I saw the img they used is  
> `linux-bigswap2.img`.
> I try to build my own ubuntu14 img file, but it always says
>
> Run /sbin/init as init process
> random: fast init done
> Mount failed for selinuxfs on /sys/fs/selinux:  No such file or directory
> random: init: uninitialized urandom read (12 bytes read)
> init: plymouth-upstart-bridge main process (638) terminated with status 1
> init: plymouth-upstart-bridge main process ended, respawning
> init: plymouth-upstart-bridge main process (648) terminated with status 1
> init: plymouth-upstart-bridge main process ended, respawning
> init: ureadahead main process (641) terminated with status 5
> init: plymouth-upstart-bridge main process (651) terminated with status 1
> init: plymouth-upstart-bridge main process ended, respawning
> init: plymouth-upstart-bridge main process (654) terminated with status 1
> init: plymouth-upstart-bridge main process ended, respawning
>
> ``
> So I want to try the linux-bigswap2.img,
> * but the links I found in the Internet are invalid.*
>
> http://www.m5sim.org/dist/current/x86/x86-system.tar.bz2*`*
> http://www.m5sim.org/dist/current/x86/config-x86.tar.bz2
> Do you still have those files? Or do you know how to solve these problems? 
> Thanks a lot!
>
> ___
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>
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[gem5-users] Re: Question Regarding L1 Cache Transient States handling Load Hit in Ruby MOESI CMP Directory protocol

[Jason Lowe-Power via gem5-users]

Hello,

This is a great question!

The short answer is I believe that the coherence protocol is correct.
(Though, there could always be unexpected bugs.)

The slightly longer answer: You are probably seeing that the store happens
before the load in "real" time. However, in the processors' view (i.e.,
*logical* time), the load is actually happening before the store. As long
as the processors are correctly implementing their consistency models
(e.g., if they are sequentially consistent then they don't allow any
reorderings between load and store instructions within each thread), then
as long as it *appears* that the load completed before the store, then it's
a correct implementation. To put it another way, if the thread doing the
load cannot tell that the load happened after the store (in real time) then
it is safe.

It's something like the Lamport Clock:
https://en.wikipedia.org/wiki/Lamport_timestamp

We have a saying in English: "If a tree falls in a forest and no one is
there to hear it, does it make a sound?" Similarly, if a thread does a
store to an address, but no other thread can tell what the ordering needs
to be, it's OK to reorder it :).

Cheers,
Jason

On Tue, Mar 21, 2023 at 11:50 PM 章志元 via gem5-users 
wrote:

> Hi all,
>   I've been looking into the default MOESI CMP Directory Protocol, and it
> came to my attention that, regarding SM states in L1 Cache (Transient state
> during a Shared to Exclusive Upgrade due to a store miss), when a load
> arrives from the local core (which hits since the Cache is technically
> still in Shared state), the cache will return the old Shared Datablk as its
> load hit result. Will it cause incoherence issues in memory ordering
> between the core and the memory system, since the CPU commits the store
> first and then commit the load returning the old data, but the memory
> system sees the load hit finish first, and then see the GETX finish?
>   Also I already speculate that such loads will probably not arrive at the
> L1 Cache controller, since it would be blocked or forwarded with newer data
> due to outstanding stores in the lsq or the mandatory queue. I'm just
> wondering if the cache protocol itself is solid in terms of request
> ordering.
>   Thanks in advance!
> Zhang Zhiyuan
> 2023.3.22
> --
> 姓名：章志元
> 手机：17717877306
> 邮箱：zhiyuanzhan...@fudan.edu.cn
>
>
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>
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[gem5-users] Re: Capturing SimPoint and running on ARM CycleModel

[Jason Lowe-Power via gem5-users]

Yes, that's correct.

Cheers,
Jason

On Thu, Mar 9, 2023 at 9:44 AM Jonathan Kang  wrote:

> I think I’d want the opposite: to get ELFies out of Gem5 CheckPoints.
> That’ll allow me to run it on an ARM Cycle Model.
>
>
>
> From the links you sent, it’s still Pin based and the resulting ELFies are
> x86 right? I’d want to do this for ARM.
>
>
>
> *From: *Jason Lowe-Power 
> *Date: *Thursday, March 9, 2023 at 8:15 AM
> *To: *Giacomo Travaglini 
> *Cc: *Jonathan Kang , The gem5 Users mailing list <
> gem5-users@gem5.org>
> *Subject: *Re: [gem5-users] Capturing SimPoint and running on ARM
> CycleModel
>
> Hi Jonathan, We just did a tutorial on how to use ELFies with gem5. See
> https: //looppoint. github. io/hpca2023/ for details. We are able to load
> ELFies and run them in gem5. See https: //github.
> com/gem5-hpca-2023/gem5-tutorial-codespace/blob/master/elfie-refs/elfie. py
>
> ZjQcmQRYFpfptBannerStart
>
> *This Message Is From an Untrusted Sender *
>
> You have not previously corresponded with this sender.
>
> ZjQcmQRYFpfptBannerEnd
>
> Hi Jonathan,
>
>
>
> We just did a tutorial on how to use ELFies with gem5. See
> https://looppoint.github.io/hpca2023/ for details.
>
>
>
> We are able to load ELFies and run them in gem5. See
> https://github.com/gem5-hpca-2023/gem5-tutorial-codespace/blob/master/elfie-refs/elfie.py
> for an example.
>
>
>
> That said, we currently only support ELFies generated by the Sniper
> simulator. If you want details on how to do that, you'll have to check out
> the looppoint documentation above or contact the looppoint/ELFie authors.
>
>
>
> Cheers,
>
> Jason
>
>
>
> On Thu, Mar 9, 2023 at 12:31 AM Giacomo Travaglini <
> giacomo.travagl...@arm.com> wrote:
>
> Hi Jonathan,
>
>
>
> On 08/03/2023 17:47, Jonathan Kang wrote:
>
> Thanks Giacomo,
>
>
>
> A few questions:
>
>
>
>1. Who is Jason? So that I can contact him 
>
>
>
> Jason Lowe-Power, here CCed
>
>
>
>
>
>1. Regarding ELFie, I found these:
>
>
>1.
>   
> https://github.com/UT-LCA/Scalability-Phase-Simpoint-of-SPEC-CPU2017/releases
>   2. https://github.com/intel/pinball2elf
>
>
>
> #2 would seem to be able to generate ELFies from the x86 pinballs that
> were captured. However, I’m unfamiliar with how ELFies work. Do they still
> capture state and thus need to inject processor state prior to simulation?
> In which case the problem still exists that the ARM Cycle Model is
> incompatible….
>
>
>
> The ELFie methodology generates guest bootcode which injects the
> architectural state before the beginning of the SimPoint
>
>
>
> Kind Regards
>
>
>
> Giacomo
>
>
>
>
>
> Thanks,
>
>
>
> Jonathan.
>
>
>
> *From: *Giacomo Travaglini 
> 
> *Date: *Wednesday, March 8, 2023 at 6:26 AM
> *To: *The gem5 Users mailing list 
> 
> *Cc: *Jonathan Kang  
> *Subject: *Re: [gem5-users] Capturing SimPoint and running on ARM
> CycleModel
>
> Hi Jonathan On 08/03/2023 01: 43, Jonathan Kang via gem5-users wrote: Hi
> all, I’m attempting to get SPEC 2k17 to run on our performance model that
> uses an ARM Cycle Model (A55). Obviously it’d take forever to run the whole
> binary so I was wondering
>
> ZjQcmQRYFpfptBannerStart
>
> *This Message Is From an External Sender *
>
> ZjQcmQRYFpfptBannerEnd
>
> Hi Jonathan
>
> On 08/03/2023 01:43, Jonathan Kang via gem5-users wrote:
>
> Hi all,
>
>
>
> I’m attempting to get SPEC 2k17 to run on our performance model that uses
> an ARM Cycle Model (A55). Obviously it’d take forever to run the whole
> binary so I was wondering if anyone has had experience capturing SimPoints
> using Gem5 and then running the resulting reduced binary on a Cycle Model.
> I know you can do it easily on Gem5 simple CPU in SE mode but I need it to
> work with our more accurate model.
>
>
>
> You can easily generate SimPoints with gem5 as you correctly said. The
> problem is the checkpoint incompatibility between gem5 and Cycle Model.
> (restoring the gem5 checkpoint from the CA simulator).
>
> It would be nice if we could generate an ELFie [1] from a gem5 checkpoint.
> As I have recently seen some commits mentioning ELFies you could ask Jason
> and his group if there's something going on...
>
>
>
> Kind Regards
>
>
>
> Giacomo
>
>
>
> [1]: https://dl.acm.org/doi/abs/10.1109/CGO51591.2021.9370340
>
>
>
>
>
> Thanks in advance!
>
>
>
> Jonathan Kang.
>
>
>
> ___
>
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>
> To unsubscribe send an email to gem5-users-le...@gem5.org
>
> IMPORTANT NOTICE: The contents of this email and any attachments are
> confidential and may also be privileged. If you are not the intended
> recipient, please notify the sender immediately and do not disclose the
> contents to any other person, use it for any purpose, or store or copy the
> information in any medium. Thank you.
>
> IMPORTANT NOTICE: The contents of this email and any attachments are
> confidential and may also be privileged. If you are not the intended
> recipient, please notify the 

[gem5-users] Re: Capturing SimPoint and running on ARM CycleModel

[Jason Lowe-Power via gem5-users]

Hi Jonathan,

We just did a tutorial on how to use ELFies with gem5. See
https://looppoint.github.io/hpca2023/ for details.

We are able to load ELFies and run them in gem5. See
https://github.com/gem5-hpca-2023/gem5-tutorial-codespace/blob/master/elfie-refs/elfie.py
for an example.

That said, we currently only support ELFies generated by the Sniper
simulator. If you want details on how to do that, you'll have to check out
the looppoint documentation above or contact the looppoint/ELFie authors.

Cheers,
Jason

On Thu, Mar 9, 2023 at 12:31 AM Giacomo Travaglini <
giacomo.travagl...@arm.com> wrote:

> Hi Jonathan,
>
>
> On 08/03/2023 17:47, Jonathan Kang wrote:
>
> Thanks Giacomo,
>
>
>
> A few questions:
>
>
>
>1. Who is Jason? So that I can contact him 
>
>
> Jason Lowe-Power, here CCed
>
>
>
>
>1. Regarding ELFie, I found these:
>   1.
>   
> https://github.com/UT-LCA/Scalability-Phase-Simpoint-of-SPEC-CPU2017/releases
>   2. https://github.com/intel/pinball2elf
>
>
>
> #2 would seem to be able to generate ELFies from the x86 pinballs that
> were captured. However, I’m unfamiliar with how ELFies work. Do they still
> capture state and thus need to inject processor state prior to simulation?
> In which case the problem still exists that the ARM Cycle Model is
> incompatible….
>
>
> The ELFie methodology generates guest bootcode which injects the
> architectural state before the beginning of the SimPoint
>
>
> Kind Regards
>
>
> Giacomo
>
>
>
>
> Thanks,
>
>
>
> Jonathan.
>
>
>
> *From: *Giacomo Travaglini 
> 
> *Date: *Wednesday, March 8, 2023 at 6:26 AM
> *To: *The gem5 Users mailing list 
> 
> *Cc: *Jonathan Kang  
> *Subject: *Re: [gem5-users] Capturing SimPoint and running on ARM
> CycleModel
>
> Hi Jonathan On 08/03/2023 01: 43, Jonathan Kang via gem5-users wrote: Hi
> all, I’m attempting to get SPEC 2k17 to run on our performance model that
> uses an ARM Cycle Model (A55). Obviously it’d take forever to run the whole
> binary so I was wondering
>
> ZjQcmQRYFpfptBannerStart
>
> *This Message Is From an External Sender *
>
> ZjQcmQRYFpfptBannerEnd
>
> Hi Jonathan
>
> On 08/03/2023 01:43, Jonathan Kang via gem5-users wrote:
>
> Hi all,
>
>
>
> I’m attempting to get SPEC 2k17 to run on our performance model that uses
> an ARM Cycle Model (A55). Obviously it’d take forever to run the whole
> binary so I was wondering if anyone has had experience capturing SimPoints
> using Gem5 and then running the resulting reduced binary on a Cycle Model.
> I know you can do it easily on Gem5 simple CPU in SE mode but I need it to
> work with our more accurate model.
>
>
>
> You can easily generate SimPoints with gem5 as you correctly said. The
> problem is the checkpoint incompatibility between gem5 and Cycle Model.
> (restoring the gem5 checkpoint from the CA simulator).
>
> It would be nice if we could generate an ELFie [1] from a gem5 checkpoint.
> As I have recently seen some commits mentioning ELFies you could ask Jason
> and his group if there's something going on...
>
>
>
> Kind Regards
>
>
>
> Giacomo
>
>
>
> [1]: https://dl.acm.org/doi/abs/10.1109/CGO51591.2021.9370340
>
>
>
>
>
> Thanks in advance!
>
>
>
> Jonathan Kang.
>
>
>
> ___
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>
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>
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> confidential and may also be privileged. If you are not the intended
> recipient, please notify the sender immediately and do not disclose the
> contents to any other person, use it for any purpose, or store or copy the
> information in any medium. Thank you.
>
> IMPORTANT NOTICE: The contents of this email and any attachments are
> confidential and may also be privileged. If you are not the intended
> recipient, please notify the sender immediately and do not disclose the
> contents to any other person, use it for any purpose, or store or copy the
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>
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[gem5-users] Re: Location of gem5 dist

[Jason Lowe-Power via gem5-users]

Hi Rajesh,

You can find all of the links in this json file:
https://gem5.googlesource.com/public/gem5-resources/+/refs/heads/stable/resources.json

It's not very user-friendly, but we're working on it :)

Cheers,
Jason

On Fri, Feb 17, 2023 at 10:15 AM Rajesh Shashi Kumar via gem5-users <
gem5-users@gem5.org> wrote:

> Hi,
>
> Where is http://dist.gem5.org/dist hosted now? I can't seem to find a
> working link to get kernels/datasets(eg Pannotia pagerank) that various
> gem5-resources or documentation point to.
>
> Thanks,
> Rajesh
>
>
>
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[gem5-users] Re: Query about Support for Chiplet Architecture

[Jason Lowe-Power via gem5-users]

Hi Zhengrong,

On Thu, Jan 12, 2023 at 2:40 PM Zhengrong Wang via gem5-users <
gem5-users@gem5.org> wrote:

> Hi All,
>
> Our group has been using gem5 for architecture research for a long time,
> and we currently want to explore some ideas on modern multi-chiplet
> architectures, e.g. AMD's EPYC. We want to understand the tradeoffs of NoC
> design and coherence protocol when there are multiple chiplets connected
> together, each chiplet with its own NoC and caches and the LLC can be
> private or shared between chiplets.
>
> To start with, we want to understand the current support in gem5 for such
> systems. Specifically:
>
> 1. Are there existing scripts/configurations modelling an AMD EPYC like
> systems? We couldn't find them in gem5 or gem5 resources. Any pointers
> would be appreciated.
>

I made a WIP a couple of months ago here:
https://gem5-review.googlesource.com/c/public/gem5/+/65612. Note that this
*doesn't work*. I tried to set things up so that the LLC was a victim
cache, but those options seem to have broken the coherence. I haven't had
time to debug.

This is still using the SimpleNetwork, but adding Garnet should be
possible... once it's working ;).

Feel free to pick this up and build on top of it!


>
> 2. If not and we have to model the system by ourselves, what is a good
> starting point? The most reasonable one to us is the CHI protocol, which
> seems to be flexible enough to model the coherence protocol.
>

Yeah, this is exactly what I was thinking as well!


>
> Thanks in advance for any help you can provide.
>
> Bests,
> Zhengrong
>
> *王 钲 荣*
>
> Zhengrong Wang
> Computer Science Department
> University of California, Los Angeles
> California, USA
> 90024
>
> Work Email: seanyukig...@gmail.com
> Mobile :+1 310-447-4568
>
>
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[gem5-users] Re: DerivO3CPU panic: initiateAcc not defined: ROB fills and locks up

[Jason Lowe-Power via gem5-users]

Hi Eliot,

Unfortunately, I don't have a direct answer for you. However, I want to say
that I appreciate you keeping the mailing list updated with your progress!

Cheers,
Jason

On Fri, Jan 6, 2023 at 10:07 AM Eliot Moss via gem5-users <
gem5-users@gem5.org> wrote:

> On 1/4/2023 11:51 PM, Eliot Moss via gem5-users wrote:
> > So, what I have found is that the bad micro-op is coming from trying to
> execute the micro-ops of an
> > INT3 macro-instruction.  The end of the sequence consists of the
> micro-ops:
> >
> > andi t0, t5, 0x1
> > br 0x803d
> > br 0x80b8
> >
> > followed by a bunch of "panic" micro-ops.  t5 holds an m5 register,
> > where the low bit supposedly indicated whether we are in long mode.
> >
> > The br micro-ops branch into long sequences of micro-ops in the "ROM".
>
> I have found out some more things about this issue.
>
> - The macro instruction is INT_I (my mistake in saying INT3), but the
>micro-ops are almost exactly the same.
>
> - My original though about a load instruction *is* connected somehow.
> Here's
>the big-picture sequence of events:
>
>1) A garden flavor load from memory (mov reg <- offset(reg)) gets stuck
> at
>the head of the ROB.  It was originally deferred because a page table
> walk
>was necessary to resolve the virtual address of the load.
>
>2) The ROB fills (all 192) entries.
>
>3) The panic happens.
>
>
> So I tried adjusting the size of the ROB, just to see what would happen.
> When
> I increased it from 192 to 500, a panic still happened.  I guess that if an
> instruction remains stuck at the head of the ROB forever, the ROB fills and
> then somehow causes the panic.
>
> When I *decreased* the ROB size from 192 to 64, the program worked.
>
> I am inclined to infer that there is (was) a bug in the O3 interactions
> that
> would make the load micro-op fully ready and not stuck at the head of the
> ROB.
>
> What I wonder is whether any similar ROB lock-up behavior has been found
> and
> fixed since 21.0.0.0.  There have been a lot of textual changes, but many
> had
> to do with names and such and did not really change what the code *does*.
> I
> am hoping someone out there can confirm one way or another whether this may
> have been found and fixed already if I can manage to move the rest of my
> changes forward to a newer release.
>
> Best - Eliot
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[gem5-users] Re: Command line options to modify the replacement policy in gem5

[Jason Lowe-Power via gem5-users]

Hi Vipin,

The interface to gem5 isn't the command line, it's a python runscript. In
your python script, you can add parameters (e.g., with optparse) which are
accessible from the command line, but this shouldn't be considered the main
interface to modifying the parameters of gem5 objects. If you want to
change the replacement policy, I suggest writing your own runscript which
has the replacement policy as an option. See
https://www.gem5.org/documentation/learning_gem5/introduction/ for more
information.

Cheers,
Jason

On Thu, Dec 15, 2022 at 9:21 PM VIPIN PATEL via gem5-users <
gem5-users@gem5.org> wrote:

> Dear Gem5-users,
>
> How can we modify the default replacement policy for ruby caches in gem5?
> Is there any command line option for replacement policy similar to
> "--l1d_size", "--l1d_assoc" for changing size and associativity of
> L1D-cahce?
>
> Regards,
> Vipin
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[gem5-users] Re: Panic when running gem5 Full System mode

[Jason Lowe-Power via gem5-users]

I believe the problem is with the kernel binary you are passing in. It
needs to be the path to the binary (not a directory), and it must be the
uncompressed kernel binary, not the compressed binary.

Cheers,
Jason

On Tue, Nov 22, 2022 at 11:06 AM JASPINDER KAUR via gem5-users <
gem5-users@gem5.org> wrote:

> Hi,
> For me compiling attacker code using --static helped on the host machine
> before executing it with Gem5 FS mode worked.
>
> On Wed, Nov 23, 2022 at 12:25 AM William Hua via gem5-users <
> gem5-users@gem5.org> wrote:
>
>> Hello everyone,
>>
>> I am trying to implement a Prime+Probe attack in gem5 full system mode
>> using X86 MESI Two Level architecture. When I run the command line, the
>> process aborts and returns
>> "build/X86_MESI_Two_Level/base/loader/image_file_data.cc:54: panic: panic
>> condition sz != 2 occurred: Couldn't read magic bytes from object file"
>>
>> Can anyone tell me how I can fix this issue?
>>
>> The command line in terminal:
>> ./build/X86_MESI_Two_Level/gem5.opt configs/example/fs.py --disk-image
>> /home/issacnewton/gem5/fsimage/ubuntu-test.img --kernel
>> /home/issacnewton/gem5/linux-6.0.9/
>>
>> The full output:
>> gem5 Simulator System.  https://www.gem5.org
>> gem5 is copyrighted software; use the --copyright option for details.
>>
>> gem5 version 22.0.0.2
>> gem5 compiled Nov 22 2022 12:14:42
>> gem5 started Nov 22 2022 12:45:00
>> gem5 executing on issacnewton-950XDB-951XDB-950XDY, pid 37367
>> command line: ./build/X86_MESI_Two_Level/gem5.opt configs/example/fs.py
>> --disk-image /home/issacnewton/gem5/fsimage/ubuntu-test.img --kernel
>> /home/issacnewton/gem5/linux-6.0.9/
>>
>> Global frequency set at 1 ticks per second
>> warn: system.workload.acpi_description_table_pointer.rsdt adopting orphan
>> SimObject param 'entries'
>> warn: No dot file generated. Please install pydot to generate the dot
>> file and pdf.
>> build/X86_MESI_Two_Level/mem/dram_interface.cc:690: warn: DRAM device
>> capacity (8192 Mbytes) does not match the address range assigned (512
>> Mbytes)
>> build/X86_MESI_Two_Level/base/loader/image_file_data.cc:54: panic: panic
>> condition sz != 2 occurred: Couldn't read magic bytes from object file
>> Memory Usage: 105036 KBytes
>> Program aborted at tick 0
>> --- BEGIN LIBC BACKTRACE ---
>> ./build/X86_MESI_Two_Level/gem5.opt(+0x17c08b0)[0x55f56fbf18b0]
>> ./build/X86_MESI_Two_Level/gem5.opt(+0x17e4d6c)[0x55f56fc15d6c]
>> /lib/x86_64-linux-gnu/libc.so.6(+0x42520)[0x7fe73d52e520]
>> /lib/x86_64-linux-gnu/libc.so.6(pthread_kill+0x12c)[0x7fe73d582a7c]
>> /lib/x86_64-linux-gnu/libc.so.6(raise+0x16)[0x7fe73d52e476]
>> /lib/x86_64-linux-gnu/libc.so.6(abort+0xd3)[0x7fe73d5147f3]
>> ./build/X86_MESI_Two_Level/gem5.opt(+0x431405)[0x55f56e862405]
>> ./build/X86_MESI_Two_Level/gem5.opt(+0x1910cd1)[0x55f56fd41cd1]
>> ./build/X86_MESI_Two_Level/gem5.opt(+0x19119e1)[0x55f56fd429e1]
>> ./build/X86_MESI_Two_Level/gem5.opt(+0x17e8ea5)[0x55f56fc19ea5]
>> ./build/X86_MESI_Two_Level/gem5.opt(+0x449f75)[0x55f56e87af75]
>> ./build/X86_MESI_Two_Level/gem5.opt(+0x99bb75)[0x55f56edccb75]
>> ./build/X86_MESI_Two_Level/gem5.opt(+0x4bbeb6)[0x55f56e8eceb6]
>> ./build/X86_MESI_Two_Level/gem5.opt(+0x4be104)[0x55f56e8ef104]
>> ./build/X86_MESI_Two_Level/gem5.opt(+0x4b09d2)[0x55f56e8e19d2]
>> /lib/x86_64-linux-gnu/libpython3.10.so.1.0(+0x12b6d3)[0x7fe73e0526d3]
>>
>> /lib/x86_64-linux-gnu/libpython3.10.so.1.0(_PyObject_MakeTpCall+0x8c)[0x7fe73e00d1ac]
>> /lib/x86_64-linux-gnu/libpython3.10.so.1.0(+0xe765a)[0x7fe73e00e65a]
>>
>> /lib/x86_64-linux-gnu/libpython3.10.so.1.0(_PyEval_EvalFrameDefault+0x9d78)[0x7fe73dfa29b8]
>> /lib/x86_64-linux-gnu/libpython3.10.so.1.0(+0x1c681f)[0x7fe73e0ed81f]
>> /lib/x86_64-linux-gnu/libpython3.10.so.1.0(+0xe7618)[0x7fe73e00e618]
>>
>> /lib/x86_64-linux-gnu/libpython3.10.so.1.0(_PyEval_EvalFrameDefault+0x9d78)[0x7fe73dfa29b8]
>> /lib/x86_64-linux-gnu/libpython3.10.so.1.0(+0x1c681f)[0x7fe73e0ed81f]
>> /lib/x86_64-linux-gnu/libpython3.10.so.1.0(+0xe7618)[0x7fe73e00e618]
>>
>> /lib/x86_64-linux-gnu/libpython3.10.so.1.0(_PyEval_EvalFrameDefault+0x9d78)[0x7fe73dfa29b8]
>> /lib/x86_64-linux-gnu/libpython3.10.so.1.0(+0x1c681f)[0x7fe73e0ed81f]
>> /lib/x86_64-linux-gnu/libpython3.10.so.1.0(+0xe7618)[0x7fe73e00e618]
>>
>> /lib/x86_64-linux-gnu/libpython3.10.so.1.0(_PyEval_EvalFrameDefault+0x9d78)[0x7fe73dfa29b8]
>> /lib/x86_64-linux-gnu/libpython3.10.so.1.0(+0x1c681f)[0x7fe73e0ed81f]
>> /lib/x86_64-linux-gnu/libpython3.10.so.1.0(+0xe7618)[0x7fe73e00e618]
>>
>> /lib/x86_64-linux-gnu/libpython3.10.so.1.0(_PyEval_EvalFrameDefault+0x9d78)[0x7fe73dfa29b8]
>> /lib/x86_64-linux-gnu/libpython3.10.so.1.0(+0x1c681f)[0x7fe73e0ed81f]
>> --- END LIBC BACKTRACE ---
>> Aborted (core dumped)
>>
>> Thanks,
>> William Hua
>> ___
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>>
>
>
> --
> Jaspinder Kaur
>
> *CONFIDENTIALITY NOTICE: The contents of this 

[gem5-users] Re: SPEC CPU 2017 taking days to simulate

[Jason Lowe-Power via gem5-users]

There are a couple of examples of using simpoints in the configs directory (
https://gem5.googlesource.com/public/gem5/+/refs/heads/develop/configs/example/gem5_library/checkpoints/).
This will be part of the next gem5 release (coming in a couple of weeks).

We would like to start distributing some of the resources for SimPoints.
This should be coming soon.

Cheers,
Jason

On Thu, Nov 10, 2022 at 9:32 AM Jonathan Kang via gem5-users <
gem5-users@gem5.org> wrote:

> Yes, you use SimPoint with the “fast” model (something simple, with no
> timing) so that the tool knows the activity. It then determines windows of
> importance so that you can run only those windows with the cycle accurate
> model.
>
>
>
> *From: *Markus Bichl via gem5-users 
> *Date: *Wednesday, November 9, 2022 at 3:49 PM
> *To: *gem5-users@gem5.org 
> *Cc: *Markus Bichl 
> *Subject: *[gem5-users] Re: SPEC CPU 2017 taking days to simulate
>
> Hi Jason, hi Jonathan, thanks a lot for pointing out SimPoint! I’m
> currently searching for details on how to use SimPoint with gem5. Is it
> right that I need to run the benchmarks at first using a timing CPU to take
> checkpoints at first? I guess
>
> ZjQcmQRYFpfptBannerStart
>
> *This Message Is From an External Sender *
>
> ZjQcmQRYFpfptBannerEnd
>
> Hi Jason, hi Jonathan,
>
>
>
> thanks a lot for pointing out SimPoint! I’m currently searching for
> details on how to use SimPoint with gem5. Is it right that I need to run
> the benchmarks at first using a timing CPU to take checkpoints at first? I
> guess (and hope) there is a way to generate the Simpoints in a faster way.
> Can someone give me a hint, or a maybe some kind of guidance on how to use
> Simpoint with gem5 v22? Thanks a lot!
>
>
>
> BR, Markus
>
>
>
> On 08.11.2022, at 20:10, Jonathan Kang  wrote:
>
>
>
> Something as big as Spec typically wouldn’t be simulated as a whole but
> rather, using SimPoint on a cycle-accurate model.
>
>
>
> *From: *Jason Lowe-Power via gem5-users 
> *Date: *Tuesday, November 8, 2022 at 11:05 AM
> *To: *The gem5 Users mailing list 
> *Cc: *Markus Bichl , Jason Lowe-Power <
> ja...@lowepower.com>
> *Subject: *[gem5-users] Re: SPEC CPU 2017 taking days to simulate
>
> Hi Markus, I would expect gem5 to be at least 10,000-100,000x slower than
> your host. So, if it takes 100 seconds on the host, then I would expect
> between 1,000,000 and 10,000,000 seconds or more! That's 277-2770 hours or
> 10-100 days!! ‍
>
> ZjQcmQRYFpfptBannerStart
>
> *This Message Is From an External Sender*
>
> ZjQcmQRYFpfptBannerEnd
>
> Hi Markus,
>
>
>
> I would expect gem5 to be at least 10,000-100,000x slower than your host.
> So, if it takes 100 seconds on the host, then I would
> expect between 1,000,000 and 10,000,000 seconds or more!
>
>
>
> That's 277-2770 hours or 10-100 days!!
>
>
>
> BTW, I actually think a 10-100,000x slowdown is on the low side if you're
> simulating multiple cores and/or using the out-of-order CPU model.
>
>
>
> In other words, running ref in gem5 to completion is not feasible :).
> There are techniques like SimPoint and other sampling methodologies that
> can help, but they come with tradeoffs, too. We're working to get some
> resources available to easily use sampling methodologies as well.
>
>
>
> Cheers,
>
> Jason
>
>
>
> On Tue, Nov 8, 2022 at 10:19 AM Markus Bichl via gem5-users <
> gem5-users@gem5.org> wrote:
>
> Dear gem5 users,
>
>
>
> I’m currently running SPEC CPU 2017 benchmarks. I was succesful creating a
> SPEC CPU 2017 disk image from this tutorial:
> https://gem5.googlesource.com/public/gem5-resources/+/refs/heads/stable/src/spec-2017/
>
>
> I used this image to start  3 benchmark runs on 3 different systems
> (server instance, desktop computer, and my laptop) 2 days ago. All of the
> systems have Intel Core/Xeon CPUs (but 5-7 years old), and 16 GBytes of
> DDR4 RAM.
>
> At this time, CPU load is 100% on one core for each system, at least 5
> Gbytes of free memory.
>
> I started benchmarks using these commands:
>
> ./build/X86/gem5.fast
> ./configs/example/gem5_library/x86-spec-cpu2017-benchmarks.py --image
> /home//Projects/spec-2017/spec-2017-image/spec-2017 --partition 1
> --benchmark 625.x264_s --size ref
>
> ./build/X86/gem5.fast
> ./configs/example/gem5_library/x86-spec-cpu2017-benchmarks.py --image
> /home//Projects/spec-2017/spec-2017-image/spec-2017 --partition 1
> --benchmark 600.perlbench_s --size ref
>
> ./build/X86/gem5.fast
> ./configs/example/gem5_library/x86-spec-cpu2017-benchmarks.py --image
> /home//Projects/spec-2017/spec-2017-image/spec-2017 --partition 1

[gem5-users] Re: SPEC CPU 2017 taking days to simulate

[Jason Lowe-Power via gem5-users]

Hi Yao,

Long-term, yes, the performance of gem5 is something that is important to
improve! We often hear this as one of our most wanted features. However,
because of the way gem5 was designed and has evolved over time,
*parallelizing* it will be very, very difficult. There are just too many
places where we have pointers between objects to easily apply parallel
discrete event simulation methodology.

Even if we could parallelize gem5, I would not expect more than a 2-4x
performance improvement. I'm not convinced there's that much potential for
independent work (again, because of the underlying design of gem5). So,
even if we could scale gem5 to multiple cores, simulating all of a SPEC CPU
ref run would be unlikely in a reasonable amount of time. Not to mention,
when the next version of SPEC CPU comes out it will be even longer!

Cheers,
Jason

On Tue, Nov 8, 2022 at 5:53 PM yaogang  wrote:

> Hi Jason,
>
>
>
>Is there any roadmap (near future not long term) to take gem5 to multi
> thread accerleration?
>
>
>
> Regards
>
> Yao
>
>
>
> *发件人:* Jason Lowe-Power via gem5-users [mailto:gem5-users@gem5.org]
> *发送时间:* 2022年11月9日 3:02
> *收件人:* The gem5 Users mailing list 
> *抄送:* Markus Bichl ; Jason Lowe-Power <
> ja...@lowepower.com>
> *主题:* [gem5-users] Re: SPEC CPU 2017 taking days to simulate
>
>
>
> Hi Markus,
>
>
>
> I would expect gem5 to be at least 10,000-100,000x slower than your host.
> So, if it takes 100 seconds on the host, then I would
> expect between 1,000,000 and 10,000,000 seconds or more!
>
>
>
> That's 277-2770 hours or 10-100 days!!
>
>
>
> BTW, I actually think a 10-100,000x slowdown is on the low side if you're
> simulating multiple cores and/or using the out-of-order CPU model.
>
>
>
> In other words, running ref in gem5 to completion is not feasible :).
> There are techniques like SimPoint and other sampling methodologies that
> can help, but they come with tradeoffs, too. We're working to get some
> resources available to easily use sampling methodologies as well.
>
>
>
> Cheers,
>
> Jason
>
>
>
> On Tue, Nov 8, 2022 at 10:19 AM Markus Bichl via gem5-users <
> gem5-users@gem5.org> wrote:
>
> Dear gem5 users,
>
>
>
> I’m currently running SPEC CPU 2017 benchmarks. I was succesful creating a
> SPEC CPU 2017 disk image from this tutorial:
> https://gem5.googlesource.com/public/gem5-resources/+/refs/heads/stable/src/spec-2017/
>
>
> I used this image to start  3 benchmark runs on 3 different systems
> (server instance, desktop computer, and my laptop) 2 days ago. All of the
> systems have Intel Core/Xeon CPUs (but 5-7 years old), and 16 GBytes of
> DDR4 RAM.
>
> At this time, CPU load is 100% on one core for each system, at least 5
> Gbytes of free memory.
>
> I started benchmarks using these commands:
>
> ./build/X86/gem5.fast
> ./configs/example/gem5_library/x86-spec-cpu2017-benchmarks.py --image
> /home//Projects/spec-2017/spec-2017-image/spec-2017 --partition 1
> --benchmark 625.x264_s --size ref
>
> ./build/X86/gem5.fast
> ./configs/example/gem5_library/x86-spec-cpu2017-benchmarks.py --image
> /home//Projects/spec-2017/spec-2017-image/spec-2017 --partition 1
> --benchmark 600.perlbench_s --size ref
>
> ./build/X86/gem5.fast
> ./configs/example/gem5_library/x86-spec-cpu2017-benchmarks.py --image
> /home//Projects/spec-2017/spec-2017-image/spec-2017 --partition 1
> --benchmark 502.gcc_r --size test
>
>
>
> I wanted to have the results as fast as possible, so I used gem5.fast, and
> also tried the gcc benchmark with the test workload.
>
> As  I do not see any progess on the benchmarks yet, I feel there is
> something wrong. Is this a normal simulation time for SPEC CPU 2017
> benchmarks? Is it possible to track the progress of the simulations, even
> with "m5.disableAllListeners()” enabled in the system configuration?
>
> A run of 600.perlbench_s using the ref workload directly on the host
> system (server instance) took 181 seconds.
>
> Thanks a lot for your help!
>
>
>
> BR,
>
> Markus Bichl
>
>
>
> Student, Technische Universität Wien
>
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[gem5-users] Re: SPEC CPU 2017 taking days to simulate

[Jason Lowe-Power via gem5-users]

Hi Markus,

I would expect gem5 to be at least 10,000-100,000x slower than your host.
So, if it takes 100 seconds on the host, then I would
expect between 1,000,000 and 10,000,000 seconds or more!

That's 277-2770 hours or 10-100 days!!

BTW, I actually think a 10-100,000x slowdown is on the low side if you're
simulating multiple cores and/or using the out-of-order CPU model.

In other words, running ref in gem5 to completion is not feasible :). There
are techniques like SimPoint and other sampling methodologies that can
help, but they come with tradeoffs, too. We're working to get some
resources available to easily use sampling methodologies as well.

Cheers,
Jason

On Tue, Nov 8, 2022 at 10:19 AM Markus Bichl via gem5-users <
gem5-users@gem5.org> wrote:

> Dear gem5 users,
>
> I’m currently running SPEC CPU 2017 benchmarks. I was succesful creating a
> SPEC CPU 2017 disk image from this tutorial:
> https://gem5.googlesource.com/public/gem5-resources/+/refs/heads/stable/src/spec-2017/
>
> I used this image to start  3 benchmark runs on 3 different systems
> (server instance, desktop computer, and my laptop) 2 days ago. All of the
> systems have Intel Core/Xeon CPUs (but 5-7 years old), and 16 GBytes of
> DDR4 RAM.
> At this time, CPU load is 100% on one core for each system, at least 5
> Gbytes of free memory.
> I started benchmarks using these commands:
> ./build/X86/gem5.fast
> ./configs/example/gem5_library/x86-spec-cpu2017-benchmarks.py --image
> /home//Projects/spec-2017/spec-2017-image/spec-2017 --partition 1
> --benchmark 625.x264_s --size ref
> ./build/X86/gem5.fast
> ./configs/example/gem5_library/x86-spec-cpu2017-benchmarks.py --image
> /home//Projects/spec-2017/spec-2017-image/spec-2017 --partition 1
> --benchmark 600.perlbench_s --size ref
> ./build/X86/gem5.fast
> ./configs/example/gem5_library/x86-spec-cpu2017-benchmarks.py --image
> /home//Projects/spec-2017/spec-2017-image/spec-2017 --partition 1
> --benchmark 502.gcc_r --size test
>
> I wanted to have the results as fast as possible, so I used gem5.fast, and
> also tried the gcc benchmark with the test workload.
> As  I do not see any progess on the benchmarks yet, I feel there is
> something wrong. Is this a normal simulation time for SPEC CPU 2017
> benchmarks? Is it possible to track the progress of the simulations, even
> with "m5.disableAllListeners()” enabled in the system configuration?
> A run of 600.perlbench_s using the ref workload directly on the host
> system (server instance) took 181 seconds.
> Thanks a lot for your help!
>
> BR,
> Markus Bichl
>
> Student, Technische Universität Wien
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[gem5-users] Re: Low memory bandwidth achieved with STREAM benchmark

[Jason Lowe-Power via gem5-users]

Majid,

These are all great suggestions! Do you have a configuration file that you
would be willing to share? It would be a huge benefit to the community if
we had some better default configurations in the "examples" for gem5
configuration files.

We're also trying to use the new standard library for these kinds of "good"
configurations. We can work with you to create a "prebuilt board" with all
of these parameters and even run nightly/weekly tests to make sure there
are no performance regressions.

Thanks!
Jason

On Fri, Apr 22, 2022 at 7:52 PM Majid Jalili  wrote:

> I think it is hard to get to a real machine level in terms of BW. But By
> looking at your stats, I found the lsqFullEvents is high.
> You can go after the CPU to make it more aggressive, increasing Load/Store
> queue size, and ROB depth are the minimal changes you can make. I
> usually do at least ROB sizes of 256 or 320. With that, you may set the LSQ
> size to at least 1/4  of ROB size.
> For MSHRs, your numbers are good now, 10 is too little even in intel
> machines, I found recently they increased that to 16-20.
> The other thing you can try to st is the cache latencies, make sure that
> they are reasonable.
> For prefetcher, you can use IMPPrefetcher in addition to DCPT, it has a
> pretty aggressive stream prefetcher inside.
> Also, DRAM memory mapping is important, I do not remember what is the
> default for the the mem type you are using
>
> Majid
>
>
>
> On Sat, Apr 16, 2022 at 2:12 AM 王子聪  wrote:
>
>> Hi Majid,
>>
>> Thanks for your suggestion! I check the default number of MSHRs (in
>> configs/common/Caches.py), and found the default #MSHR of L1/L2 are 4 and
>> 20 respectively.
>>
>> According to the PACT’18 paper "Cimple: Instruction and Memory Level
>> Parallelism: A DSL for Uncovering ILP and MLP”,  it says that "Modern
>> processors typically have 6–10 L1 cache MSHRs”, and "Intel’s Haswell
>> microarchitecture uses 10 L1 MSHRs (Line Fill Buffers) for
>> handling outstanding L1 misses”. So I change to L1 #MSHRs to 16 and L2
>> #MSHRs to 32 (which I think it’s enough to handling outstanding misses),
>> and then change the L1/L2 prefetcher type to DCPT. Then I got the STREAM
>> output as shown in below:
>>
>> ./build/X86/gem5.opt configs/example/se.py --cpu-type=O3CPU --caches
>> --l1d_size=256kB --l1i_size=256kB
>> --param="system.cpu[0].dcache.mshrs=16;system.cpu[0].icache.mshrs=16;system.l2.mshrs=32"
>> --l2cache --l2_size=8MB --l1i-hwp-type=DCPTPrefetcher
>> --l1d-hwp-type=DCPTPrefetcher --l2-hwp-type=DCPTPrefetcher
>> --mem-type=DDR3_1600_8x8 -c ../stream/stream
>> -
>> FunctionBest Rate MB/s  Avg time Min time Max time
>> Copy:3479.8 0.004598 0.004598 0.004598
>> Scale:   3554.0 0.004502 0.004502 0.004502
>> Add: 4595.0 0.005223 0.005223 0.005223
>> Triad:   4705.9 0.005100 0.005100 0.005100
>> -
>>
>> The busutil of DRAM also improved:
>> -
>> system.mem_ctrls.dram.bytesRead  239947840  # Total bytes read
>> (Byte)
>> system.mem_ctrls.dram.bytesWritten   121160640  # Total bytes written
>> (Byte)
>> system.mem_ctrls.dram.avgRdBW  1611.266685  # Average DRAM read
>> bandwidth in MiBytes/s ((Byte/Second))
>> system.mem_ctrls.dram.avgWrBW   813.602251  # Average DRAM write
>> bandwidth in MiBytes/s ((Byte/Second))
>> system.mem_ctrls.dram.peakBW  12800.00  # Theoretical peak
>> bandwidth in MiByte/s ((Byte/Second))
>> system.mem_ctrls.dram.busUtil18.94  # Data bus
>> utilization in percentage (Ratio)
>> system.mem_ctrls.dram.busUtilRead12.59  # Data bus
>> utilization in percentage for reads (Ratio)
>> system.mem_ctrls.dram.busUtilWrite6.36  # Data bus
>> utilization in percentage for writes (Ratio)
>> system.mem_ctrls.dram.pageHitRate89.16  # Row buffer hit
>> rate, read and write combined (Ratio)
>> -
>>
>> It’s indeed improving the achieved bandwidth, but still a little far away
>> from the peak bandwidth of DDR3_1600 (12800 MiB/s). stats.txt is uploaded
>> for reference (
>> https://gist.github.com/wzc314/cf29275f853ee0b2fcd865f9b492c355)
>>
>> Any idea is appreciated!
>> Thank you in advance!
>>
>> Bests,
>> Zicong
>>
>>
>>
>> 2022年4月16日 00:08，Majid Jalili  写道：
>>
>> Hi,
>> Make sure your system has enough MSHRs, out of the box, L1, and L2 are
>> set to have a few MSHR entries.
>> Also, stride prefetcher is not the best, you may try something better:
>> DCPT gives me better numbers.
>>
>> On Fri, Apr 15, 2022 at 4:57 AM Zicong Wang via gem5-users <
>> gem5-users@gem5.org> wrote:
>> Hi Jason,
>>
>>   We are testing the memory bandwidth program STREAM ​(
>> https://www.cs.virginia.edu/stream/)​, 

[gem5-users] Re: Adding PioDevice leads to TypeError: No constructor defined

[Jason Lowe-Power via gem5-users]

I just pushed a change that will make this error message better.

"fatal: Cannot instantiate an abstract SimObject (system.dev)" is what the
error now says :).

See https://gem5-review.googlesource.com/c/public/gem5/+/59049

Cheers,
Jason

On Fri, Apr 22, 2022 at 8:57 AM Jason Lowe-Power 
wrote:

> Hello,
>
> I believe the problem is that gem5 tries to do too much automatically for
> you! gem5 automatically creates a lot of the constructor/destructor codes.
> Given all of this hidden/automatic code generation, it's difficult to know
> exactly what's going wrong (for both you and for us).
>
> That said, I think the problem is that `PioDevice` is an abstract
> SimObject, not a concrete SimObject. This may work if you instead use the
> `DmaDevice`.
>
> Cheers,
> Jason
>
> On Thu, Apr 21, 2022 at 1:58 PM Raghu Shankar via gem5-users <
> gem5-users@gem5.org> wrote:
>
>> By adding a PioDevice() to my version of two_level.py configuration
>> script, I get this error
>>
>>
>>
>> TypeError: _m5.param_PioDevice.PioDeviceParams: No constructor defined!
>>
>> And checking io_device.cc the constructor looks empty
>>
>>
>>
>> Any help please? Thanks
>>
>>
>>
>> *Details:*
>>
>>
>>
>> Traceback (most recent call last):
>>   File "", line 1, in 
>>   File "build/X86/python/m5/main.py", line 455, in main
>> exec(filecode, scope)
>>
>>
>>   File "/home/raghu/gem5/configs/learning_gem5/part1/two_level.py", line
>> 187, in 
>> m5.instantiate()
>>   File "build/X86/python/m5/simulate.py", line 116, in instantiate
>>
>>   File "build/X86/python/m5/SimObject.py", line 1790, in createCCObject
>> self.getCCParams()
>>   File "build/X86/python/m5/SimObject.py", line 1720, in getCCParams
>> cc_params = cc_params_struct()
>>
>> TypeError: _m5.param_PioDevice.PioDeviceParams: No constructor defined!
>>
>>
>>
>>
>>
>> *Io_device.cc*
>>
>> include "dev/io_device.hh"
>>
>> #include "base/trace.hh"
>> #include "debug/AddrRanges.hh"
>> #include "sim/system.hh"
>>
>> namespace gem5
>> {
>>
>> PioDevice::PioDevice(const Params )
>> : ClockedObject(p), sys(p.system), pioPort(this)
>> {}
>>
>> PioDevice::~PioDevice()
>> {
>> }
>>
>>
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[gem5-users] Re: Adding PioDevice leads to TypeError: No constructor defined

[Jason Lowe-Power via gem5-users]

Hello,

I believe the problem is that gem5 tries to do too much automatically for
you! gem5 automatically creates a lot of the constructor/destructor codes.
Given all of this hidden/automatic code generation, it's difficult to know
exactly what's going wrong (for both you and for us).

That said, I think the problem is that `PioDevice` is an abstract
SimObject, not a concrete SimObject. This may work if you instead use the
`DmaDevice`.

Cheers,
Jason

On Thu, Apr 21, 2022 at 1:58 PM Raghu Shankar via gem5-users <
gem5-users@gem5.org> wrote:

> By adding a PioDevice() to my version of two_level.py configuration
> script, I get this error
>
>
>
> TypeError: _m5.param_PioDevice.PioDeviceParams: No constructor defined!
>
> And checking io_device.cc the constructor looks empty
>
>
>
> Any help please? Thanks
>
>
>
> *Details:*
>
>
>
> Traceback (most recent call last):
>   File "", line 1, in 
>   File "build/X86/python/m5/main.py", line 455, in main
> exec(filecode, scope)
>
>
>   File "/home/raghu/gem5/configs/learning_gem5/part1/two_level.py", line
> 187, in 
> m5.instantiate()
>   File "build/X86/python/m5/simulate.py", line 116, in instantiate
>
>   File "build/X86/python/m5/SimObject.py", line 1790, in createCCObject
> self.getCCParams()
>   File "build/X86/python/m5/SimObject.py", line 1720, in getCCParams
> cc_params = cc_params_struct()
>
> TypeError: _m5.param_PioDevice.PioDeviceParams: No constructor defined!
>
>
>
>
>
> *Io_device.cc*
>
> include "dev/io_device.hh"
>
> #include "base/trace.hh"
> #include "debug/AddrRanges.hh"
> #include "sim/system.hh"
>
> namespace gem5
> {
>
> PioDevice::PioDevice(const Params )
> : ClockedObject(p), sys(p.system), pioPort(this)
> {}
>
> PioDevice::~PioDevice()
> {
> }
>
>
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[gem5-users] Re: Integrating MCPAT with gem5

[Jason Lowe-Power via gem5-users]

Hi Vipin,

McPAT is not the same kind of simulator as SST, DRAMSim, and SystemC, so it
cannot be integrated in the same way. It's not really a timing simulator at
all. You can use gem5's statistics output as the "activity rate" which is
one of the inputs to McPAT. However, the other inputs (e.g., the relative
energy cost of different activations) is not something that you can get
from gem5.

There have been a few scripts created to convert gem5 stats to McPAT files
in the past. However, I do not think that there are any that work with the
current version (21.2) of gem5. You may be able to find one and update it
for your needs.

Cheers,
Jason

On Thu, Apr 21, 2022 at 3:49 AM VIPIN PATEL via gem5-users <
gem5-users@gem5.org> wrote:

> Hi All,
>
> Simulators like SST, DRAMSim, SystemC can be integrated with gem5.
> Can we integrate the McPAT with gem5 ? Are there any pointers available
> for doing this?
>
> Thanks in advance.
>
> Regards,
> Vipin Patel
> Ph.D. CSE
> IIT Kanpur
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[gem5-users] Re: How to set the Cache replacement policy

[Jason Lowe-Power via gem5-users]

Hi Ankit,

I would suggest modifying your python runscript instead of using command
line parameters.
https://www.gem5.org/documentation/learning_gem5/introduction/ may help
explain how to set parameters on SimObjects.

Cheers,
Jason

On Wed, Apr 6, 2022 at 2:48 PM Ankit Berde  wrote:

> Hi Gem5 Team,
>
> Could you please guide us on how to set the replacement policy to a
> certain value. We are trying to simulate Cache Replacement policies, and
> whichever argument we provide as "--repl_policy==FIFORP()", it by default
> calls LRURP.
>
> Could you please help us on this
>
> Thanks,
> Ankit
>
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[gem5-users] Re: How does an out of order pipeline implementation handle instructions (cmp, adds,cmn etc.) which update N,Z,C,V?

[Jason Lowe-Power via gem5-users]

Hi Tom,

On Tue, Mar 29, 2022 at 9:39 AM tomjosekallooran--- via gem5-users <
gem5-users@gem5.org> wrote:

> Hi ,
> This may sound very generic, but i want to try some experiments with the
> out of order implementation. I came across few scenarios, which are listed
> below (any input would be helpful):
> 1. lets consider the following set of instructions (an example which was
> made up):
> Address instr  Operands
> 4357136cmp {"x1", "#16"}
> 4357140cmp {"x2", "#16"}
> 4357144bhi   {"4387895"}
>
> So if we have two execution units which can execute integer instructions,
> then both "cmp" instruction (4357136 and 4357140) could be issued to the
> execution unit. But an "cmp" instruction will update N,Z,C,V flags which
> inturn are used for evaluating conditional flags (eq_ne, hi_ls, cs_cc etc).
> So, can these two cmp be issued to execution units in the same cycle? If
> so, are the N,Z,C,V for each cmp only updated after inorder commit? How is
> it handled ? (do we use temp registers for holding each N,Z,C,V value?)
>

If I remember correctly, we rename all of the flag registers on each
instruction, and we increase the number of physical registers such that
this renaming is not a bottleneck. In a real processor, I don't think it
would work this way, but it should be OK performance-wise.


>
> 2. In speculative execution, how are stores implemented? do we place them
> into a store buffer and write it to memory once its commited?
>

I think that's correct, at least for x86. In Arm/RISC-V the stores could go
out of order to memory as well. You can check the code in the lsq_unit
files in src/cpu/o3 and poke around for "tso" to see exactly how it's
handled. Someone else may remember better than I do :).

Cheers,
Jason


>
> Any input would be appreciated.
> Regards,
> Tom
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[gem5-users] Re: Problem with SimObject

[Jason Lowe-Power via gem5-users]

Hi Artyom,

You're absolutely right that the tutorial needs to be updated! The
website is also open source and managed via a git repo:
https://gem5.googlesource.com/public/gem5-website/. Updating this would be
a good way to get started contributing to gem5 :).

By the way, for the namespace, you can also wrap the file in the following
so you don't have to explicitly use namespaces everywhere:

```
namespace gem5
{

}
```

Cheers,
Jason

On Sat, Mar 26, 2022 at 10:57 PM Artyom Liu via gem5-users <
gem5-users@gem5.org> wrote:

> Hi,
>
> The problem is solved by literally adding a new parameter `sim_objects`.
>
>  > SimObject("HelloObject.py", sim_objects = ["HelloObject"])
>
> But I find yet another problem with the tutorial: the code that use
> classes from gem5 is missing namespace declaration. For example, the
> class `SimObject` is under namespace `gem5`, but the tutorial is using
> it directly. It makes the compiler unable to find the class.
>
> ```
> #ifndef __LEARNING_GEM5_HELLO_OBJECT_HH__
> #define __LEARNING_GEM5_HELLO_OBJECT_HH__
>
> #include "params/HelloObject.hh"
> #include "sim/sim_object.hh"
>
> class HelloObject : public SimObject
> {
>public:
>  HelloObject(const HelloObjectParams );
> };
>
> #endif // __LEARNING_GEM5_HELLO_OBJECT_HH__
> ```
>
> For the compiler to work, we should use `gem5::SimObject` instead. And
> `gem5::HelloObjectParams` for the same reason.
>
> None of the problems are mentioned in the tutorial. I wonder if it is
> necessary to *update* the tutorial?
>
> Artyom
> artyom...@hust.edu.cn
>
> On 3/27/22 10:05, Artyom Liu wrote:
> > Hi,
> >
> > I'm new to gem5 and just start learning by following the tutorial on
> > gem5.org. However, there's a problem when I try to create my custom
> > object[1].
> >
> > [1]: https://www.gem5.org/documentation/learning_gem5/part2/helloobject/
> >
> > I follow exactly the guide, but I fail to re-compile with scons. The
> > error message as below.
> >
> >  > Error: SimObject(HelloObject.py...) must list c++ sim_objects or
> > enums > (set either to [] if there are none).
> >
> > My gem5 version is Version 21.2.1.0, and I noticed that there's an *API
> > change* about SimObject declaration in Version 21.2.0.0, requiring that
> > sim_object parameter of SimObject declaration "should list all SimObject
> > classes which have a type attribute defined".
> >
> > It matches the error message. So I wonder how could I change my
> > SConscript to fit this change? My current SConscript is from the
> tutorial.
> >
> > ```
> > Import("*")
> >
> > SimObject("HelloObject.py")
> > Source("hello_object.py")
> > ```
> >
> > Artyom
> > artyom...@hust.edu.cn
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[gem5-users] Re: gem5 and non volatile memory

[Jason Lowe-Power via gem5-users]

Hello Taiyu,

I would suggest reaching out to the VANS authors. Since this project is not
part of the gem5 repository, we have little control over the integration.

Cheers,
Jason

On Thu, Mar 24, 2022 at 8:49 PM Taiyu Zhou via gem5-users <
gem5-users@gem5.org> wrote:

> Could you give me some advise to integrate VANS with new version gem5?
> VANS is interrogated to commit id dde093b2 .
> However the newer version of gem5 breaks a lot of old Python interfaces,
> making it unable to run with VANS GEM5 wrapper, although compilation is
> fine.
> When I run VANS with new version gem5.
> The respond pkt can not sent via port.sendTimingResp.
>
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[gem5-users] Re: CXL protocol/model implementation

[Jason Lowe-Power via gem5-users]

Hi Zicong,

1. I personally don't believe that CXL in SE mode would be very
interesting. From  my point of view, CXL would be interesting only to
capture the OS and system-level effects. That said, you may be able to test
CXL.cache in SE mode.

2.
To implement the different protocols:
CXL.io: This would be extending the PCI devices in gem5/src/dev. This part
of the protocol will need to be implemented functionally to get the OS
drivers to work correctly.
CXL.mem: This should be quite straightforward to implement without any
changes to any coherence protocols. This part of CXL would just be setting
up the memory ranges correctly and hooking it into CXL.io. I would start
with this one.
CXL.cache: To model the coherence in CXL.cache, you will need to add and/or
modify a new Ruby coherence protocol. To get this to work, you'll first
have to have CXL.io and be able to figure out how to communicate the memory
ranges (like CXL.mem).

3.
CXLDevice would most likely inherit from PciDevice. The other devices would
be whatever you want them to be (e.g., a GPU which speaks CXL.cache or a
memory device that speaks CXL.mem). Then these devices would "register"
with the CXLDevice and through the configuration file you will hook up the
other devices in the protocol.

The most complex part of all of this will be the configuration. I would
suggest trying to make the configuration as modular as possible. The
examples in the standard library should help.

I've given this some thought, but I haven't started implementing anything.
I'm sure that the process I outlined above will change as you start diving
into things.

Cheers,
Jason

On Fri, Mar 25, 2022 at 1:35 AM Zicong Wang via gem5-users <
gem5-users@gem5.org> wrote:

> Hi Jason,
>
>  We are planning to implement and test CXL protocol/model with gem5, and
> I've seen your reply about CXL implementation (
> https://www.mail-archive.com/gem5-users@gem5.org/msg18881.html). Before
> diving into the code, I have some questions about implementation. Could you
> please provide some tips? Thanks!​
>
>  1. Could it be implemented in SE mode? It seems to be complicated with
> the OS layer and driver layer in FS mode, and we want to firstly implement
> an initial model (e.g., a type 1 (cxl.io + cxl.cache) or type 3 (cxl.io +
> cxl.mem) device) as simple as possible.
>
>  2. Could the cxl.cache/mem sub-protocol ​be implemented in SLICC? How to
> treat and implement the cxl.io sub-protocol (which is PCIe-like)?
>
>  3. What kind of SimObject should be implemented roughly (CXLDevice,
> CXLController, etc.)?​ Should the CXLDevice be inherited from PciDevice
> class?
>
>  Thank you very much!
>
>
> Best Regards,
>
> Zicong Wang
>
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[gem5-users] Re: Issue with strange virtual address access

[Jason Lowe-Power via gem5-users]

Hi Tom,

I'm not sure. Again, I'd add the Vma and the SyscallVerbose debug flags
which may help figure it out. It's possible that's the address of a
dynamically-loaded library as well.

Also, this trace looks like it came from Arm instead of x86. I don't
have as much experience looking at Arm addresses and guessing the meaning
:).

Cheers,
Jason

On Tue, Mar 22, 2022 at 8:32 AM tomjosekallooran--- via gem5-users <
gem5-users@gem5.org> wrote:

> Hi Jason,
> I have one doubt.
> The following is some selected parts of Exec trace:
> If we look at lines:
> line 4:   ldr   x1, [sp]: MemRead :
> D=0x0001
> A=0x7efe70
> line 74  :   ldr   x1, [x0]: MemRead :
> D=0x0010
> A=0x7efe90
> line 88  :   ldr   x3, [x8, #3840]: MemRead :  D=0x0001
> A=0x498f00
> line 92  :   ldr   x7, [x10, #3896]  : MemRead :  D=0x0001
> A=0x499f38
> line 152:   ldr   x28, [x0, #8]: MemRead :  D=0x004471e3
> A=0x7efe98
>
> Prior to these lines, there was no MemWrite to the corresponding address.
> Is this also related to Stack addresses?Could you please provide an insight
> on how these addresses are loaded with these data?
>
> Any information on the same would hugely help.
>
> Regards,
> Tom
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[gem5-users] Re: Building Old gem5 error

[Jason Lowe-Power via gem5-users]

Hello Abdelrahman,

Unfortunately, it's incredibly difficult to keep the development
environment for older versions of gem5 working. You may be able to find an
old dockerfile in those gem5 repositories that could help to recreate the
build environment. (I'm not sure if we were using docker at the time or
not.)

Another thing you can try is specifying a python version when running
scons. You can use
```
python2 `which scons` build/X86_MESI_Two_Level/gem5.opt
```
That should force scons to use python2. However, you might find that the
scons version that you installed only works with python3. Again, it's
really hard to get these older gem5's to build on modern systems.

If those two ideas don't work, a final suggestion would be to create a
docker container (or install) Ubuntu 16.04 and try with that. 16.04
should have everything python2 by default.

Good luck!

Cheers,
Jason

On Tue, Mar 22, 2022 at 3:19 AM Abdelrahman S. Hussein via gem5-users <
gem5-users@gem5.org> wrote:

> Hello,
>
> I am trying to build older version(s) of gem5 (specifically, the ones used
> for InvisiSpec and STT). I understand that this version of gem5 requires
> python2, thus, I build a virtual environment based on python2 and
> re-installed scons. However, when I run this command:
> scons build/X86_MESI_Two_Level/gem5.opt -j16
>
> I got the following error:
>
> AttributeError: 'NoneType' object has no attribute 'group':
>   File "stt/SConstruct", line 435:
> *if not as_version or compareVersions(as_version, "2.23") < 0:*
>   File "stt/src/python/m5/util/__init__.py", line 133:
> v1 = make_version_list(v1)
>   File "stt/src/python/m5/util/__init__.py", line 127:
> return map(lambda x: int(re.match('\d+', x).group()), v.split('.'))
>   File "stt/src/python/m5/util/__init__.py", line 127:
> return map(lambda x: int(re.match('\d+', x).group()), v.split('.'))
>
> Same with InvisiSpec.
>
> Before line 435@stt/SConstruct, which is underlined above, line 433 has
> the following:
> as_version = as_version_raw[-1].split('-')[0] if as_version_raw else None
>
> When I printed as_version, its value was:
> same
>
> How can I solve this problem? Or, what further information do you need me
> to share?
>
> Thank you!
>
> --
>
> *Best,Abdelrahman Hussein*
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[gem5-users] Re: Issue with strange virtual address access

[Jason Lowe-Power via gem5-users]

Hi Liyan,

This looks like a stack address to me, so it won't appear in the objdump.

Since you're using SE mode, gem5 is controlling the physical address
mappings (not the OS). You can use the "Vma" debug flag to see all of the
virtual memory areas that gem5 creates/assigns. the "SyscallVerbose" flag
could also be useful.

Cheers,
Jason

On Mon, Mar 21, 2022 at 12:46 AM liyan.chen--- via gem5-users <
gem5-users@gem5.org> wrote:

> Hi all,
>
> I used the following command to view the virtual address translation
> process.
>
>   build/X86/gem5.opt --debug-flags=Exec,TLB
> --debug-file=/home/liyan/Desktop/gem5/m5out/debug.txt configs/example/se.py
> --cpu-type=TimingSimpleCPU --caches --l2cache --mem-type=DRAMsim3
> --num-cpus=1 -c "tests/test-progs/hello/bin/x86/linux/hello"
>
> However, I found some strange virtual address such as 0x7fffee20
>
>   56500: system.cpu.dtb: Translating vaddr 0x7fffee20.
>   56500: system.cpu.dtb: In protected mode.
>   56500: system.cpu.dtb: Paging enabled.
>   56500: system.cpu.dtb: Handling a TLB miss for address 0x7fffee20 at
> pc 0x400a55.
>   56500: system.cpu.dtb: Mapping 0x7fffe000 to 0xbd000
>   56500: system.cpu.dtb: Miss was serviced.
>   56500: system.cpu.dtb: Entry found with paddr 0xbd000, doing protection
> checks.
>   56500: system.cpu.dtb: Translated 0x7fffee20 -> 0xbde20.
>
> And it(0x7fffee20) also appears here(I don't know whether there is any
> relationship)
>
>   56500: system.cpu T0 : @_start+5: pop rsi
>   56500: system.cpu T0 : @_start+5.0  :   POP_R : ldis   t1, SS:[rsp] :
> MemRead :  D=0x0001 A=0x7fffee20
>  110500: system.cpu T0 : @_start+5.1  :   POP_R : addi   rsp, rsp, 0x8 :
> IntAlu :  D=0x7fffee28
>  110500: system.cpu T0 : @_start+5.2  :   POP_R : mov   rsi, rsi, t1 :
> IntAlu :  D=0x0001
>
> Then I used following command to check the address in hello.dump file but
> didn't find such address.
>
>   objdump -D hello > hello.dump
>
> I'm not familiar with the compilation process and work flow of the core.
> Does anyone know why these address exist?
>
> Any ideas are appreciated! Please reply if you have some advice. Thanks in
> advance!
>
> Liyan Chen
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[gem5-users] Re: How do I disable most statistics in the stats.txt under Atomic CPU

[Jason Lowe-Power via gem5-users]

Hello,

I don't believe there's a way to do that right now. However, in atomic
mode, many stats *are* skipped as they are only accessed in the "timing"
functions. I doubt it would make much performance difference. However,
that's just a guess, and I could be wrong.

Cheers,
Jason

On Wed, Mar 16, 2022 at 6:25 PM Liyichao via gem5-users 
wrote:

> Hi All:
>
>  In the Atomic CPU, only a function simulation is performed for
> enabling or debugging applications. The performance statistics of the
> architecture are not concerned. Therefore, only a small items are required,
> e.g. number of instructions or cycles.
>
>
>
> According to my understanding, each performance measurement item in the
> code may affect the simulation speed. If we can disable statistics items
> that are not concerned in most functional models, the simulation speed may
> be greatly improved. I do not know whether my understanding is correct. If
> so, does GEM5 consider the performance statistics switch?
>
>
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[gem5-users] Re: Is thread lock not working under both SE and FS mode?

[Jason Lowe-Power via gem5-users]

Hi Meng,

It depends on the ISA you're using and the configuration of the system. For
instance, x86+classic caches is known to have some synchronization issues.
The transactional memory support only works with Arm, and I'm not sure
which memory system it requires.

What system are you trying to simulate?

Cheers,
Jason

On Sat, Mar 12, 2022 at 11:45 PM Chen Meng via gem5-users <
gem5-users@gem5.org> wrote:

> Hi!
>
> I was trying to run a multi-threaded program with thread locks, I tried
> many methods but only to result in failure. I borrowed the program code
> with thread lock from the following page:
> https://www.gem5.org/project/2020/10/27/tme.html , and it turns out to be
> unstable when I run it with FS mode.
>
> My gem5 version is v21.1.0.2, and my script is borrowed from
> gem5_resources also at v21.1.0.2 (
> https://gem5.googlesource.com/public/gem5-resources/+/refs/tags/v21.1.0.2),
> everything is stick to the SPEC-2017 tutorial (
> https://gem5.googlesource.com/public/gem5-resources/+/refs/tags/v21.1.0.2/src/spec-2017/README.md),
> except that I substitute the SPEC benchmarks with my own program.
>
> Any ideas are appreciated! Please reply if you have some advice or
> face/have faced the same problem. Thanks!
>
> Best Regards,
> Meng
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[gem5-users] Re: Running FS in example/gem5_library/x86-spec-cpu2017-benchmarks.py

[Jason Lowe-Power via gem5-users]

Hi Abdelrahman,


> Is there a better way you can suggest using SPEC2017 in FS mode to
> evaluate my system on gem5?
>

No, there's not a better way, as far as I know :).


> My understanding is that the FS simulation is significantly slow. Any
> guidelines on how to make it as fast as possible?


You can use sampling methodologies, but there are tradeoffs there. You can
run different simulation configurations in parallel as well. Generally,
there's nothing easy to do to improve simulation speed.

Jason

On Thu, Mar 10, 2022 at 7:17 AM Abdelrahman S. Hussein <
abdelrahman.sob...@gmail.com> wrote:

> Thank you so much.
>
> There were some questions that you missed at the end of the email. I list
> them below again for convenience:
>
>
>- Is there a better way you can suggest using SPEC2017 in FS mode to
>evaluate my system on gem5?
>- My understanding is that the FS simulation is significantly slow.
>Any guidelines on how to make it as fast as possible?
>
> Above all, thanks a lot for taking time helping us. Much appreciated!
>
>
>
>
> On Thu, Mar 10, 2022 at 7:01 AM Jason Lowe-Power 
> wrote:
>
>> Hi Abdelrahman,
>>
>> From the get error message, it says:
>> "This error may be caused by a too restrictive setting
>>   in the file '/proc/sys/kernel/perf_event_paranoid'
>>   The default value was changed to 2 in kernel 4.6
>>   A value greater than 1 prevents gem5 from making
>>   the syscall to perf_event_open"
>>
>> If you put `1` or `0` in /proc/sys/kernel/perf_event_paranoid it should
>> work.
>>
>> Cheers,
>> Jason
>>
>> On Wed, Mar 9, 2022 at 9:27 PM Abdelrahman S. Hussein <
>> abdelrahman.sob...@gmail.com> wrote:
>>
>>> Hello,
>>>
>>> I am trying to run gem5 in FS mode using the following command (I am
>>> using gem5 v21.2):
>>>
>>> gem5/build/X86/gem5.opt
>>> gem5/configs/example/gem5_library/x86-spec-cpu2017-benchmarks.py --image
>>> spec-2017/disk-image/spec-2017/spec-2017-image/spec-2017 --benchmark
>>> 503.bwaves_r --size test
>>>
>>> However, I got the following error (There are details after the error,
>>> please continue reading after you check the error):
>>>
>>> build/X86/sim/simulate.cc:194: info: Entering event queue @ 0.  Starting
>>> simulation...
>>> build/X86/cpu/kvm/perfevent.cc:176: panic: PerfKvmCounter::attach
>>> recieved error EACCESS
>>>   This error may be caused by a too restrictive setting
>>>   in the file '/proc/sys/kernel/perf_event_paranoid'
>>>   The default value was changed to 2 in kernel 4.6
>>>   A value greater than 1 prevents gem5 from making
>>>   the syscall to perf_event_open
>>> Memory Usage: 3817816 KBytes
>>> build/X86/cpu/kvm/perfevent.ccProgram aborted at tick 0
>>> :176: panic: PerfKvmCounter::attach recieved error EACCESS
>>>   This error may be caused by a too restrictive setting
>>>   in the file '/proc/sys/kernel/perf_event_paranoid'
>>>   The default value was changed to 2 in kernel 4.6
>>>   A value greater than 1 prevents gem5 from making
>>>   the syscall to perf_event_open
>>> Memory Usage: 3817816 KBytes
>>> ./spec_fs_run.sh: line 16: 1648681 Aborted
>>>
>>> I have done some checking:
>>>
>>>- Ran kvm-ok to make sure that KVM is working:
>>>$kvm-ok
>>>INFO: /dev/kvm exists
>>>KVM acceleration can be used
>>>
>>>- Also, I checked the value
>>>inside /proc/sys/kernel/perf_event_paranoid
>>>$cat /proc/sys/kernel/perf_event_paranoid
>>>3
>>>
>>>- The SPEC17 is created by following the instructions in:
>>>https://gem5art.readthedocs.io/en/v1.0.0/tutorials/spec2017-tutorial.html
>>>
>>>
>>> Questions:
>>>
>>>- How to solve this error?
>>>
>>>- Is it safe to modify the /proc/sys/kernel/perf_event_paranoid of
>>>the linux running on my host machine to 1, in case this solves the 
>>> problem?
>>>
>>>- Is there a better way you can suggest using SPEC2017 in FS mode to
>>>evaluate my system on gem5?
>>>
>>>
>>>
>>> Thanks.
>>>
>>> --
>>>
>>> *Best,Abdelrahman Hussein*
>>>
>> --
>
> --
>
> *Best,Abdelrahman Hussein*
>
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[gem5-users] Re: Running FS in example/gem5_library/x86-spec-cpu2017-benchmarks.py

[Jason Lowe-Power via gem5-users]

Hi Abdelrahman,

>From the get error message, it says:
"This error may be caused by a too restrictive setting
  in the file '/proc/sys/kernel/perf_event_paranoid'
  The default value was changed to 2 in kernel 4.6
  A value greater than 1 prevents gem5 from making
  the syscall to perf_event_open"

If you put `1` or `0` in /proc/sys/kernel/perf_event_paranoid it should
work.

Cheers,
Jason

On Wed, Mar 9, 2022 at 9:27 PM Abdelrahman S. Hussein <
abdelrahman.sob...@gmail.com> wrote:

> Hello,
>
> I am trying to run gem5 in FS mode using the following command (I am using
> gem5 v21.2):
>
> gem5/build/X86/gem5.opt
> gem5/configs/example/gem5_library/x86-spec-cpu2017-benchmarks.py --image
> spec-2017/disk-image/spec-2017/spec-2017-image/spec-2017 --benchmark
> 503.bwaves_r --size test
>
> However, I got the following error (There are details after the error,
> please continue reading after you check the error):
>
> build/X86/sim/simulate.cc:194: info: Entering event queue @ 0.  Starting
> simulation...
> build/X86/cpu/kvm/perfevent.cc:176: panic: PerfKvmCounter::attach recieved
> error EACCESS
>   This error may be caused by a too restrictive setting
>   in the file '/proc/sys/kernel/perf_event_paranoid'
>   The default value was changed to 2 in kernel 4.6
>   A value greater than 1 prevents gem5 from making
>   the syscall to perf_event_open
> Memory Usage: 3817816 KBytes
> build/X86/cpu/kvm/perfevent.ccProgram aborted at tick 0
> :176: panic: PerfKvmCounter::attach recieved error EACCESS
>   This error may be caused by a too restrictive setting
>   in the file '/proc/sys/kernel/perf_event_paranoid'
>   The default value was changed to 2 in kernel 4.6
>   A value greater than 1 prevents gem5 from making
>   the syscall to perf_event_open
> Memory Usage: 3817816 KBytes
> ./spec_fs_run.sh: line 16: 1648681 Aborted
>
> I have done some checking:
>
>- Ran kvm-ok to make sure that KVM is working:
>$kvm-ok
>INFO: /dev/kvm exists
>KVM acceleration can be used
>
>- Also, I checked the value inside /proc/sys/kernel/perf_event_paranoid
>$cat /proc/sys/kernel/perf_event_paranoid
>3
>
>- The SPEC17 is created by following the instructions in:
>https://gem5art.readthedocs.io/en/v1.0.0/tutorials/spec2017-tutorial.html
>
>
> Questions:
>
>- How to solve this error?
>
>- Is it safe to modify the /proc/sys/kernel/perf_event_paranoid of the
>linux running on my host machine to 1, in case this solves the problem?
>
>- Is there a better way you can suggest using SPEC2017 in FS mode to
>evaluate my system on gem5?
>
>
>
> Thanks.
>
> --
>
> *Best,Abdelrahman Hussein*
>
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[gem5-users] Re: M5 Fs utility workbegin

[Jason Lowe-Power via gem5-users]

Great question!

Since KVM is executing using the host's hardware, you can't use the magic
instructions! However, we have another interface (called `m5_addr` or
`m5-addr` in the code, IIRC) that will work with KVM. If you compile using
-DM5_ADDR=, it should work in KVM. For x86, we usually
use 0x. Then, I believe you need to call a function to map
the memory (not sure what it's called, it's not in the documentation)
before calling any m5 functions.

See
https://gem5.googlesource.com/public/gem5-resources/+/refs/heads/stable/src/parsec/disk-image/parsec/parsec-benchmark/pkgs/libs/hooks/src/hooks.c#96
for an example.
Also see
https://gem5.googlesource.com/public/gem5-resources/+/refs/heads/stable/src/parsec/disk-image/parsec/parsec-benchmark/pkgs/libs/hooks/src/Makefile.shared#9
for how we compile the parsec hooks with m5 addr.

Note: it looks like either parsec is a bit out of date with current gem5
develop or the README.md in util/m5 is out of date. I'm not sure which.

Cheers,
Jason

On Wed, Mar 9, 2022 at 4:47 PM George Michelogiannakis <
mixelog...@yahoo.co.uk> wrote:

> Hello Jason and everyone,
>
> I'll add the fix to my todo list :)
>
> But before then, I'm confused by something. Thanks for the link to hooks
> and indeed I "m5_work_begin(0,0);. I recompiled the benchmarks I had with
> work begin and end. It's just adding "m5_work_begin(0,0)" and 
> "m5_work_end(0,0)"
> at the right spots, without anything else fancy. It compiles and links
> fine. When I try to run natively as expected they terminate due to an
> illegal instruction ("./run: line 1:  1161 Illegal instruction").
> However, the exact same error happens if I run the same binary in FS mode.
> Note that I'm running first in KVM mode on a x86 host hoping to switch CPUs
> once the work start event happens. Are magic ops unsupported in KVM mode?
>
> Thanks!
>
>
> On Wednesday, March 9, 2022, 09:14:24 AM PST, Jason Lowe-Power via
> gem5-users  wrote:
>
>
> Hi George,
>
> For workbegin/workend, they can be called from within applications if you
> link to the libm5 library. For instance, in the parsec resource here:
> https://resources.gem5.org/resources/parsec we use the m5_workbegin()
> function in the ROI hooks. See
> https://gem5.googlesource.com/public/gem5-resources/+/refs/heads/stable/src/parsec/disk-image/parsec/parsec-benchmark/pkgs/libs/hooks/src/hooks.c#96
> for the code.
>
> This works in both SE mode and FS mode. I have no idea why those functions
> are not available in the m5 binary. This seems like an oversight, and it
> should be a simple fix. If you want to make the fix, we'd appreciate it,
> otherwise, we'll put it on the to do list :).
>
> If you require using the m5 binary without any changes, then you can use
> `m5 exit` and modify your run script to "understand" that the first exit is
> to reset the stats, the second exit means to dump the stats, etc.
>
> Cheers,
> Jason
>
> On Wed, Mar 9, 2022 at 4:08 AM Gabe Black via gem5-users <
> gem5-users@gem5.org> wrote:
>
> I don't think we ever transitioned from an assembly based mechanism to a C
> based one, since we have always (as far as I know) used both, assembly to
> actually invoke the call into gem5, and C to provide a friendly
> interface/wrapper around the assembly. That said, yes, it looks like work
> begin and work end are just not in the utility, but they are in the header
> files and are implemented in gem5 itself.
>
> Looking at this again triggered a vague memory where I think these didn't
> make sense being called from the utility for some reason? Maybe they only
> make sense in SE mode, or they should be called from code directly instead
> of from a shell or script? I'm not very familiar with them so I can't say
> for sure, but I vaguely remember there was something like that.
>
> Gabe
>
> On Wed, Mar 9, 2022 at 2:45 AM Giacomo Travaglini <
> giacomo.travagl...@arm.com> wrote:
>
> Hi George,
>
>
>
> Thanks for reporting this, I noticed the same issue. When we transitioned
> from the old m5 subsystem (assembly based) to the new C based one we forgot
> to provide an implementation for workbegin and workend I suppose. Putting
> Gabe on CC
>
>
>
> Kind Regards
>
>
>
> Giacomo
>
>
>
> *From: *George Michelogiannakis via gem5-users 
> *Date: *Wednesday, 9 March 2022 at 06:54
> *To: *gem5-users@gem5.org 
> *Cc: *George Michelogiannakis 
> *Subject: *[gem5-users] M5 Fs utility workbegin
>
> Hello Gem5 community,
>
>
>
> I'm trying to use the M5 utility meant for full system mode to signal work
> begin and end. I see in the documentation that the utility supports these
> parameters:
>
>
>
>-

[gem5-users] Re: M5 Fs utility workbegin

[Jason Lowe-Power via gem5-users]

Hi George,

For workbegin/workend, they can be called from within applications if you
link to the libm5 library. For instance, in the parsec resource here:
https://resources.gem5.org/resources/parsec we use the m5_workbegin()
function in the ROI hooks. See
https://gem5.googlesource.com/public/gem5-resources/+/refs/heads/stable/src/parsec/disk-image/parsec/parsec-benchmark/pkgs/libs/hooks/src/hooks.c#96
for the code.

This works in both SE mode and FS mode. I have no idea why those functions
are not available in the m5 binary. This seems like an oversight, and it
should be a simple fix. If you want to make the fix, we'd appreciate it,
otherwise, we'll put it on the to do list :).

If you require using the m5 binary without any changes, then you can use
`m5 exit` and modify your run script to "understand" that the first exit is
to reset the stats, the second exit means to dump the stats, etc.

Cheers,
Jason

On Wed, Mar 9, 2022 at 4:08 AM Gabe Black via gem5-users <
gem5-users@gem5.org> wrote:

> I don't think we ever transitioned from an assembly based mechanism to a C
> based one, since we have always (as far as I know) used both, assembly to
> actually invoke the call into gem5, and C to provide a friendly
> interface/wrapper around the assembly. That said, yes, it looks like work
> begin and work end are just not in the utility, but they are in the header
> files and are implemented in gem5 itself.
>
> Looking at this again triggered a vague memory where I think these didn't
> make sense being called from the utility for some reason? Maybe they only
> make sense in SE mode, or they should be called from code directly instead
> of from a shell or script? I'm not very familiar with them so I can't say
> for sure, but I vaguely remember there was something like that.
>
> Gabe
>
> On Wed, Mar 9, 2022 at 2:45 AM Giacomo Travaglini <
> giacomo.travagl...@arm.com> wrote:
>
>> Hi George,
>>
>>
>>
>> Thanks for reporting this, I noticed the same issue. When we transitioned
>> from the old m5 subsystem (assembly based) to the new C based one we forgot
>> to provide an implementation for workbegin and workend I suppose. Putting
>> Gabe on CC
>>
>>
>>
>> Kind Regards
>>
>>
>>
>> Giacomo
>>
>>
>>
>> *From: *George Michelogiannakis via gem5-users 
>> *Date: *Wednesday, 9 March 2022 at 06:54
>> *To: *gem5-users@gem5.org 
>> *Cc: *George Michelogiannakis 
>> *Subject: *[gem5-users] M5 Fs utility workbegin
>>
>> Hello Gem5 community,
>>
>>
>>
>> I'm trying to use the M5 utility meant for full system mode to signal
>> work begin and end. I see in the documentation that the utility supports
>> these parameters:
>>
>>
>>
>>- workbegin: Cause an exit evet of type, “workbegin”, that could be
>>used to mark the begining of an ROI.
>>- workend: Cause an exit event of type, “workend”, that could be used
>>to mark the termination of an ROI.
>>
>> But when I run the utility in X86 after compiling it for X86 those two
>> options aren't available as commands. There is a "fail" option with a
>> parameter that isn't mentioned in the documentation. Is that the way to
>> simulate workbegin and workend?
>>
>>
>>
>> Thanks in advance,
>>
>>   George M
>>
>>
>>
>>
>> IMPORTANT NOTICE: The contents of this email and any attachments are
>> confidential and may also be privileged. If you are not the intended
>> recipient, please notify the sender immediately and do not disclose the
>> contents to any other person, use it for any purpose, or store or copy the
>> information in any medium. Thank you.
>>
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[gem5-users] Re: Inquiry on the gem5 communities and forums

[Jason Lowe-Power via gem5-users]

Hi Jianda,

There will also be a tutorial and workshop at ISCA in New York this year
(June 11). More info coming soon!

Cheers,
Jason

On Fri, Feb 18, 2022 at 8:21 AM Gabriel Busnot via gem5-users <
gem5-users@gem5.org> wrote:

> Hi and welcome Jianda,
>
> You are in the right place! Feel free to subscribe to this mailing list to
> get notified upon new post. You can also post any question related to gem5.
> You will usually get an answer within a working day or two. You can also
> monitor the Jira to learn about what is going on in the background (
> https://gem5.atlassian.net/jira/software/c/projects/GEM5/issues).
>
> Best,
> Gabriel
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[gem5-users] Re: Not able to access webpage to run_npb.py

[Jason Lowe-Power via gem5-users]

Hi David,

Sorry for the confusion. We need to update that documentation! You can now
find the script here:
https://gem5.googlesource.com/public/gem5/+/refs/heads/stable/configs/example/gem5_library/x86-npb-benchmarks.py
(or in configs/example/gem5_library in the gem5 repo).

Cheers,
Jason

On Thu, Feb 17, 2022 at 10:42 AM David Fong via gem5-users <
gem5-users@gem5.org> wrote:

> Hi,
>
>
>
> I’m going through the steps to create the npb environment.
>
>
>
> https://www.gem5.org/documentation/gem5art/tutorials/npb-tutorial
>
>
> gem5 run scripts
>
> Next, we need to add gem5 run scripts. We will do that in a folder named
> configs-npb-tests. Get the run script named run_npb.py from here
> ,
> and other system configuration files from [here]((
> https://gem5.googlesource.com/public/gem5-resources/+/refs/heads/stable/src/npb/configs/system/
> ).
>
>
>
>
>
> I’m not able to access the link to “run_npb.py”.
>
>
>
>
> https://gem5.googlesource.com/public/gem5-resources/+/refs/heads/stable/src/npb/configs/run_npb.py
>
>
>
> I get this error
>
>
>
>
>
> Does anyone else have this problem and how to workaround ?
>
> Is there another location to download the “run_npb.py” ?
>
>
>
> Thanks,
>
>
>
> David
>
>
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[gem5-users] Re: Does the gem5 v21.0.1.0 support to bootup with kernel 5.10 in Ruby-CHI and O3

[Jason Lowe-Power via gem5-users]

Hello,

This specific setup has not been tested, as far as I know. I would also
suggest using v21.2.1 as there have been lots of bugfixes to CHI in the
past year.

Cheers,
Jason

On Tue, Feb 15, 2022 at 6:23 PM Liyichao via gem5-users 
wrote:

> Hi All:
>
>  Does the gem5 v21.0.1.0 support to bootup with kernel 5.10 in
> Ruby-CHI and O3?
>
> Or if anyone has ever bootup with it?
>
>
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[gem5-users] Re: Run srsRAN code with gem5

[Jason Lowe-Power via gem5-users]

Hi Uma,

Not all X86 vector instructions are implemented. What you're seeing is
that pmovzxbw isn't
implemented. Specifically, there's at least one version (as shown here
https://www.felixcloutier.com/x86/pmovzx) which hasn't been implemented
yet. I'm not sure which one. The `Vdq_Udq_or_Mq` somehow specifies the
sizes of the registers, but it's not documented and you'll have to dig into
the code to figure out how it works.

You can either compile your code with SSE4/AVX or you can implement the
instruction. If you do the latter, we would appreciate the contribution!

Cheers,
Jason

On Fri, Feb 11, 2022 at 5:13 AM VEDIKA JITENDRA KULKARNI via gem5-users <
gem5-users@gem5.org> wrote:

> Hello,
>
>
> *We are trying to run srsRAN functionalities individually as srsepc,srsenb
> and srsUE. Also I need suggestions on how to run end-end srsRAN code into
> gem5 to analyse the ARM vs X86 performance. *
>
>
> *Please find the below error for srsENB while simulating in gem5.*
>
>
>
> command line: ./build/X86/gem5.opt configs/example/se.py
> --cmd=tests/test-progs/hello/bin/x86/linux/srsenb
>
>
>
> Global frequency set at 1 ticks per second
>
> warn: No dot file generated. Please install pydot to generate the dot file
> and pdf.
>
> build/X86/mem/mem_interface.cc:791: warn: DRAM device capacity (8192
> Mbytes) does not match the address range assigned (512 Mbytes)
>
> 0: system.remote_gdb: listening for remote gdb on port 7000
>
>  REAL SIMULATION 
>
> build/X86/sim/simulate.cc:194: info: Entering event queue @ 0.  Starting
> simulation...
>
> build/X86/sim/syscall_emul.cc:74: warn: ignoring syscall mprotect(...)
>
> build/X86/sim/syscall_emul.cc:74: warn: ignoring syscall mprotect(...)
>
> build/X86/sim/syscall_emul.cc:74: warn: ignoring syscall mprotect(...)
>
>
>
> build/X86/sim/syscall_emul.cc:74: warn: ignoring syscall
> set_robust_list(...)
>
> build/X86/sim/syscall_emul.cc:85: warn: ignoring syscall rt_sigaction(...)
>
>   (further warnings will be suppressed)
>
> build/X86/sim/syscall_emul.cc:85: warn: ignoring syscall
> rt_sigprocmask(...)
>
>   (further warnings will be suppressed)
>
> build/X86/sim/syscall_emul.hh:509: warn: futex: op 7 not implemented;
> ignoring.
>
>
>
> build/X86/sim/syscall_emul.cc:74: warn: ignoring syscall mprotect(...)
>
> build/X86/arch/x86/generated/exec-ns.cc.inc:27: warn: instruction
> 'pmovzxbw_Vdq_Udq_or_Mq' unimplemented
>
> *build/X86/arch/x86/faults.cc:129: panic: Unrecognized/invalid instruction
> executed:*
>
>
>
> {
>
> leg = 0x10,
>
> rex = 0,
>
> vex/xop = 0x5,
>
> op = {
>
> type = three byte 0f38,
>
> op = 0x59,
>
> },
>
> modRM = 0,
>
> sib = 0,
>
> immediate = 0,
>
> displacement = 0
>
> dispSize = 0}
>
> Memory Usage: 842444 KBytes
>
> Program aborted at tick 7880406000
>
> --- BEGIN LIBC BACKTRACE ---
>
> ./build/X86/gem5.opt(+0x67429c)[0x5620be8bc29c]
>
> ./build/X86/gem5.opt(+0x6a0eaa)[0x5620be8e8eaa]
>
> /lib/x86_64-linux-gnu/libpthread.so.0(+0x12980)[0x7f1b35eeb980]
>
> /lib/x86_64-linux-gnu/libc.so.6(gsignal+0xc7)[0x7f1b34d3efb7]
>
> /lib/x86_64-linux-gnu/libc.so.6(abort+0x141)[0x7f1b34d40921]
>
> ./build/X86/gem5.opt(+0x342b6f)[0x5620be58ab6f]
>
> ./build/X86/gem5.opt(+0x74f8b7)[0x5620be9978b7]
>
> ./build/X86/gem5.opt(+0xe9218a)[0x5620bf0da18a]
>
> ./build/X86/gem5.opt(+0xe7f779)[0x5620bf0c7779]
>
> ./build/X86/gem5.opt(+0x680fee)[0x5620be8c8fee]
>
> ./build/X86/gem5.opt(+0x6c5fd4)[0x5620be90dfd4]
>
> ./build/X86/gem5.opt(+0x6c6d1e)[0x5620be90ed1e]
>
> ./build/X86/gem5.opt(+0xc2b44a)[0x5620bee7344a]
>
> ./build/X86/gem5.opt(+0x69ced9)[0x5620be8e4ed9]
>
>
> /usr/lib/x86_64-linux-gnu/libpython3.6m.so.1.0(PyCFunction_Call+0x96)[0x7f1b3630b736]
>
>
> /usr/lib/x86_64-linux-gnu/libpython3.6m.so.1.0(_PyEval_EvalFrameDefault+0x76e0)[0x7f1b3627cb20]
>
> /usr/lib/x86_64-linux-gnu/libpython3.6m.so.1.0(+0x17ba0f)[0x7f1b36273a0f]
>
> /usr/lib/x86_64-linux-gnu/libpython3.6m.so.1.0(+0x17c0fc)[0x7f1b362740fc]
>
>
> /usr/lib/x86_64-linux-gnu/libpython3.6m.so.1.0(_PyEval_EvalFrameDefault+0x4ec3)[0x7f1b3627a303]
>
> /usr/lib/x86_64-linux-gnu/libpython3.6m.so.1.0(+0x17a803)[0x7f1b36272803]
>
> /usr/lib/x86_64-linux-gnu/libpython3.6m.so.1.0(+0x17c2be)[0x7f1b362742be]
>
>
> /usr/lib/x86_64-linux-gnu/libpython3.6m.so.1.0(_PyEval_EvalFrameDefault+0x4ec3)[0x7f1b3627a303]
>
> /usr/lib/x86_64-linux-gnu/libpython3.6m.so.1.0(+0x17ba0f)[0x7f1b36273a0f]
>
> /usr/lib/x86_64-linux-gnu/libpython3.6m.so.1.0(+0x17c0fc)[0x7f1b362740fc]
>
>
> /usr/lib/x86_64-linux-gnu/libpython3.6m.so.1.0(_PyEval_EvalFrameDefault+0x4ec3)[0x7f1b3627a303]
>
> /usr/lib/x86_64-linux-gnu/libpython3.6m.so.1.0(+0x17ba0f)[0x7f1b36273a0f]
>
>
> /usr/lib/x86_64-linux-gnu/libpython3.6m.so.1.0(PyEval_EvalCodeEx+0x3e)[0x7f1b362744ce]
>
>
> /usr/lib/x86_64-linux-gnu/libpython3.6m.so.1.0(PyEval_EvalCode+0x1b)[0x7f1b3627524b]
>
> 

[gem5-users] Re: findOrCreate function

[Jason Lowe-Power via gem5-users]

Hi Scott,

I think the answer is the same as the prior email. You need to register an
exit callback to close the file stream :). See, for instance, the elastic
trace code:
https://gem5.googlesource.com/public/gem5/+/refs/heads/stable/src/cpu/o3/probe/elastic_trace.cc#103

Cheers,
Jason

On Wed, Feb 9, 2022 at 5:19 PM Scott Blankenberg via gem5-users <
gem5-users@gem5.org> wrote:

> Hello all,
>
> Has anyone used the findOrCreate Gem5 function for opening custom file
> streams?
>
> For example in src/cpu/base.cc we see that this function is used in the
> constructor for BaseCPU
>
>   const std::string fname = csprintf("ftrace.%s", name());
>   functionTraceStream = simout.findOrCreate(fname)->stream();
>
>
> Has anyone who has used this function called it to create .gz files?
>
> I am having an issue right now where for some benchmarks I run that the
> final gz file I get out is not compressed correctly. When I attempt to
> decompress the .gz files, I will get errors such as "unexpected end of
> file".
>
> One possibility I can think of is that the file does not close properly.
> However, I am struggling to find out where I should close the file since I
> need to do it at the end of the simulation and there is no clear place in
> BaseCPU code to place code you want to execute at the end of simulation. I
> have tried using the BaseCPU destructor to close my stream files, but the
> code I put into this destructor does not seemed to be invoked.
>
> Anyways, has anyone ran into similar issues?
>
> Thanks,
>
> Scott Blankenberg
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[gem5-users] Re: Destructor for BaseCPU

[Jason Lowe-Power via gem5-users]

Hi Scott,

If you want something to execute before gem5 is completed, you can call
`registerExitCallback`. See
http://doxygen.gem5.org/release/current/namespacegem5.html#abcf3056836ee522620e5b14d9392ea87

I *think* that will solve your problem, but let me know if not. I don't
think there's a clean way to have a SimObject's destructor guaranteed to be
called.

Cheers,
Jason

On Wed, Feb 9, 2022 at 4:47 PM Scott Blankenberg via gem5-users <
gem5-users@gem5.org> wrote:

> Hello,
>
> In src/cpu/base.cc we have the following destructor:
>
> BaseCPU::~BaseCPU()
> {
> }
>
> By default nothing is inside of it. However, when I put code inside, it
> does not seem to be executed at any point. Based on some previous threads I
> have seen on the forums, it seems that the destructor for BaseCPU is not
> being called at the end of the simulation.
>
> Has anyone found a way to make sure this destructor is called when the
> simulation ends?
>
> Similarly, has anyone written a tracer which is a subclass of InstTracer
> that has a destructor which is successfully called at the end of
> simulation?
>
> Basically my objective is to make sure the destructor to my customTracer
> is called at the end of the simulation.
>
> Thanks,
>
> Scott Blankenberg
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[gem5-users] Re: Problems on creating HelloObject & re-compiling following tutorial

[Jason Lowe-Power via gem5-users]

Namespaces were recently added to gem5 and the documentation hasn't been
updated, yet. We'll put that on the to do list.

Cheers,
Jason

On Wed, Feb 2, 2022 at 6:11 AM Zhang Zhiyuan via gem5-users <
gem5-users@gem5.org> wrote:

> Dear gem5 faculties:
>
> Hi! I’ve been trying to follow the getting started guide on the gem5
> website, and encountered this question in “Creating a very simple
> SimObject” part of the tutorial. I removed the files under
> src/learning_gem5/part2, and substituted them with the following files,
> content of which are precisely copied down from the tutorial:
>
> However, when I tried to recompile the gem5.opt, the following error was
> shown:
>
>
>
> In file included from build/X86/learning_gem5/part_new/hello_object.cc:2:
>
> build/X86/learning_gem5/part_new/hello_object.hh:8:1: error: expected
> class-name before '{' token
>
> 8 | {
>
>   | ^
>
> build/X86/learning_gem5/part_new/hello_object.hh:10:27: error:
> 'HelloObjectParams' does not name a type; did you mean 'HelloObject'?
>
>10 | HelloObject(const HelloObjectParams );
>
>   |   ^
>
>   |   HelloObject
>
> build/X86/learning_gem5/part_new/hello_object.cc:6:32: error:
> 'HelloObjectParams' does not name a type; did you mean 'HelloObject'?
>
> 6 | HelloObject::HelloObject(const HelloObjectParams ) : SimObject(p)
>
>   |^
>
>   |HelloObject
>
> build/X86/learning_gem5/part_new/hello_object.cc: In constructor
> 'HelloObject::HelloObject(const int&)':
>
> build/X86/learning_gem5/part_new/hello_object.cc:6:56: error: class
> 'HelloObject' does not have any field named 'SimObject'
>
> 6 | HelloObject::HelloObject(const HelloObjectParams ) : SimObject(p)
>
>   |^
>
> [SO Param] m5.objects.Ethernet, EtherLink -> X86/params/EtherLink.hh
>
> [SO Param] m5.objects.Ethernet, DistEtherLink ->
> X86/params/DistEtherLink.hh
>
> [SO Param] m5.objects.Ethernet, Sinic -> X86/params/Sinic.hh
>
> [SO Param] m5.objects.FuncUnit, FUDesc -> X86/params/FUDesc.hh
>
> [SO Param] m5.objects.InstPBTrace, InstPBTrace -> X86/params/InstPBTrace.hh
>
> scons: *** [build/X86/learning_gem5/part_new/hello_object.o] Error 1
>
> scons: building terminated because of errors.
>
>
>
> It seems that the HelloObject sources cant find HelloObjectParams and
> SimObject definitions. However, after throwing everything in the header and
> the source file under namespace gem5, and adding cxx_class member in the
> python class definition, everything seems to work out fine. So is it an
> issue that needs to be fixed in the tutorial, or is the namespace inclusion
> unnecessary here? Thanks!
>
>
>
>  Zhiyuan Zhang
>
>
>
>  2022.2.2
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[gem5-users] Re: Clarification minor CPU “in-order”

[Jason Lowe-Power via gem5-users]

Good question, Felix!

The short answer is that since there are instructions that take multiple
cycles to execute you need something like a scoreboard to track the
dependencies.

In the H book, you can see some details of this in Appendix C.5 (6th
edition). If you happen to have the Patterson and Hennessy Computer
Organization and Design book, Section 4.11 (2nd ed. of RISC-V version,
titled "Real Stuff: The ARM Cortex-A53...") shows a pipeline very similar
to the minor CPU.

Cheers,
Jason

On Sat, Jan 29, 2022 at 4:06 PM Felix Böseler via gem5-users <
gem5-users@gem5.org> wrote:

> Hello everybody,
>
> According to [1] the gem5 minor CPU is an in-order processor model and
> features a scoreboarding algorithm. However, according to [2] scoreboarding
> is a dynamic scheduling algorithm with out-of-order execution like the
> Tomasulo algorithm. Therefore, I have the following two questions:
>
> (1) Why is the minor CPU called an in-order CPU model if it has
> scoreboarding capabilities? Is it because the issuing happens in-order,
> nevertheless?
>
> (2) What is the difference between the O3 CPU model and the minor CPU
> model if the minor CPU already has scoreboarding? Does the O3 CPU offers a
> more sophisticated dynamic scheduling approach since [3] mentions register
> renaming (as in the Tomasulo algorithm).
>
> Many regards and many thanks in advance
>
> Felix Böseler
>
> [1] https://www.gem5.org/documentation/general_docs/cpu_models/minor_cpu
>
> [2] Hennessy, John L.; Patterson, David A. (op. 2012): Computer
> architecture. A quantitative approach. 5th ed. Waltham, MA: Morgan
> Kaufmann/Elsevier.
>
> [3] https://www.gem5.org/documentation/general_docs/cpu_models/O3CPU
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[gem5-users] Re: Compiling gem5 on ARM Based Host

[Jason Lowe-Power via gem5-users]

Hi Sam,

I was wondering when this problem would come up again. Here's a Jira issue
to track the same thing in a different context:
https://gem5.atlassian.net/browse/GEM5-1003

Could you do something like `du -h build/ | sort -h` to see what objects
are the biggest? I'm going to guess that there are ~100+ .o files that are
more than 20MB. At least, that was the case with RISC-V when I ran into
this problem.

We never did figure out why so many files were so big. The hypothesis was
something to do with pybind, but no one was able to provide solid evidence
of this. We did find that using a different compiler version, having
different libraries installed on the system, and removing unnecessary
includes seemed to make a difference, though. You may be able to use this
to at least work around the problem.

Here's the changeset that fixed it for RISC-V. However, I doubt it's going
to fix it again in your case.
https://gem5-review.googlesource.com/c/public/gem5/+/46820

You can also try this abandoned change, though it probably won't apply
cleanly or straightforwardly:
https://gem5-review.googlesource.com/c/public/gem5/+/46380

Cheers,
Jason

On Fri, Jan 7, 2022 at 9:39 AM Samuel Thomas via gem5-users <
gem5-users@gem5.org> wrote:

> Hi all,
>
> I typically work on an x86 machine, but I’m trying to submit gem5 jobs to
> a cluster that runs ARM based hosts. Each source script compiles, I run
> into the following error when linking:
>
> /tmp/gem5.fast.unstripped.PI0JsN.ltrans45.ltrans.o: in function
> `ArmV8KvmCPU::updateThreadContext()':
> :(.text+0x25884): relocation truncated to fit:
> R_AARCH64_ADR_PREL_PG_HI21 against `.rodata’collect2: error: ld returned 1
> exit status
>
> It makes sense that the .text segment of the binary will be very large,
> and I see that there is a note on gem5’s architecture support documentation
> that it is out dated. I assume that I can try disassembling the binary and
> seeing if there is an alternative command to avoid this particular linker
> error, but I figured I would also ping the mailing list to see if there is
> an easier fix as well.
>
> Thank you all for your help!
>
> Best,
> Sam
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[gem5-users] Re: some problem about IO device's write or read function's return tick

[Jason Lowe-Power via gem5-users]

Hello,

If you are using *atomic* memory mode, then the tick number is mostly
ignored. If you're using *timing* mode, then the tick number should be used
by whatever object calls the read/write function and the delay is inserted
there. Also, if your program doesn't have a direct dependence on the I/O
device, the latency may be hidden. Enabling various debug flags should help
you track this down.

Cheers,
Jason

On Thu, Dec 23, 2021 at 8:58 AM lin via gem5-users 
wrote:

> Hi
>
> I make an IO device link to the membus and complete the Tick
> read(PacketPtr pkt) and the write() function .But I find that no matter how
> many ticks ( the funciton return n*tick) I set,the simSeconds no change.If
> it normal?If not , what can I do to set the return ticks of the read() or
> write() function?
>
> Thanks everyone!
>
>
>
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[gem5-users] Re: RISCV Full System with Ruby

[Jason Lowe-Power via gem5-users]

Hi Fu,

You can modify that file to import a Ruby-based cache hierarchy (e.g.,
MESI_Two_Level and MI_Example have been tested). Or, better yet, create
your own run script. `riscv_fs.py` is just an *example* of how to use the
standard library components.

Cheers,
Jason

On Fri, Dec 24, 2021 at 7:57 AM FU zx via gem5-users 
wrote:

> Hello!
>
>
> I just tried your riscv_fs.py in configs/example/gem5_library(I think this
> is where it is in the latest version, am I right?), and it did boot Linux,
> but I can't find how to config the script to enable the ruby cache system,
> the default config is just a classic cache model. Is there any guide to
> enable the ruby cache system in fs mode? Any help would be appreciated.
>
>
>
> Thanks in advance.
>
> Fu
>
>
>
>
>
>
>
>
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[gem5-users] Re: Adding use of an external library

[Jason Lowe-Power via gem5-users]

Hi Elliot,

You may be able to get some inspiration from the code in gem5/ext/*. This
is where we have included external libraries.

Cheers,
Jason

On Fri, Dec 17, 2021 at 6:21 PM Eliot Moss via gem5-users <
gem5-users@gem5.org> wrote:

>
> I have an external library that I would like to link with my gem5 build.
> How
> do I do that?  Also the code I want to compile that will use that library
> needs to include a particular .h file.  How do I work that into the build
> process?
>
> Thanks for tips on how to do this!  Regards - Eliot Moss
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[gem5-users] Re: Deadlock with pthread and DerivO3CPU in SE mode

[Jason Lowe-Power via gem5-users]

Hi Brian,

You can try the patch linked below if you want x86 + multicore + classic.
There is a download button on that page. However, this isn't "officially"
supported.

Some Ruby protocols have been tested with x86 and multiple cores. The
details on the gem5-resources website and/or repo should describe what's
been tested.

Cheers,
Jason

On Thu, Dec 16, 2021 at 10:36 AM Brian Schwedock via gem5-users <
gem5-users@gem5.org> wrote:

> Hi Jason,
>
> Thanks for the response.
>
> I will give full system mode a try. Will x86 + classic cache + multicore
> work with full system mode? Or do I also need to use, e.g., ruby caches?
>
> Thanks,
> Brian
>
> On Thu, Dec 16, 2021 at 9:23 AM Jason Lowe-Power 
> wrote:
>
>> Hi Brian,
>>
>> A few quick thoughts:
>> 1. x86 + classic cache + multicore is not supported. There is a changeset
>> on gerrit (https://gem5-review.googlesource.com/c/public/gem5/+/52303)
>> which may fix this, but it has not been tested widely.
>> 2. SE mode + pthreads will likely not work in all circumstances. The
>> system calls required for pthreads are complex and we may not have
>> implemented them to perfectly match their behavior on Linux
>> 3. Which leads to this: If you want to investigate multicore performance,
>> I would strongly suggest using full system mode. With gem5-resources (
>> https://resources.gem5.org/) it should be straightforward to set up. See
>> also the new gem5 standard library coming in gem5-21.2 (released next week)
>> as well.
>>
>> Cheers,
>> Jason
>>
>> On Wed, Dec 15, 2021 at 7:28 PM Brian Schwedock via gem5-users <
>> gem5-users@gem5.org> wrote:
>>
>>> Hi,
>>>
>>> I'm trying to run a simple multithreaded C++ application in SE mode, but
>>> I seem to be getting deadlock when running with DerivO3CPU. TimingSimpleCPU
>>> does not deadlock. I'm running on the develop branch without modification.
>>>
>>> Here is the configuration I'm running:
>>> ./build/X86/gem5.opt configs/example/se.py
>>> --cmd=/path/to/app --num-cpus=16 --cpu-type=DerivO3CPU --caches --l2cache 
>>> --l1d_size=64kB --l1i_size=16kB --l2_size=4MB --mem-type=DDR3_1600_8x8
>>>
>>> My application spawns 16 pthreads, and the threads perform atomic
>>> arithmetic operations and use pthread barriers. From what I can tell, the
>>> issue is that on one of the barriers only one or two threads are ever woken
>>> up once all threads are ready.
>>>
>>> When running with the above configuration, the simulation just hangs.
>>> When I run with ruby caches, the simulation eventually terminates from the
>>> Sequencer panicking on "Possible Deadlock detected."
>>>
>>> Are pthread barriers not currently supported? I tried using m5threads,
>>> but as per this issue (https://github.com/gem5/m5threads/issues/2), I
>>> can't compile it with my gcc and kernel versions.
>>>
>>> I would greatly appreciate any help with this issue.
>>>
>>> Thanks,
>>> Brian
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[gem5-users] Re: Deadlock with pthread and DerivO3CPU in SE mode

[Jason Lowe-Power via gem5-users]

Hi Brian,

A few quick thoughts:
1. x86 + classic cache + multicore is not supported. There is a changeset
on gerrit (https://gem5-review.googlesource.com/c/public/gem5/+/52303)
which may fix this, but it has not been tested widely.
2. SE mode + pthreads will likely not work in all circumstances. The system
calls required for pthreads are complex and we may not have implemented
them to perfectly match their behavior on Linux
3. Which leads to this: If you want to investigate multicore performance, I
would strongly suggest using full system mode. With gem5-resources (
https://resources.gem5.org/) it should be straightforward to set up. See
also the new gem5 standard library coming in gem5-21.2 (released next week)
as well.

Cheers,
Jason

On Wed, Dec 15, 2021 at 7:28 PM Brian Schwedock via gem5-users <
gem5-users@gem5.org> wrote:

> Hi,
>
> I'm trying to run a simple multithreaded C++ application in SE mode, but I
> seem to be getting deadlock when running with DerivO3CPU. TimingSimpleCPU
> does not deadlock. I'm running on the develop branch without modification.
>
> Here is the configuration I'm running:
> ./build/X86/gem5.opt configs/example/se.py
> --cmd=/path/to/app --num-cpus=16 --cpu-type=DerivO3CPU --caches --l2cache 
> --l1d_size=64kB --l1i_size=16kB --l2_size=4MB --mem-type=DDR3_1600_8x8
>
> My application spawns 16 pthreads, and the threads perform atomic
> arithmetic operations and use pthread barriers. From what I can tell, the
> issue is that on one of the barriers only one or two threads are ever woken
> up once all threads are ready.
>
> When running with the above configuration, the simulation just hangs. When
> I run with ruby caches, the simulation eventually terminates from the
> Sequencer panicking on "Possible Deadlock detected."
>
> Are pthread barriers not currently supported? I tried using m5threads, but
> as per this issue (https://github.com/gem5/m5threads/issues/2), I can't
> compile it with my gcc and kernel versions.
>
> I would greatly appreciate any help with this issue.
>
> Thanks,
> Brian
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[gem5-users] Re: Run Timed Simulation (Stop After Certain Time)

[Jason Lowe-Power via gem5-users]

You can call cpu.scheduleInstStop(, , )

So, you can set an initial instruction limit which will exit from the
simulate() call. Then, you can reset the stats and set a new instruction
limit with scheduleInstStop. Then, call simulate() again. When this second
simulate returns you can dump the stats.

You may or may not be able to do all this from se/fs.py, but it's pretty
straightforward to write your own gem5 runscript.

Cheers,
Jason

On Mon, Dec 6, 2021 at 6:41 PM Abdelrahman S. Hussein <
abdelrahman.sob...@gmail.com> wrote:

> Hi Prof. Jason,
>
> Thanks a lot for your response.
>
> The problem is not that we need to set one instruction limit but set one
> instruction limit, then reset the stats, and then terminate the simulation
> completely after the "total instruction limit". So, these are basically two
> termination points; one for warmup and the other for the actual simulation.
>
> Thanks.
>
> --
>
> *Best,Abdelrahman Hussein*
>
>
> On Mon, Dec 6, 2021 at 8:57 AM Jason Lowe-Power 
> wrote:
>
>> Hi Abdelrahman,
>>
>> I think you have the right approach. Is the simulation not exiting after
>> the warmup_inst instructions?
>>
>> Cheers,
>> Jason
>>
>> On Sat, Dec 4, 2021 at 11:43 PM Abdelrahman S. Hussein via gem5-users <
>> gem5-users@gem5.org> wrote:
>>
>>> Hello,
>>>
>>> I am trying to warm up my gem5 in order to train cache prediction. I am
>>> doing this by running a timed simulation in order to limit the number of
>>> instructions executed (if there is a more direction, that would be
>>> certainly welcomed).
>>>
>>> So, how to do this?
>>>
>>> I tried the following:
>>>
>>> system.setMemCtrl(valid_mem_ctls[args.memory_ctl])
>>> system.cpu.max_insts_any_thread = warmup_inst
>>>
>>> Also, I tried to set the duration desired for the simulation by passing
>>> it as an argument to the m5.simulate().
>>>
>>> Thanks.
>>>
>>> --
>>>
>>> *Best,Abdelrahman Hussein*
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>>
>>
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[gem5-users] Re: Run Timed Simulation (Stop After Certain Time)

[Jason Lowe-Power via gem5-users]

Hi Abdelrahman,

I think you have the right approach. Is the simulation not exiting after
the warmup_inst instructions?

Cheers,
Jason

On Sat, Dec 4, 2021 at 11:43 PM Abdelrahman S. Hussein via gem5-users <
gem5-users@gem5.org> wrote:

> Hello,
>
> I am trying to warm up my gem5 in order to train cache prediction. I am
> doing this by running a timed simulation in order to limit the number of
> instructions executed (if there is a more direction, that would be
> certainly welcomed).
>
> So, how to do this?
>
> I tried the following:
>
> system.setMemCtrl(valid_mem_ctls[args.memory_ctl])
> system.cpu.max_insts_any_thread = warmup_inst
>
> Also, I tried to set the duration desired for the simulation by passing it
> as an argument to the m5.simulate().
>
> Thanks.
>
> --
>
> *Best,Abdelrahman Hussein*
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[gem5-users] Re: fatal when adding a new CPU

[Jason Lowe-Power via gem5-users]

Hi Fengze,

Yeah, there's a lot of complicated and undocumented things you need to do
when initializing a CPU.

Here's a couple of pointers that may help. However, this code was written a
few years ago and is almost 4000 commits behind, so things have probably
changed since then!
Code: https://github.com/darchr/gem5/tree/simple-cpu/src/learning_gem5/part4
Notes:
https://github.com/darchr/gem5/blob/simple-cpu/src/learning_gem5/part4/notes.rst

I am certain that workload stuff has changed since I wrote the above code.
Though, I hope that it can help you get started.

Cheers,
Jason

On Wed, Nov 3, 2021 at 3:19 AM Fengze Yu via gem5-users 
wrote:

> Hi
>
> I was trying to add a new CPU inherit from BaseCPU:
>
> class MY_CPU: public BaseCPU
> {
> public:
>
> MY_CPU(const MY_CPUParams& p);
> ~MY_CPU(){}
> ...
> private:
> ...
> }
>
> but incurs the following running error: fatal: Process system.cpu.workload
> is not associated with any HW contexts!
>
> ...
> warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports`
> warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports`
> warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports`
> warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports`
> warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports`
> Global frequency set at 1 ticks per second
> warn: No dot file generated. Please install pydot to generate the dot file
> and pdf.
> build/RISCV/mem/mem_interface.cc:793: warn: DRAM device capacity (8192
> Mbytes) does not match the address range assigned (512 Mbytes)
> build/RISCV/base/statistics.hh:277: warn: One of the stats is a legacy
> stat. Legacy stat is a stat that does not belong to any statistics::Group.
> Legacy stat is deprecated.
> build/RISCV/arch/riscv/linux/se_workload.cc:60: warn: Unknown operating
> system; assuming Linux.
> build/RISCV/sim/process.cc:290: fatal: Process system.cpu.workload is not
> associated with any HW contexts!
> ...
>
> Did I miss anything essential when creating a new CPU class?
>
>
> Thanks in advance
>
> Fengze
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[gem5-users] Re: RISCV Full System with Ruby

[Jason Lowe-Power via gem5-users]

Hello,

Yes. MI_example and MESI_Two_Level have been tested with the RISC-V board
in the components library. See
https://gem5.googlesource.com/public/gem5/+/refs/heads/develop/configs/example/components-library/riscv_fs.py

I am working on the CHI protocol. I have a WIP changeset that I could
share. The final part I'm working on is getting DMA. That said, since
MI_example and MESI_Two_Level work, there's evidence that any protocol
should work.

Cheers,
Jason

On Tue, Nov 2, 2021 at 3:29 AM Javier Garcia Hernandez via gem5-users <
gem5-users@gem5.org> wrote:

> Hello.
>
> Is Ruby supported on RISCV FS?
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[gem5-users] Re: m5 pesudo

[Jason Lowe-Power via gem5-users]

Hello,

The m5 magic operations (either via magic instructions or addresses) will
work with all CPU models.

Cheers,
Jason

On Sat, Oct 30, 2021 at 8:31 PM Liyichao via gem5-users 
wrote:

> Hi All:
>
>  Does “m5 --addr 0x1001 exit” take effect in the O3 system?
>
>
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[gem5-users] Re: Vector Instructions Support

[Jason Lowe-Power via gem5-users]

Hi Nitesh,

I don't think there's any good documentation. This may help with Arm SVE
support, but it's from a while ago. Things have changed since 2018.
https://community.arm.com/arm-research/b/articles/posts/simulating-the-arm-sve-with-gem5

On Fri, Oct 29, 2021 at 2:27 AM Nitesh Narayana GS 
wrote:

> Hi
>
> Thanks for the information. I will check the code base for that. Do you
> have any suggestions for the documentation regarding it ?
>
>
> Regards
> Nitesh
>
> On Thu, 28 Oct 2021 at 17:53, Jason Lowe-Power 
> wrote:
>
>> Hello,
>>
>> For Arm, gem5 has SVE support and (some/most/all?) of the NEON
>> instructions. For x86, we support most 128-bit SIMD instructions, but very
>> few or no 256-bit or 512-bit SIMD instructions. I have heard of
>> forks/groups that have implemented many of the x86 vector instructions, and
>> I have heard that RISC-V vector extensions have been implemented. However,
>> these implementations have not been made public or have not been pushed
>> upstream.
>>
>> Cheers,
>> Jason
>>
>> On Thu, Oct 28, 2021 at 4:08 AM nitesh--- via gem5-users <
>> gem5-users@gem5.org> wrote:
>>
>>> Hi
>>>
>>> I am working on understanding VPUs and vector instructions, and am a bit
>>> new to the gem5 environment. I aI wanted to know if there is any official
>>> update on the vector instruction support for gem5 x86 and ARM? I see there
>>> are some forked versions available in the community but I am skeptical
>>> about their stability and version. Would like to know if anyone recommends
>>> any such version.
>>>
>>> I also see In this link
>>> https://www.gem5.org/documentation/general_docs/architecture_support/
>>> that gem5 has support for SSE in x86 but see little documentation regarding
>>> that. Also no mention of ARM vector instruction support.
>>>
>>> Sorry if I am wrong regarding the things I have mentioned.
>>>
>>> So any guidance, help, or advice regarding this will be great!!
>>>
>>> Thanks
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>>>
>>
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[gem5-users] Re: Vector Instructions Support

[Jason Lowe-Power via gem5-users]

Hello,

For Arm, gem5 has SVE support and (some/most/all?) of the NEON
instructions. For x86, we support most 128-bit SIMD instructions, but very
few or no 256-bit or 512-bit SIMD instructions. I have heard of
forks/groups that have implemented many of the x86 vector instructions, and
I have heard that RISC-V vector extensions have been implemented. However,
these implementations have not been made public or have not been pushed
upstream.

Cheers,
Jason

On Thu, Oct 28, 2021 at 4:08 AM nitesh--- via gem5-users <
gem5-users@gem5.org> wrote:

> Hi
>
> I am working on understanding VPUs and vector instructions, and am a bit
> new to the gem5 environment. I aI wanted to know if there is any official
> update on the vector instruction support for gem5 x86 and ARM? I see there
> are some forked versions available in the community but I am skeptical
> about their stability and version. Would like to know if anyone recommends
> any such version.
>
> I also see In this link
> https://www.gem5.org/documentation/general_docs/architecture_support/
> that gem5 has support for SSE in x86 but see little documentation regarding
> that. Also no mention of ARM vector instruction support.
>
> Sorry if I am wrong regarding the things I have mentioned.
>
> So any guidance, help, or advice regarding this will be great!!
>
> Thanks
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[gem5-users] Re: How to map elf section to physical memory

[Jason Lowe-Power via gem5-users]

Hi Jose,

This is an interesting question! My quick suggestion would be to "hack" the
loader/page table to skip the mapping portion when loading the elf section.

I don't fully understand exactly what the underlying "problem" is. That
said, we may be able to solve it "correctly" by generally skipping the
mapping during the elf loading if it's already been manually mapped by the
process.map function. This may be useful to upstream if this idea works.

Cheers,
Jason

On Fri, Oct 22, 2021 at 4:30 PM Monsalve, Jose Manuel via gem5-users <
gem5-users@gem5.org> wrote:

> Hi everyone,
>
>
>
> I am working on developing the simulation of a system that contains two
> different regions of memory. One that maps to the cachable system memory
> (including cache hierarchy) but another region that is non-cachable, and
> which goes to a different memory (similar to scratchpad memory for the sake
> of this question). Additionally, in the executing code, I am trying to
> allocate some objects into this scratchpad memory address space from a
> section in the elf file. While running in SE mode. So, for example:
>
>
>
> System Memory address range -> 0x-0 to 0x00FFF
>
> Scratchpad memory address range -> 0x01000 to 0xF
>
>
>
> And in the linker script I place some sections in this region like:
>
>
>
> . = 0x1000
>
> .scratchpad {
>
>/* all symbols */
>
> }
>
>
>
> Then to use the __attribute__((section(“.scratchpad”)) in a given
> definition.
>
>
>
> However, when the loader loads this elf file, the virtual memory is
> assigned correctly, but it is mapped to another physical memory range that
> is different to the physical memory of the SPmem device.
>
>
>
> I know I can use the *.map()* method in the process like this (in python)
>
>
>
> process.map(Addr(args.mem_size),
>
> Addr(args.mem_size),
>
> SPMemorySize,
>
> False)
>
>
>
> This will only work if I don’t use sections in the linker script, and
> instead, manually assign the value of a pointer. (e.g. int **a = (int**)
> 0x1000;)
>
>
>
> But when I run it with the elf sections I get the error:
>
> build/RISCV/mem/page_table.cc:60: panic: panic condition !clobber
> occurred: EmulationPageTable::allocate: addr 0xc000 already mapped
>
>
>
> Because by the moment I reach the second map, the loader has already
> mapped the region before.
>
>
>
> I would appreciate if someone can share nay pointers on how to properly do
> this mapping between virt and physical.
>
>
>
> Thanks!
>
>
>
> Jose M Monsalve Diaz
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[gem5-users] Re: L2 or L3 cache interface

[Jason Lowe-Power via gem5-users]

Hi Fengze,

No, there is no defined interface between different levels of the cache in
Ruby. Ruby is a "black box" in some sense, with input on the CPU side and
output on the memory side. See
https://www.gem5.org/documentation/learning_gem5/part3/MSIintro/ and
https://www.youtube.com/watch?v=XTIrVBb86aM_channel=JasonLowe-Power for
more information.

Cheers,
Jason

On Mon, Oct 25, 2021 at 6:18 AM Fengze Yu via gem5-users <
gem5-users@gem5.org> wrote:

>
> Hi
>
> What is the interface between L1 and L2 cache in Ruby cache coherence
> model? Is there a clear defined interface, similar to the icachePort and
> dcachePort between CPU and memory, between different levels of caches in
> Ruby?
>
>
> Thanks in advance
>
> Fengze Yu
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[gem5-users] Re: Use xbar stat in BaseCPU

[Jason Lowe-Power via gem5-users]

Hi Victor,

It's not super easy to access stats between SimObjects. I would suggest
computing any and all formulas after running the simulation, not during the
simulation loop.

You can either parse the stats.txt or use the new python stats interface (
https://gem5.googlesource.com/public/gem5/+/refs/heads/stable/src/python/m5/stats/gem5stats.py#237)
to access stats from your python run script.

Cheers,
Jason

On Thu, Oct 21, 2021 at 4:12 PM Victor Kariofillis via gem5-users <
gem5-users@gem5.org> wrote:

> Hi,
>
> I have created a new stat of type Formula in the xbar.cc/hh files. There
> I aggregate all the different transDist types. I'd like to use this newly
> created stat to compute another stat in the BaseCPU object. What is the
> best way to have access to it (i.e., allTransactions stat) from BaseCPU? Is
> there any way to make it globally accessible?
>
> Thanks
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[gem5-users] Re: SPEC 2017 Benchmarks: Input Files Not Found

[Jason Lowe-Power via gem5-users]

Hi Reiko,

I would guess that it's a permission issue as well. Maybe, by default, when
booting the image it logs in as a regular user?

What I would do is not pass the rcS script and log in interactively with
the m5term (see util/term). Then, run the commands in the rcS file one at a
time manually to see what's going on.

Cheers,
Jason

On Sat, Oct 16, 2021 at 4:34 PM Reiko Matsuda-dunn via gem5-users <
gem5-users@gem5.org> wrote:

> Hello!
>
> I am trying to run the SPEC 2017 benchmarks with gem5 and have had luck
> with some of them, but many are unable to find their input files. If I
> mount the disk image I'm using, I can actually run these benchmarks
> directly on the disk image as root (they can open their input files).
> However, if I have the exact same command in a .rCs file passed as a script
> to $build/ARM/gem5.opt configs/fs.py, I get these file not found errors.
>
> I'm checking all my paths, but I'm skeptical that that is the issue, as
> some benchmarks consistently run and other specific benchmarks do not.
>
> An example of the full command I'm running is:
>
> $build/ARM/gem5.opt --outdir=run/exchange2_s configs/fs_ARM.py
> --checkpoint-dir=checkpoint/exchange2_s -r 1
> --disk-image=../m5_binaries/disks/gem5.img
> --kernel=../m5_binaries/binaries/vmlinux.arm64
> --script=scripts/exchange2_s.rcS --mem-size=4GB --cpu-type=AtomicSimpleCPU
> --caches --l2cache --l1d_size=32kB --l1i_size=32kB --l2_size=512kB
> --checkpoint-at-end --maxinsts=20
>
> The benchmarks with these errors include: cam4_s, exchange2_s, fotonik_s,
> nab_s, omnetpp_s, pop2_s, roms_s, wrf_s, and x264_s.
>
> Could this possibly be a permissions issue? The input files in question
> have -rw-rw-r-- as their permissions, which seems to me like it should be
> okay.
>
> Any ideas would be appreciated!
> Thanks,
> Reiko
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[gem5-users] Re: Pseudo Instruction - m5_reset_stats() - Body Modification

[Jason Lowe-Power via gem5-users]

I would suggest using DPRINTF instead of cout. It's possible that some
print statements aren't being flushed.

Jason

On Mon, Oct 11, 2021 at 7:16 AM Sampad Mohapatra  wrote:

> Hi Jason,
>
> I have added a std::cout statement to the resetstats()'s body and I am
> calling m5_reset_stats from my GPU benchmarks.
> The GPU kernels are launched right after reset is called. I pipe the
> output of simulations to a file. But, strangely enough
> some outputs show the std::cout statements while others don't. What could
> be the reason ?
>
> Thanks,
> Sampad
>
> On Mon, Oct 4, 2021 at 12:08 PM Jason Lowe-Power 
> wrote:
>
>> Hi Sampad,
>>
>> Here is where m5_reset_stats is implemented in the simulator:
>> https://gem5.googlesource.com/public/gem5/+/refs/heads/stable/src/sim/pseudo_inst.cc#303
>>
>> There are a large number of steps between when the guest code calls
>> m5_reset_stats and when the above function executes, but this should help
>> you start hacking :).
>>
>> Cheers,
>> Jason
>>
>> On Sat, Oct 2, 2021 at 4:05 AM Sampad Mohapatra via gem5-users <
>> gem5-users@gem5.org> wrote:
>>
>>> Hi All,
>>>
>>> I need to set a bool variable in src/cpu/simple/base.(hh|cc) to be true
>>> when m5_reset_stats() is *explicitly *called from some binary executing
>>> on gem5. Using this bool and instruction count, I want to exit the
>>> simulation.
>>>
>>> How can I modify the body (hack) of m5_reset_stats() to call other
>>> functions ? Where is its body defined ?
>>> If not possible, then is there any alternative way to set the bool
>>> variable when m5_reset_stats() is *explicitly* called ?
>>>
>>> Thank You,
>>> Sampad Mohapatra
>>>
>>>
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>>
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[gem5-users] Re: Seg. Fault while "Creating a simple configuration script"

[Jason Lowe-Power via gem5-users]

Hello,

Does the file configs/learning_gem5/part1/simple.py work for you? If so,
then there is probably a small mistake in your configuration script. If
this is the case, can you send your script (maybe off list)? I would like
to understand the problem and improve the error message.

Cheers,
Jason

On Fri, Oct 8, 2021 at 12:35 AM saheed - via gem5-users 
wrote:

> Hello,
>
> I am following the Getting started instructions, I am stuck at the
> beginning!
> "Creating a simple configuration script".
>
> I am using the current stable version of gem5 on a Debian (buster) system.
>
> 1. `build/X86/mem/mem_interface.cc:793: warn: DRAM device capacity (8192
> Mbytes) does not match the address range assigned (512 Mbytes)`
>
>  I managed to fix this by increasing `system.mem_ranges` to 8GB.
> Buried somewhere on the internet is a comment about something defaulting to
> 8GB.
>
> 2. `warn: No dot file generated. Please install pydot to generate the dot
> file and pdf.`
>
>   I have installed this with `sudo apt install python-pydot
> python-pydot-ng graphviz` . Could this be because my system is running in
> server mode (no GUI)?
>
> 3. *The SEG. FAULT:*
> Here is the whole load down, please let me know what I am doing wrong
>
> ~/DEV/comp-arch/gem5$ build/X86/gem5.opt configs/tutorial/simple.py
> gem5 Simulator System.  http://gem5.org
> gem5 is copyrighted software; use the --copyright option for details.
>
> gem5 version 21.1.0.2
> gem5 compiled Oct  8 2021 08:16:42
> gem5 started Oct  8 2021 09:27:49
> gem5 executing on saheed-deb, pid 22197
> command line: build/X86/gem5.opt configs/tutorial/simple.py
>
> Global frequency set at 1 ticks per second
> warn: No dot file generated. Please install pydot to generate the dot file
> and pdf.
> Beginning simulation!
> build/X86/sim/simulate.cc:107: info: Entering event queue @ 0.  Starting
> simulation...
> gem5 has encountered a segmentation fault!
>
> --- BEGIN LIBC BACKTRACE ---
> build/X86/gem5.opt(+0x9275b9)[0x55a3a34815b9]
> build/X86/gem5.opt(+0x9417ff)[0x55a3a349b7ff]
> /lib/x86_64-linux-gnu/libpthread.so.0(+0x12730)[0x7f63c4fbf730]
> build/X86/gem5.opt(+0x986654)[0x55a3a34e0654]
> build/X86/gem5.opt(+0x4b9847)[0x55a3a3013847]
> build/X86/gem5.opt(+0x4b21a5)[0x55a3a300c1a5]
> build/X86/gem5.opt(+0x4b2e18)[0x55a3a300ce18]
> build/X86/gem5.opt(+0x933e75)[0x55a3a348de75]
> build/X86/gem5.opt(+0x95aad1)[0x55a3a34b4ad1]
> build/X86/gem5.opt(+0x95b2a2)[0x55a3a34b52a2]
> build/X86/gem5.opt(+0xe7d3ce)[0x55a3a39d73ce]
> build/X86/gem5.opt(+0x39276d)[0x55a3a2eec76d]
>
> /lib/x86_64-linux-gnu/libpython3.7m.so.1.0(PyCFunction_Call+0xfb)[0x7f63c5243b5b]
>
> /lib/x86_64-linux-gnu/libpython3.7m.so.1.0(_PyEval_EvalFrameDefault+0x78e0)[0x7f63c5044700]
>
> /lib/x86_64-linux-gnu/libpython3.7m.so.1.0(_PyEval_EvalCodeWithName+0x996)[0x7f63c516c1e6]
>
> /lib/x86_64-linux-gnu/libpython3.7m.so.1.0(_PyFunction_FastCallKeywords+0x93)[0x7f63c5243123]
>
> /lib/x86_64-linux-gnu/libpython3.7m.so.1.0(_PyEval_EvalFrameDefault+0x7b95)[0x7f63c50449b5]
>
> /lib/x86_64-linux-gnu/libpython3.7m.so.1.0(_PyEval_EvalCodeWithName+0x996)[0x7f63c516c1e6]
>
> /lib/x86_64-linux-gnu/libpython3.7m.so.1.0(PyEval_EvalCodeEx+0x3e)[0x7f63c516c46e]
>
> /lib/x86_64-linux-gnu/libpython3.7m.so.1.0(PyEval_EvalCode+0x1b)[0x7f63c516d23b]
> /lib/x86_64-linux-gnu/libpython3.7m.so.1.0(+0x1a2bdd)[0x7f63c5170bdd]
>
> /lib/x86_64-linux-gnu/libpython3.7m.so.1.0(_PyMethodDef_RawFastCallKeywords+0x2a5)[0x7f63c5242c75]
>
> /lib/x86_64-linux-gnu/libpython3.7m.so.1.0(_PyCFunction_FastCallKeywords+0x25)[0x7f63c5243a05]
>
> /lib/x86_64-linux-gnu/libpython3.7m.so.1.0(_PyEval_EvalFrameDefault+0x8bde)[0x7f63c50459fe]
>
> /lib/x86_64-linux-gnu/libpython3.7m.so.1.0(_PyEval_EvalCodeWithName+0x996)[0x7f63c516c1e6]
>
> /lib/x86_64-linux-gnu/libpython3.7m.so.1.0(_PyFunction_FastCallKeywords+0x93)[0x7f63c5243123]
>
> /lib/x86_64-linux-gnu/libpython3.7m.so.1.0(_PyEval_EvalFrameDefault+0x7b95)[0x7f63c50449b5]
>
> /lib/x86_64-linux-gnu/libpython3.7m.so.1.0(_PyEval_EvalCodeWithName+0x996)[0x7f63c516c1e6]
>
> /lib/x86_64-linux-gnu/libpython3.7m.so.1.0(PyEval_EvalCodeEx+0x3e)[0x7f63c516c46e]
>
> /lib/x86_64-linux-gnu/libpython3.7m.so.1.0(PyEval_EvalCode+0x1b)[0x7f63c516d23b]
>
> /lib/x86_64-linux-gnu/libpython3.7m.so.1.0(PyRun_StringFlags+0x8b)[0x7f63c513afeb]
> build/X86/gem5.opt(+0x93fa1f)[0x55a3a3499a1f]
> --- END LIBC BACKTRACE ---
> Segmentation fault
>
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[gem5-users] Re: Porting a configuration file from gem5 v20 to gem5 v21

[Jason Lowe-Power via gem5-users]

Hi Ali,

Is your guest code 32-bit Arm? If so, I think this could be the problem in
SE mode: https://gem5.atlassian.net/browse/GEM5-1074

Cheers,
Jason

On Tue, Oct 5, 2021 at 7:45 AM Ali Ghandour via gem5-users <
gem5-users@gem5.org> wrote:

> In FS mode, full errror stack below:
>
> Traceback (most recent call last):
>   File "", line 1, in 
>   File "build/ARM/python/m5/main.py", line 455, in main
>   File "./RPIv4.py", line 535, in 
> main()
>   File "./RPIv4.py", line 512, in main
> root.system = systemCreate(args)
>   File "./RPIv4.py", line 297, in systemCreate
> system = RPISystemCreate(ArmSystem, args, mode)
>   File "./RPIv4.py", line 182, in RPISystemCreate
> return RPISystem(args, mode)
>   File "./RPIv4.py", line 127, in __init__
> self.configMem(args)
>   File "./RPIv4.py", line 158, in configMem
> self.cpu_cluster.connectDirect(self.membus)
>   File
> "/home/ali/Desktop/spirals/reproduce-spectre-gem5/gem5/./ARMv8A_Cortex_A72.py",
> line 325, in connectDirect
> cpu.dtb.walker.port = bus.slave
>   File "build/ARM/python/m5/SimObject.py", line 1416, in __getattr__
> AttributeError: object 'ARM_A72_TLB_L1D' has no attribute 'walker'
>   (C++ object is not yet constructed, so wrapped C++ methods are
> unavailable.)
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[gem5-users] Re: Pseudo Instruction - m5_reset_stats() - Body Modification

[Jason Lowe-Power via gem5-users]

Hi Sampad,

Here is where m5_reset_stats is implemented in the simulator:
https://gem5.googlesource.com/public/gem5/+/refs/heads/stable/src/sim/pseudo_inst.cc#303

There are a large number of steps between when the guest code calls
m5_reset_stats and when the above function executes, but this should help
you start hacking :).

Cheers,
Jason

On Sat, Oct 2, 2021 at 4:05 AM Sampad Mohapatra via gem5-users <
gem5-users@gem5.org> wrote:

> Hi All,
>
> I need to set a bool variable in src/cpu/simple/base.(hh|cc) to be true
> when m5_reset_stats() is *explicitly *called from some binary executing
> on gem5. Using this bool and instruction count, I want to exit the
> simulation.
>
> How can I modify the body (hack) of m5_reset_stats() to call other
> functions ? Where is its body defined ?
> If not possible, then is there any alternative way to set the bool
> variable when m5_reset_stats() is *explicitly* called ?
>
> Thank You,
> Sampad Mohapatra
>
>
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[gem5-users] Re: Get Size of Stack and Heap

[Jason Lowe-Power via gem5-users]

Hi Ange,

If you're using SE mode, you may be able to augment the allocation code to
track the heap size. E.g.,
https://gem5.googlesource.com/public/gem5/+/refs/heads/stable/src/sim/mem_state.cc#108

In fact, the MemState object tracks both the stack and the heap, so you can
get a lot of information from that. Again, this assumes you're using SE
mode.

If you're using FS mode, it will be a bit more complicated. You're on the
right track with the readArchInReg. I'm not sure exactly how Arm tracks the
heap, but I would dig into the remote GDB implementation to see if there
are any hints in that code.

Cheers,
Jason

On Thu, Sep 23, 2021 at 9:46 AM Ange via gem5-users 
wrote:

> Hi all,
>
> I am trying to keep track of the size of the stack and heap while
> executing a binary, and at the moment, I can get the address of the stack
> pointer using this line of code
> cpu->readArchIntReg(ArmISA::INTREG_SP ,tid).
> I am also trying to read the frame pointer (FP), but I am having trouble
> getting the address for it
> because it always prints zero as its address, and I am using Register 11
> for the FP (cpu->readArchIntReg(ArmISA::INTREG_R11) ).
> Am I doing something wrong, or is there a better way to get the stack
> size?  and also the heap size with its addresses?
>
> I saw that someone asked a similar question a while back on this forum,
> but it was not fully answered.
> Here is the link
> https://www.mail-archive.com/gem5-users@gem5.org/msg04154.html
>
> I need help!
>
> Ange
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[gem5-users] Re: gem5art, FS mode, panic: PerfKvmCounter (perf_event_paranoid is set to -1)

[Jason Lowe-Power via gem5-users]

Yeah. I would suggest working on a native linux machine if you're going to
use KVM. If you're not using KVM, then WSL *should* (no promises ;)) work
OK.

Cheers,
Jason

On Thu, Sep 23, 2021 at 3:21 PM Reiko Matsuda-dunn <
reiko.matsudad...@colorado.edu> wrote:

> Thanks for the resources! Seems like quite a can of worms.It's almost
> looking like it could be easier to partition a computer for Linux and start
> over. Would you recommend that as an alternative?
>
> All th
>
> On Thu, Sep 23, 2021 at 1:36 PM Jason Lowe-Power via gem5-users <
> gem5-users@gem5.org> wrote:
>
>> Hi Reiko,
>>
>> The KVM CPU requires that the host platform supports KVM. Given that
>> you're using WSL, this means that you need to have nested virtualization
>> enabled and implemented on your WSL kernel.
>> https://www.reddit.com/r/bashonubuntuonwindows/comments/ldbyxa/what_is_the_current_state_of_kvm_acceleration_on/
>> has more information.
>>
>> We can try to help you with this, but currently we only support KVM on
>> native Linux hosts.
>>
>> Cheers,
>> Jason
>>
>> On Thu, Sep 23, 2021 at 11:36 AM Reiko Matsuda-dunn via gem5-users <
>> gem5-users@gem5.org> wrote:
>>
>>> Hello,
>>>
>>> I'm trying to troubleshoot this error (output below).  I've looked at
>>> prior posts in this mailing list and was able to change perf_event_paranoid
>>> to -1 ( I confirmed this with $cat /proc/sys/kernel/perf_event_paranoid,
>>> which returns -1, although it resets to 2 every time I reboot). It looks
>>> like there's some mention of a patch, but I haven't been able to find that
>>> patch. If anyone could point me to that, or offer other suggestions I would
>>> be grateful!
>>>
>>> I'm using gem5 21, WSL2, and have otherwise follower the tutorial here:
>>> https://www.gem5.org/documentation/gem5art/tutorials/spec-tutorial
>>> <https://secure-web.cisco.com/17IBO0xQxkZZIebcGCBpl1G0BsdiJYaESwCqShOyCJRixJFvPEMpbaePLfLril03_Qv4GGBoSf1-s_RSxDFuTNEd3nZ6jb0A1cTSgSVFF0TlW1yWTMajw2VxDcgoQK9MBNdDMxXseHmenbOhFoHzv2_nSqldKvC5u8wj1QXxh6AWAgT-lqcyDlX3wNkRQ-RubhrlVql0h1nLr5X3xLcaS9VTm2VvIJRRkiCZ9AUQeNGn0Tw2BWM1jWjW9qSghZtSB-ir8AP83Di1pPW25Q2ALWnuR-YoVfQ9JL4eL6Aql49G8VUkDU4LtTjLHprwIYfe7xfz-J2mBNwAs6Cy_qgF8Z7M1c6GbEc_4GBF_QUvdVYZhz4L46EEpidbJb2txcdtl4NghPNs9ua1gBj5wynZ2j1GynRoxrrc_Y_sJnfR_xMQxGI9EcqCfe9zm2-St2Zq3clFno40v_7K-s8JTR5a8GA/https%3A%2F%2Fwww.gem5.org%2Fdocumentation%2Fgem5art%2Ftutorials%2Fspec-tutorial>
>>>
>>> My launch_spec2017_experiment.py has been modified slightly for the
>>> paths and gem5 version.
>>>
>>> Thanks for all your help,
>>> Reiko
>>>
>>> build/X86/mem/mem_interface.cc:791: warn:
>>> DRAM device capacity (32768 Mbytes) does not match the address range 
>>> assigned (1024 Mbytes)
>>> build/X86/mem/mem_interface.cc:791: warn:
>>> DRAM device capacity (32768 Mbytes) does not match the address range 
>>> assigned (1024 Mbytes)
>>> build/X86/mem/mem_interface.cc:791: warn:
>>> DRAM device capacity (32768 Mbytes) does not match the address range 
>>> assigned (1024 Mbytes)
>>> build/X86/mem/mem_interface.cc:791: warn:
>>> DRAM device capacity (32768 Mbytes) does not match the address range 
>>> assigned (1024 Mbytes)
>>> build/X86/mem/mem_interface.cc:791: warn:
>>> DRAM device capacity (32768 Mbytes) does not match the address range 
>>> assigned (1024 Mbytes)
>>> build/X86/mem/mem_interface.cc:791: warn:
>>> DRAM device capacity (32768 Mbytes) does not match the address range 
>>> assigned (1024 Mbytes)
>>> build/X86/mem/mem_interface.cc:791: warn:
>>> DRAM device capacity (32768 Mbytes) does not match the address range 
>>> assigned (1024 Mbytes)
>>> build/X86/mem/mem_interface.cc:791: warn:
>>> DRAM device capacity (32768 Mbytes) does not match the address range 
>>> assigned (1024 Mbytes)
>>> build/X86/mem/mem_interface.cc:791: warn:
>>> DRAM device capacity (32768 Mbytes) does not match the address range 
>>> assigned (128 Mbytes)
>>> build/X86/sim/kernel_workload.cc:46: info: kernel located at:
>>> vmlinux-4.19.83
>>> build/X86/dev/serial/terminal.cc:170: warn:
>>> Sockets disabled, not accepting terminal connections
>>> build/X86/base/remote_gdb.cc:377: warn:
>>> Sockets disabled, not accepting gdb connections
>>> build/X86/mem/coherent_xbar.cc:140: warn:
>>> CoherentXBar system.cpu.mmucache.mmubus has no snooping ports attached!
>>> build/X86/dev/intel_8254_timer.cc:125: warn:
>&g

[gem5-users] Re: gem5art, FS mode, panic: PerfKvmCounter (perf_event_paranoid is set to -1)

[Jason Lowe-Power via gem5-users]

Hi Reiko,

The KVM CPU requires that the host platform supports KVM. Given that you're
using WSL, this means that you need to have nested virtualization enabled
and implemented on your WSL kernel.
https://www.reddit.com/r/bashonubuntuonwindows/comments/ldbyxa/what_is_the_current_state_of_kvm_acceleration_on/
has more information.

We can try to help you with this, but currently we only support KVM on
native Linux hosts.

Cheers,
Jason

On Thu, Sep 23, 2021 at 11:36 AM Reiko Matsuda-dunn via gem5-users <
gem5-users@gem5.org> wrote:

> Hello,
>
> I'm trying to troubleshoot this error (output below).  I've looked at
> prior posts in this mailing list and was able to change perf_event_paranoid
> to -1 ( I confirmed this with $cat /proc/sys/kernel/perf_event_paranoid,
> which returns -1, although it resets to 2 every time I reboot). It looks
> like there's some mention of a patch, but I haven't been able to find that
> patch. If anyone could point me to that, or offer other suggestions I would
> be grateful!
>
> I'm using gem5 21, WSL2, and have otherwise follower the tutorial here:
> https://www.gem5.org/documentation/gem5art/tutorials/spec-tutorial
> My launch_spec2017_experiment.py has been modified slightly for the paths
> and gem5 version.
>
> Thanks for all your help,
> Reiko
>
> build/X86/mem/mem_interface.cc:791: warn:
> DRAM device capacity (32768 Mbytes) does not match the address range assigned 
> (1024 Mbytes)
> build/X86/mem/mem_interface.cc:791: warn:
> DRAM device capacity (32768 Mbytes) does not match the address range assigned 
> (1024 Mbytes)
> build/X86/mem/mem_interface.cc:791: warn:
> DRAM device capacity (32768 Mbytes) does not match the address range assigned 
> (1024 Mbytes)
> build/X86/mem/mem_interface.cc:791: warn:
> DRAM device capacity (32768 Mbytes) does not match the address range assigned 
> (1024 Mbytes)
> build/X86/mem/mem_interface.cc:791: warn:
> DRAM device capacity (32768 Mbytes) does not match the address range assigned 
> (1024 Mbytes)
> build/X86/mem/mem_interface.cc:791: warn:
> DRAM device capacity (32768 Mbytes) does not match the address range assigned 
> (1024 Mbytes)
> build/X86/mem/mem_interface.cc:791: warn:
> DRAM device capacity (32768 Mbytes) does not match the address range assigned 
> (1024 Mbytes)
> build/X86/mem/mem_interface.cc:791: warn:
> DRAM device capacity (32768 Mbytes) does not match the address range assigned 
> (1024 Mbytes)
> build/X86/mem/mem_interface.cc:791: warn:
> DRAM device capacity (32768 Mbytes) does not match the address range assigned 
> (128 Mbytes)
> build/X86/sim/kernel_workload.cc:46: info: kernel located at:
> vmlinux-4.19.83
> build/X86/dev/serial/terminal.cc:170: warn:
> Sockets disabled, not accepting terminal connections
> build/X86/base/remote_gdb.cc:377: warn:
> Sockets disabled, not accepting gdb connections
> build/X86/mem/coherent_xbar.cc:140: warn:
> CoherentXBar system.cpu.mmucache.mmubus has no snooping ports attached!
> build/X86/dev/intel_8254_timer.cc:125: warn:
> Reading current count from inactive timer.
> build/X86/cpu/kvm/base.cc:152: info: KVM:
> Coalesced MMIO disabled by config.
> build/X86/arch/x86/cpuid.cc:180: warn: x86 cpuid family 0x:
> unimplemented function 2
> build/X86/arch/x86/cpuid.cc:180: warn: x86 cpuid family 0x:
> unimplemented function 3
> build/X86/arch/x86/cpuid.cc:180: warn: x86 cpuid family 0x:
> unimplemented function 4
> build/X86/arch/x86/cpuid.cc:180: warn: x86 cpuid family 0x:
> unimplemented function 5
> build/X86/arch/x86/cpuid.cc:180: warn: x86 cpuid family 0x:
> unimplemented function 6
> build/X86/arch/x86/cpuid.cc:180: warn: x86 cpuid family 0x:
> unimplemented function 8
> build/X86/cpu/kvm/base.cc:152: info: KVM:
> Coalesced MMIO disabled by config.
> build/X86/arch/x86/cpuid.cc:180: warn: x86 cpuid family 0x:
> unimplemented function 2
> build/X86/arch/x86/cpuid.cc:180: warn: x86 cpuid family 0x:
> unimplemented function 3
> build/X86/arch/x86/cpuid.cc:180: warn: x86 cpuid family 0x:
> unimplemented function 4
> build/X86/arch/x86/cpuid.cc:180: warn: x86 cpuid family 0x:
> unimplemented function 5
> build/X86/arch/x86/cpuid.cc:180: warn: x86 cpuid family 0x:
> unimplemented function 6
> build/X86/arch/x86/cpuid.cc:180: warn: x86 cpuid family 0x:
> unimplemented function 8
> build/X86/sim/simulate.cc:107: info:
> Entering event queue @ 0.  Starting simulation...
> build/X86/cpu/kvm/perfevent.cc:183: panic:
> PerfKvmCounter::attach failed (2)
> Memory Usage: 8738772 KBytes
> build/X86/cpu/kvm/perfevent.cc:183: panic:
> PerfKvmCounter::attach failed (2)
> Memory Usage: 8738772 KBytes
> Program aborted at tick 0
> ___
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[gem5-users] Re: Problems with Deprecated names are not supported by the compiler

[Jason Lowe-Power via gem5-users]

Hi Xihui,

The error is "died with "

I would guess you're out of memory or trying to compile too many files at
once. But, it could be many different problems. If it's an issue with
dependencies or your host, you can always use our docker images:
https://www.gem5.org/documentation/general_docs/building#:~:text=dev%20pkg-config-,Docker,-For%20users%20struggling

Cheers,
Jason

On Thu, Sep 23, 2021 at 1:01 AM Xihui Yuan via gem5-users <
gem5-users@gem5.org> wrote:

> Hi Jason,
>
>   Thanks for your help.
>   But there are lots of errors in the first time to build gem5.
>
> scons: *** [build/X86/mem/ruby/protocol/DMA_Controller.py.cc]
> CalledProcessError : Command '['/home/xihui/下载/gem5/build/X86/marshal',
> 'build/X86/mem/ruby/protocol/DMA_Controller.py']' died with
> .
> Traceback (most recent call last):
>   File "/usr/lib/scons/SCons/Action.py", line 1209, in execute
> result = self.execfunction(target=target, source=rsources, env=env)
>   File "/home/xihui/下载/gem5/build/X86/SConscript", line 1293, in
> embedPyFile
> marshalled = subprocess.check_output(
>   File "/usr/lib/python3.8/subprocess.py", line 415, in check_output
> return run(*popenargs, stdout=PIPE, timeout=timeout, check=True,
>   File "/usr/lib/python3.8/subprocess.py", line 516, in run
> raise CalledProcessError(retcode, process.args,
> subprocess.CalledProcessError: Command
> '['/home/xihui/下载/gem5/build/X86/marshal',
> 'build/X86/mem/ruby/protocol/DMA_Controller.py']' died with
> .
> scons: building terminated because of errors.
>
> Do you have any opinion or suggestion?
>
>
> Regards,
> Xihui
> ___
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> %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
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