Can you try to figure it out yourself? All this stuff is mostly handled in
python in configs/common/Simulate.py (or something; I'm on my phone so its
not easy to check). If it used to work, you can look on the repository to
see what if anything has changed lately. If you run into more detailed
On Mon, Jun 6, 2011 at 10:45 AM, Nilay Vaish ni...@cs.wisc.edu wrote:
On Mon, 6 Jun 2011, biswabandan panda wrote:
blackscholes
On Mon, Jun 6, 2011 at 8:37 PM, Nilay Vaish ni...@cs.wisc.edu wrote:
On Mon, 6 Jun 2011, biswabandan panda wrote:
@nilay i downloaded the latest dev one and
Actually I believe this is a somewhat pervasive problem in the slides,
where latex has automatically substituted a single dash for the --
option prefix... I noticed this myself during the tutorial.
I assume there's a way to escape these prefixes to avoid this
problem... we probably need someone
As part of our continued transition from m5 and GEMS to gem5, the URLs
for HTTP access to our repositories have changed from m5 and m5-stable
to gem5 and gem5-stable. The full URLs for these repositories are
now:
http://repo.gem5.org/gem5
http://repo.gem5.org/gem5-stable
If you had previously
to mention, I'm using the m5threads lib.
I think the discrepancy might be caused by the threads syncing mechanism.
As soon as I discover the cause, I'll report here.
On Thu, Jun 2, 2011 at 11:04 AM, Steve Reinhardt ste...@gmail.com wrote:
Depending on your ISA, instructions that miss in the TLB
It indicates that the requester needs an exclusive copy of the block,
typically because it's a write miss.
Steve
On Sat, Jun 4, 2011 at 2:19 AM, Keitarou Oka o...@soc.ait.kyushu-u.ac.jp
wrote:
Dear M5,
I can't understand what needsExclusive stand for,which is function in
src/mem/packet.hh.
, 2011 at 12:46 PM, Steve Reinhardt ste...@gmail.com wrote:
Yes, it's almost impossible to get completely identical behavior without
running a completely identical system. Even making the cache larger will
make the program run faster in some phases, which will change where timer
interrupts happen
Unless there's a real need to capture OS behavior, you're probably
better off using ALPHA_SE. AFAIK, SPEC CPU benchmarks don't have a
lot of OS activity.
Steve
On Tue, May 24, 2011 at 12:36 PM, Alex Edwards afedw...@ucla.edu wrote:
Hey Everyone,
I am running m5 in ALPHA_FS mode and I am
I would say that if the changes to get gem5 to compile with LLVM are modest
and reasonable we should include them even if they don't provide any
additional benefit.
I'd also say that compiling benchmarks with LLVM and compiling gem5 itself
with LLVM are two different topics that involve very
Hi Tim,
Brad's on vacation, so I'll try and answer...
If you're completely sure that it's the same PC value in both traces and the
error is just in the symbol table, then it makes sense that you'd be running
into trouble with trying to skip functions that aren't really there. AFAIK,
See the m5threads package (http://repo.m5sim.org/m5threads) for pthreads
support in SE mode. Note that it's not supported on all ISAs.
Steve
2011/5/12 xuewen zhou zhouxuewen1...@gmail.com
Hello all：
Now I have one question that if I running m5 in SE mode with
multicore，does it support
Is there a wiki? Or is that your question?
Steve
On Tue, May 10, 2011 at 9:19 AM, Richard Strong rstr...@cs.ucsd.edu wrote:
Hi all,
I am trying to find out more about m5threads and whether it is possible to
simulate parsec with the ALPHA-ISA. I see bits and pieces of emails that ask
how
On Thu, May 12, 2011 at 11:40 AM, nathan binkert n...@binkert.org wrote:
Why are the kernel symbols stored in the m5 checkpoints?
Because the kernel is saved in the checkpoint memory. We could just
extract the symbols from the provided binary a second time, but it
just seemed safer this
On Thu, May 12, 2011 at 1:24 PM, nathan binkert n...@binkert.org wrote:
I've wondered about this too, and assumed it was so you didn't need to
provide the kernel binary when restarting from a checkpoint. It does
seem
like a lot of state to save.
Compared to memory?
Does this really
There is one known problem with unserializing into a system with switch_cpus
defined, that I have an uncommitted patch for here:
http://reviews.m5sim.org/r/608
Based on your description I don't think this is what you're seeing, but I
thought I'd throw it out there in case I'm wrong, or you're
Do you have this problem with the tip revision of the m5 repository? There
have been several other patches applied after the one you list, though I
don't know if any of them would address this problem. If you are seeing it
in a clean copy of the tip, then it's clearly a bug. Otherwise, it's
These tests depend on the eio code in the 'encumbered' package, so
they'll fail if you don't download it and compile it in. You really
don't need that package though, so it's easiest just to ignore these
test failures.
Steve
On Fri, Apr 15, 2011 at 9:43 AM, Patrick plafr...@gmail.com wrote:
is there. Have you figured out a way of solving
the problem?
Thanks,
Leonard
On Wed, Mar 2, 2011 at 9:32 AM, Steve Reinhardt ste...@gmail.com wrote:
FYI, I finally got around to reproducing this, and I think I see what the
problem is. Unfortunately I don't see a really trivial fix, but I've
In theory, these should all work, though as Ali said things will break
if you take a checkpoint in a system with caches because the caches
will likely have dirty memory blocks that don't get saved. So since
O3 doesn't work without caches, in practice you can't create a
checkpoint from it. But
SE mode has a page table and TLBs, so it shouldn't be too hard to put
per-page uncacheable bits in there that are handled the same as in FS
mode. The page table structure is defined in src/mem/page_table.*.
At runtime it's managed via the Process class, in src/sim/process.*.
Steve
On Thu, Mar
I just discovered that there's a small wrinkle here... it turns out that
scons doesn't use optparse to figure out what's a target and what's not, but
instead just ignores things on the command line that start with '-' or
contain an '='. So
scons --default FOO build/BAR/m5.debug
doesn't work
Hi Stijn,
I'm confused about what code you're looking at; in simulate.py, I see:
# Restore checkpoint (if any)
if ckpt_dir:
ckpt = internal.core.getCheckpoint(ckpt_dir)
internal.core.unserializeGlobals(ckpt);
for obj in root.descendants(): obj.loadState(ckpt)
Can you clarify what you're seeing? CPUs don't have cache stats, so your
question doesn't make sense to me.
Steve
On Mon, Mar 7, 2011 at 5:36 PM, Adwait Jog adwait...@gmail.com wrote:
Hi All:
I am running PARSEC Benchmarks on M5. I am interested in getting cache
stats and IPC Values. When
Once a block is invalidated the cache doesn't care what the tag is. You'd
have to modify the writeback miss code to detect the case where there's an
invalid block in the set that has a tag match.
(Assuming you're talking about the traditional m5 caches and not Ruby.)
Steve
On Mon, Mar 7, 2011
On Tue, Mar 8, 2011 at 10:07 AM, Adam Jacobvitz a...@duke.edu wrote:
Two Questions:
1) How are blocks written into the L1 or L2 cache when there is no block to
replace? I see this thing called a tempBlock but I can't seem to find the
code that writes it into the cache...
It isn't written
in the caches for
which there is no replacement event.
Thanks,
Adam
On 3/8/2011 6:42 PM, Steve Reinhardt wrote:
On Tue, Mar 8, 2011 at 10:07 AM, Adam Jacobvitz a...@duke.edu mailto:
a...@duke.edu wrote:
Two Questions:
1) How are blocks written into the L1 or L2 cache when
time any block ever is being inserted into the set)? Does it just return a
hex value corresponding to whatever garbage value was in that memory
location?
By the way, thanks for the help, and thanks for making M5!
Adam
On 3/8/2011 7:18 PM, Steve Reinhardt wrote:
findVictim() will return
One way to do this is to expose the function via swig and call it from
python in the switchCpus() function in python/m5/simulate.py.
On Tue, Mar 8, 2011 at 1:48 PM, Adwait Jog adwait...@gmail.com wrote:
Hi,
Is there any way to know (at run time) the Tick at which cpu will switch to
the
FYI, I finally got around to reproducing this, and I think I see what the
problem is. Unfortunately I don't see a really trivial fix, but I've got
some ideas I'll work on to see if I can take care of it.
Steve
On Fri, Feb 18, 2011 at 5:21 AM, Steve Reinhardt ste...@gmail.com wrote:
BTW
Historically there have been a couple of problems with this:
- it's hard to guarantee that the arrays are sized properly (e.g.,
originally a cache didn't know how many CPUs/threads it was connected to)
- some packets (like writebacks) don't have an associated ID
Lisa did a bunch of work to clean
) (orphan) (orphan) (orphan) (orphan)
(orphan) (orphan)
On Thu, Feb 17, 2011 at 5:45 AM, Steve Reinhardt ste...@gmail.comwrote:
Hi Rick,
I'm a little confused by your statement there is no recursion to add the
children of params. Being param value and being a child are separate
things
Hi Rick,
I'm a little confused by your statement there is no recursion to add the
children of params. Being param value and being a child are separate
things, because an object A can be a param of many other objects but can
only be the child of one other object. The only relationship between
m5 will compile under cygwin but it does not run very well and is almost
impossible to debug. If you really need to run on a windows machine, the
best route is to install linux in a virtual machine and run it in that (free
vms like virtualbox and vmware player work just fine).
Steve
On Fri, Feb
Actually the cache will block as soon as the MSHRs are full; see
allocateBufferInternal() in src/mem/cache/base.hh:
if (mq-isFull()) {
setBlocked((BlockedCause)mq-index);
}
Steve
On Tue, Feb 1, 2011 at 8:45 PM, Sheng Li sheng@gmail.com wrote:
Hi Guys,
I am a
There is no prefetch buffer... what code makes you think that there is?
On Mon, Jan 31, 2011 at 5:08 AM, biswabandan panda biswa@gmail.comwrote:
Hi all,
It seem the prefetched blockse were not transferred to upper
level cache. what i understood from the code in prefetch folder
the
response returns, the data is put in the cache, again just like any other
request.
Steve
On Mon, Jan 31, 2011 at 6:36 AM, biswabandan panda biswa@gmail.comwrote:
i mean to say prefetch queue
On Mon, Jan 31, 2011 at 7:56 PM, Steve Reinhardt ste...@gmail.com wrote:
There is no prefetch buffer
again for your time
On Mon, Jan 31, 2011 at 8:37 PM, Steve Reinhardt ste...@gmail.com wrote:
The prefetch queue is just a queue of addresses generated by the
prefetcher; when the cache has an opportunity it will pull an address of
that queue and generate a prefetch request for it. While
I don't know of any reason offhand that you wouldn't be seeing prefetches
from the icache... traceflags and gdb are your friends, you'll have to dive
in and find more clues. Let us know.
Steve
On Mon, Jan 24, 2011 at 11:41 PM, biswabandan panda biswa@gmail.comwrote:
Hi all,
i
Good questions... anyone from Wisconsin want to respond? Brad is on
vacation so he won't be able to help anytime soon.
Steve
On Mon, Jan 24, 2011 at 8:38 PM, Joseph Pusdesris jo...@umich.edu wrote:
I am having difficulty understanding Crossbar.py. Is it capable of
multiple simultaneous
for the OS to make that much
difference?
These statistics are taken after the benchmarks have started.
Thanks!
Steve
On Tue, Jan 25, 2011 at 12:00 AM, Steve Reinhardt ste...@gmail.comwrote:
OK, sorry for the confusion; since you were running a Parsec benchmark I
assumed the numbers were processor
See http://m5sim.org/wiki/index.php/Memory_System#Access_Types.
Functional accesses get instantaneously broadcast through the whole system,
which is why every cache reports that it is processing the access at the
same tick.
Steve
On Mon, Jan 24, 2011 at 1:33 AM, biswabandan panda
Nothing you've printed looks unusual. Try turning on some trace flags (
http://m5sim.org/wiki/index.php/Debugging_M5) to see what's happening,
Steve
http://m5sim.org/wiki/index.php/Debugging_M5
On Sun, Jan 23, 2011 at 7:04 PM, Yingying Tian yt...@cs.utsa.edu wrote:
Hi All,
I have compiled
Yes, it's been discussed on this list before.
In reality: possible
In M5: not supported
On Sun, Jan 23, 2011 at 3:14 AM, Gabe Black gbl...@eecs.umich.edu wrote:
I don't know about in general, but I'm pretty sure you can't in M5. I
think it has to do with the coherence protocol. Other people
24, 2011 at 8:50 AM, Yingying Tian yt...@cs.utsa.edu wrote:
Thank you, Steve. But I think if everything ran correctly, there should be
some statistics in stats.txt, right?
Thanks,
Yingying
On Mon, Jan 24, 2011 at 9:09 AM, Steve Reinhardt ste...@gmail.com wrote:
Nothing you've printed
With a multiprocessor, seemingly small changes in configuration can have a
significant impact if it changes the order in which threads grab a lock, or
something like that. So in particular, for the stats you have below, it
seems likely that there's some serialized computation going on that
That is pretty freaky... you get the warnings by default, I think, but you
can try the 'Config' traceflag. Feel free to add more DPRINTFs if that
doesn't help. The unserialization is driven by the objects, so the question
is why the PageTable in the Process object unserializes correctly in one
100,000 each time)
On Mon, Jan 24, 2011 at 7:14 PM, Steve Reinhardt ste...@gmail.com wrote:
With a multiprocessor, seemingly small changes in configuration can have a
significant impact if it changes the order in which threads grab a lock, or
something like that. So in particular, for the stats you
Strange, I've never had that problem. It's really a gdb issue, I'd say, but
one way to get around it is to go into src/mem/cache/config/cache.hh and
comment out everything except the USE_CACHE_LRU line so those other caches
don't get compiled in.
Steve
2011/1/7 Shinya Hashiguchi
In the classic (non-Ruby) M5 memory system, request packets are routed based
on address, not bus ID. The bus IDs are only used internally to route
responses back to requestors.
You may want to use Ruby instead since that supports a point-to-point
network interconnect rather than busses.
Steve
Try running under gdb to see where the segmentation fault happens.
On Tue, Jan 4, 2011 at 11:31 PM, sunitha p suniac...@gmail.com wrote:
Hi all,
I am trying to assign different workloads to cpus . am using splash
benchmarks. I have gonr through the mailing list and accordingly
The code
] *代表
*Steve Reinhardt
*发送时间:* 2010年12月22日星期三 7:48
*收件人:* M5 users mailing list
*主题:* Re: [m5-users] Can't resolve Frequency error for FS Script File
I think it's actually complaining about this line from src/sim/System.py:
boot_cpu_frequency = Param.Frequency(Self.cpu[0
I think it's actually complaining about this line from src/sim/System.py:
boot_cpu_frequency = Param.Frequency(Self.cpu[0].clock.frequency,
boot processor frequency)
It's hard to say what the problem is without knowing more about the specific
At a higher level, Ali Saidi did some work a while ago on validating M5's
network performance modeling:
http://www.ideal.ece.ufl.edu/workshops/iosca05/validation.pdf
http://www.eecs.umich.edu/techreports/cse/2005/CSE-TR-511-05.pdf
Steve
On Fri, Dec 17, 2010 at 6:49 AM, Vince Weaver
Yea, you've got most of it there... I think the key detail you might be
missing is that forwarded packets and non-response packets are closely
related but not quite the same thing. It's quite possible that the usage of
isForward and isForwardNoResponse() is confusing the issue, so forget about
No, that's not true... the out-of-order scheduling will happen regardless of
functional unit assignment. I'm guessing that what happens is that all
instructions get assigned to some default functional unit type (probably
integer ALU), and I'm pretty sure the default O3 model has multiple integer
Thanks for the detailed analysis... this code is complex, I agree; I wrote
it, and when I have to get back into it to fix a bug it always takes a while
to recall all the detailed interactions.
I don't completely follow why downstreamPending is causing problems for you,
but I can elaborate a
Hi Marc,
Offhand, I'd say the accuracy of M5's models is pretty typical for an
academic research simulator; as with most simulators in this vein, we try to
balance performance, flexibility, and accuracy. It's also important to
remember that M5 is really a framework that comes with a bunch of
On Tue, Nov 23, 2010 at 10:22 AM, Ali Saidi sa...@umich.edu wrote:
What do you mean by cycle-accurate -- different people have very different
defintions?
Very true, which is why I didn't answer that part of Marc's question
directly...
___
m5-users
On Tue, Nov 2, 2010 at 7:33 AM, Weixun Wang wew...@cise.ufl.edu wrote:
Hi all,
A simple question. Could any one tell me that is the miss latency (e.g.,
system.cpu.dcache.overall_miss_latency) in M5 simulation output file? It is
apparently not # number of overall miss cycles since it has a
I'm guessing your system is not even booting... look through the output
files for error messages, and try to boot to a prompt before trying to run a
benchmark.
On Mon, Nov 1, 2010 at 9:35 PM, Omar Kahwwaji omarkahw...@hotmail.comwrote:
my command line is :
%build/ALPHA_FS/m5.opt -d
implementation? What part
(class) of the M5 behaves wrong at the scenario?
I would happy to know what is the correct scenario and where should I look
for a bug.
Thanks in advance,
Aleksei
On Mon, Nov 1, 2010 at 9:41 AM, Steve Reinhardt ste...@gmail.com wrote:
Yea, this looks like
On Fri, Oct 22, 2010 at 6:04 PM, Dave dave...@gmail.com wrote:
Hi all,
I like to evaluate my multicore cache model in ALPHA_SE and I wrote a simple
multithreading program for debugging.
Now I want to compile the program with Parmacs thread lib. I have no idea to
use which ALPHA cross
Sorry for the slow reply... the key thing to remember about the
built-in m5 coherence protocol is that one of the primary features is
that it works for arbitrary bus-based hierarchies. There are some
things that it does that are sub-optimal for specific hierarchies (and
for uniprocessors in
On Fri, Oct 22, 2010 at 11:22 AM, Glenn Ko g...@illinois.edu wrote:
Good question... I don't know the answer off the top of my head, but
you should be able to do it without adding more .cc and .hh files, but
just by adding stages to the time buffer so that it takes the buffered
values additional
You have to checkpoint the entire simulation (both systems), as there
is TCP connection state on both sides that has to be in sync (and
possibly even packets in flight on the wire). It is very useful to do
a checkpoint to avoid not just the bootup but the app init time as
well.
Unfortunately, in
First of all, I bet that 2B instructions are just a tiny fraction of
the total benchmark. If you're only looking for cache miss rates, you
don't need the detailed CPU mode ('-d'), and m5 will run a lot faster
without that.
Even if you are running the full program, there are a number of things
Is the benchmark running successfully on a single core, or is it not
running at all?
On Fri, Oct 15, 2010 at 8:41 PM, biswabandan panda biswa@gmail.com wrote:
Hi all,
i am still getting zeros all the cores except one for multicore
simulation with splash,some of the m5 users were
Can you change that assertion to include
target-pkt-cmd == MemCmd::SCUpgradeFailReq
and see if that fixes it? My guess just from reading your email is
that the bug is in the assertion and not in the code. At least that
would be nice, since it's an easy fix :-).
That assertion was just added
Good question... I don't know the answer off the top of my head, but
you should be able to do it without adding more .cc and .hh files, but
just by adding stages to the time buffer so that it takes the buffered
values additional cycles to get from one stage to the next.
At least that's the theory
to fork more threads.
Steve
On Fri, Oct 15, 2010 at 9:39 PM, biswabandan panda biswa@gmail.com wrote:
hi,
its running for single core.
On Sat, Oct 16, 2010 at 10:00 AM, Steve Reinhardt ste...@gmail.com wrote:
Is the benchmark running successfully on a single core
and FFT,
is it the problem with binaries which prevent it for running for long
time,actually it ends in 4 secs,but those FFT and FMM took around 15 to 20
mins.
thanks
biswa
On Sat, Oct 16, 2010 at 10:15 AM, Steve Reinhardt ste...@gmail.com wrote:
Then my guess is that somehow the arguments
here
Exiting @ tick 1147337000 because target called exit()
and in the stats file stats for one core only.
thanks biswa
On Sat, Oct 16, 2010 at 10:29 AM, Steve Reinhardt ste...@gmail.com wrote:
If it's ending in 4 seconds, it's almost certainly ending with an
error. I'd think you'd end up
There are bugs in the O3 model such that restoring directly from a
checkpoint into O3 doesn't work. That's why the standard-switch model
exists. I don't think it has anything to do with the memory size.
Steve
On Wed, Oct 13, 2010 at 11:54 AM, Lide Duan leaderd...@gmail.com wrote:
Hi,
I
On Thu, Oct 7, 2010 at 7:18 AM, Gabe Black gbl...@eecs.umich.edu wrote:
Steve Reinhardt wrote:
On Thu, Oct 7, 2010 at 2:01 AM, Glenn Ko g...@illinois.edu wrote:
1. Is it because it's a 64bits and 4 bytes cannot be accessed?
2. icache is working with 4 bytes because 32bit instructions
On Sat, Sep 25, 2010 at 3:05 AM, zhanglun...@ict.ac.cn wrote:
Hi, I am using M5 to study cache replacement policy. And I want M5 to skip
first 40 billion instructions and then running in the detailed mode.
As my may configure different L2 cache for each simulation (e.g. different
The files in the splash2 directory are for running some very old and
obsolete versions of Splash compiled for Tru64 with hacked-up
synchronization under SE mode. If you want to run under FS (which is
what you should be doing), you'll have to recompile the benchmarks for
Alpha Linux with pthreads.
That sounds interesting... I agree, the performance impact would be my
main concern. Generally interesting simulations run for long enough
that you more than make up for the cost of recompilation in the amount
of time you save running it. In particular if you're just counting
things, it's
The L1 will issue a ReadExReq whenever there is a write access that
completely misses in the L1. (It's a writeback, write-allocate
cache.) The L2 will be able to satisfy the ReadExReq only if it has
an exclusive copy of the block. Note that a ReadExReq is a true read;
an UpgradeReq is what is
Have you tried a recent version of the code? This changeset I pushed
last week eliminates some (but probably not all) of the unusual
coherence behavior:
http://repo.m5sim.org/m5/rev/aa8fd8f6a495
Also, are you running a uniprocessor or multiprocessor workload?
Steve
On Tue, Sep 14, 2010 at
Have you tried a different compiler version? 4.1.2 is kind of old,
and IIRC, the whole 4.1 series was a bit buggy.
Steve
On Wed, Sep 1, 2010 at 10:04 AM, Nilay Vaish ni...@cs.wisc.edu wrote:
I have been trying to compile M5 with Ruby. I am using the following the
command
scons -j 4
Hi Stijn,
It's true that there are subtle bugs in the coherence protocol that
seem to appear only when you use a different DRAM model that creates
different timings. I spent a fair amount of time a month or two ago
to try and fix things up, and I made some progress, but it's hard to
fix one
There may be other components that have timing derived from the CPU
clock in Python, and even though the core clock gets changed these
derived values won't get updated when you make the change too late as
in test 3. I don't know offhand of any examples, but you should diff
the config.ini files
Yea, you've got the right idea on the stats. We really should add
some stats to the PhysicalMemory object to count accesses but since we
haven't, counting MSHR misses in the last-level cache should give you
the same number (as long as you're not in FS mode with lots of I/O
device accesses).
As
It's still not ready for prime time... we've made a lot of progress
recently but haven't pushed it to the public repository yet.
Steve
On Fri, Jul 16, 2010 at 10:00 AM, Matthew Horsnell
matthew.horsn...@gmail.com wrote:
Can anyone comment on the progress of the GEM5 project?
Has anyone
.
On Wed, Jul 21, 2010 at 6:43 PM, Steve Reinhardt ste...@gmail.com wrote:
That would probably work. Thanks for cluing me in... hadn't thought
about verification applications.
Steve
On Wed, Jul 21, 2010 at 12:48 PM, Eberle rambo.u...@gmail.com wrote:
What about using only an icache
of a cache.
On Thu, Jul 22, 2010 at 2:02 PM, Steve Reinhardt ste...@gmail.com wrote:
Easy is in the eye of the beholder, but it is a change that only
involves the python config script.
Steve
On Thu, Jul 22, 2010 at 9:56 AM, Eberle rambo.u...@gmail.com wrote:
Is there an easy way to configure
O3 can deadlock if it doesn't have independent ID caches... if the
dcache blocks, the pipeline will continuously replay blocked loads,
which saturates the icache port and will prevent the blocked loads
from issuing if they don't have an independent path.
(At least that's how I remember it... I'm
to observe
the behavior with and without caches.
--
Eberle.
On Wed, Jul 21, 2010 at 2:37 PM, Steve Reinhardt ste...@gmail.com wrote:
O3 can deadlock if it doesn't have independent ID caches... if the
dcache blocks, the pipeline will continuously replay blocked loads,
which saturates the icache
I think Gabe is right that the memory values in the cache are getting
corrupted leading to the wrong values being used to generate pointers.
The type of problem you suggest with writeback seems like a possible
cause.
Steve
On Wed, Jul 21, 2010 at 11:38 AM, Weixun Wang wew...@cise.ufl.edu wrote:
On Mon, Jul 19, 2010 at 10:24 PM, nathan binkert n...@binkert.org wrote:
I am working on some timing attack problems. I was wondering whether it is
possible to use m5 in SE mode to do a pseudo switch of contexts: to execute
a workload, then (using the current processor state including caches,
What do you mean by SIMU?
Are you using m5 or m5-stable? The latter may not be updated for gcc 4.3.
Steve
On Fri, Jul 16, 2010 at 11:36 PM, VenkataRao Nagella
venkatarao.i...@gmail.com wrote:
Hii all,
My requirement is to get the hit/misses of TLB's,caches at every level.
I am wondering how
Lisa's script to paste together multiple independent checkpoints into
a multiprogrammed workload could be useful here...
On Fri, Jul 9, 2010 at 1:49 PM, Sujay Phadke spha...@eecs.umich.edu wrote:
Hello,
I want to execute a multi-workload simulation consisting of
different workloads (only 1
The eio tests will fail if you're not compiling in the eio extensions
from the encumbered repository.
Other tests will fail if you don't have the right binaries. In
particular, we can't distribute binaries for the spec-based
regressions due to licensing issues.
We're working on cleaning up the
It should work in the config file as long as you do it after the
system is constructed but before you call instantiate.
On Thu, Jul 15, 2010 at 7:43 AM, Zhe Wang zhw...@cise.ufl.edu wrote:
Hi Jie
Thanks for replying.
I clean up all the previous build and recompile M5, it works.
I
Lisa is right that AverageStat is the best answer to your specific problem.
If you really did need to do something on every CPU tick in the cache
though, I would recommend just adding a tick() method to the cache and
an event to call it at the same frequency as the CPU rather than
trying to
You're on the right track... off the top of my head:
M = Valid, Writable, Dirty
O = Valid, !Writable, Dirty
E = Valid, Writable, !Dirty
S = Valid, !Writable, !Dirty
I = !Valid
Note that Readable is only false for Valid blocks in transient states.
Steve
On Thu, Jul 15, 2010 at 9:50 AM, Lide
prefetcher-getPacket() should be called multiple times, each time the
bus becomes free, as long as the queue is not empty.
On Thu, Jul 15, 2010 at 10:20 AM, Ankit Sethia aset...@eecs.umich.edu wrote:
Hi,
I have a query regarding the working of prefetcher in M5. There is the
prefetcher degree
:14 AM, Steve Reinhardt wrote:
It should work in the config file as long as you do it after the
system is constructed but before you call instantiate.
On Thu, Jul 15, 2010 at 7:43 AM, Zhe Wangzhw...@cise.ufl.edu wrote:
Hi Jie
Thanks for replying.
I clean up all the previous build
trying to modify the condition that is checked when switching
into the timing/detailed mode to stall till all cores complete.
On Thu, 2010-07-15 at 07:56 -0700, Steve Reinhardt wrote:
Lisa's script to paste together multiple independent checkpoints into
a multiprogrammed workload could be useful
As you might have figured out, I don't think anyone runs m5 under
cygwin... I used to occasionally many years ago, but there are too
many little things that got annoying (signal handling issues, gdb not
really working properly, etc.). I eventually got to the point where,
if I really wanted to run
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