[gem5-users] Re: How to add registers in SE mode?

Hi Sai, Which kind of register are you talking about? Integer register? Floating point register? System register? (MiscReg in gem5) Also which ISA? (ARM, X86, etc) Giacomo From: svk V via gem5-users Sent: 25 April 2020 15:38 To: gem5-users@gem5.org Cc: svk V Subject: [gem5-users] How to add

[gem5-users] Re: M5 operation in kvm

Hi Tracy, It’s probably because the m5 binary shipped with linaro-minimal-aarch64.img Is using a reserved m5 instruction which is gem5 specific and it is not recognised by the host. In order to make things work, you need to recompile the m5 binary so that it uses memory mapped operations.

[gem5-users] Re: GDB debug help

Hi Shougang curTick is a function as you can see from: (gdb) p curTick $1 = {Tick (void)} 0x562aea48 Could you try doing: (gdb) p curTick() It should display the current Tick time Giacomo From: Shougang Yuan via gem5-users Sent: 02 October 2020 04:00 To: gem5 users mailing list Cc:

[gem5-users] Re: How to run ARM ISA in SE mode on an x86 host

Hi Dimitrios; The problem is that your binary is dynamically linked. You need to point the elf loader to the aarch64 interpreter(linker) which is usually provided within the toolchain. Please have a look at:

[gem5-users] Re: CPU configuration and default values

(as most people probably do already). Thanks. -- dbb ____ From: Giacomo Travaglini via gem5-users mailto:gem5-users@gem5.org>> Sent: Thursday, October 8, 2020 11:17:43 AM To: gem5 users mailing list Cc: Davide Basilio Bartolini; Giacomo Travaglini Subject

[gem5-users] Re: CPU configuration and default values

Hi Davide, This is annoying indeed. The main problem IMHO is that you shouldn't be using Options.py in the first place (this is why I am not personally using swiss army knife scripts like fs.py). I suggest you to have a look at fs_bigLITTLE.py and use that as a reference for a main/top level

[gem5-users] Re: Exceptions and errors when running tests with gem5 release 20.1

Hi Liao, That is correct, the script is trying to download binaries from: http://dist.gem5.org/dist/current/ If you want to download them manually, you might need the full path of the binary the test is trying to download. Once you download them the first time, you won't have to download them

[gem5-users] Re: KVM test regressions?

https://gem5-review.googlesource.com/c/public/gem5/+/31219 This is introducing it for Arm. The only missing thing is replacing the m5 binary in gem5.org to use the mmapped m5 exit From: Gabe Black via gem5-users Sent: 25 August 2020 06:12 To: gem5 users mailing list ; Bobby Bruce ; Andreas

[gem5-users] Re: Using perf_event with the ARM PMU inside gem5 on Linux

Hey Pierre, You are actually very close to get it right! The problem is: there should be a single PMU instantiation. What you need to do in the BaseCPU is: # Generate nodes from the BaseCPU children. # Please note: this is mainly needed for the ISA class for node in

[gem5-users] Re: Using perf_event with the ARM PMU inside gem5 on Linux

This is great Pierre! I recommend you the following documentation http://www.gem5.org/contributing which will guide you through the contributing process. If you have any other question, don’t hesitate to ask. About the issue you are encountering, I am not that familiar with perf_events; I

[gem5-users] Re: Using perf_event with the ARM PMU inside gem5 on Linux

Hi Pierre, First of all many thanks for explaining in detail what is your problem. This is very helpful. The reason why you are not able to use perf_events is probably because the kernel is not aware of the presence of PMUs. This is usually communicated to Linux via the DTB. I can see how we

[gem5-users] Re: Protobuf error on different ubuntu version

Hi Shougang, This happens since some protobuf versions use preprocessing symbols without defining them (relying on the fact they default to 0). This is clashing with gem5 behaviour of warning on undefined symbols (Wundef). Feel free to remove the Wundef locally (as a hack) or choose a protobuf

[gem5-users] Re: Protobuf error on different ubuntu version

Sure, just remove the Wundef option from the top level SConstruct file Giacomo From: Shougang Yuan Sent: 22 May 2020 22:46 To: Giacomo Travaglini Cc: gem5 users mailing list Subject: Re: [gem5-users] Protobuf error on different ubuntu version Hi, Giacomo, Thanks for your reply, could you

[gem5-users] Re: Ask for HELP about SMT in FS mode

Hi, You shouldn't be concerned about the warnings you mentioned; those are quite common and they shouldn't affect the functional correctness of you simulation warn: instruction'csdb' unimplemented warn: GIC APRn write ignored because not implemented: 0xd0 About SMT: I am not aware of the

[gem5-users] Re: --script parameter doesn't work

Hi Tracy, It seems like there is a problem in the m5 pseudo op which doesn’t get recognised by gem5. Could you open a JIRA ticket for this? https://gem5.atlassian.net/secure/BrowseProjects.jspa Feel free to assign it to me Kind Regards Giacomo From: Tracy Mac via gem5-users Sent: 25

[gem5-users] Re: KVM does not work

Hi, which branch/commitId are you using? Giacomo From: 毛允飞 via gem5-users Sent: 12 August 2020 09:41 To: gem5-users@gem5.org Cc: 毛允飞 Subject: [gem5-users] KVM does not work Hi All I run the fs_bigLITTLE.py script in gem5, but there is no information in the m5term console. I don't know what

[gem5-users] Re: Current status of gem5 capabilities regarding multicores full system simulation

Thanks Nathanael, Could you open a JIRA ticket for that? https://gem5.atlassian.net/projects/GEM5/issues Kind Regards Giacomo From: Nathanael Premillieu Sent: 29 July 2020 16:46 To: Giacomo Travaglini ; gem5 users mailing list Cc: Ciro Santilli Subject: RE: [gem5-users] Re: Current status

[gem5-users] Re: Running a program on GEM5 for specific number of instructions

Hi, it depends what you mean by skip. Most of the times those initial 50k instructions would be needed to be executed to bring up the program to the current state. What you can do is to execute 50k instructions and then take a checkpoint. Next time you have to re-execute the program you would

[gem5-users] Re: Remove/disable stats

Yes I think the commit message is referring to an old version of the patch. Now the option is in https://gem5-review.googlesource.com/c/public/gem5/+/28628/5/configs/common/Options.py which is used by https://gem5-review.googlesource.com/c/public/gem5/+/28628/5/configs/common/Simulation.py#458

[gem5-users] Re: Remove/disable stats

Hi Oivind I suggest you to have a look at the following patch which is currently under review: https://gem5-review.googlesource.com/c/public/gem5/+/28628 This will make it possible to dump stats starting from a user specified root node (in the simobject hierarchy). For example, if you are

[gem5-users] Re: Remove/disable stats

No problem! Giacomo P.S For the future, may I suggest you to reply to the message rather than creating a new one? In this way it will be easier for other people to follow the thread if it is interesting to them  -Original Message- From: Øivind Harket Bakke via gem5-users Sent: 08

[gem5-users] Re: Current status of gem5 capabilities regarding multicores full system simulation

Nathanael, The only difference is that V1 is using GICv2 and V2 is using GICv3. About what I am suggesting: while using V2 with DTB autogen (as Ciro suggested), apply the following diff diff --git a/src/dev/arm/RealView.py b/src/dev/arm/RealView.py index f78b41e..d667659 100644 ---

[gem5-users] Re: Current status of gem5 capabilities regarding multicores full system simulation

I have the suspicion the problem is in the Gicv3 ITS doing DMAs to the coherent XBar without a cache controller. Could you disable it from V2? Otherwise you would need to put a cache between the ITS and the XBar Let me know if it works, Giacomo Get Outlook for iOS

[gem5-users] Re: Using perf_event with the ARM PMU inside gem5 on Linux

> > > > From: Giacomo Travaglini [giacomo.travagl...@arm.com] > > > > > Sent: 19 November 2020 11:41 > > > > > To: POLYCHRONOU Nikolaos; gem5 users mailing list > > > > > Subject: RE: [gem5-users] Re: Using perf_event with the ARM PMU >

[gem5-users] Re: Looking for Linux disk image for 64-bit ARM with Ubuntu 18.04 or GLIBC 2.27

Hi Jiwon We recently uploaded a prebuilt Ubuntu18.04 on gem5.org: http://dist.gem5.org/dist/current/arm/disks/ubuntu-18.04-arm64-docker.img.bz2 Kind Regards Giacomo > -Original Message- > From: Choe, Jiwon via gem5-users > Sent: 29 November 2020 04:42 > To: gem5 users mailing list >

[gem5-users] Re: Using perf_event with the ARM PMU inside gem5 on Linux

; > > > > static int perf_fd_cpu_cycles; > > > > > static struct perf_event_attr attr_cpu_cycles; > > > > > attr_cpu_cycles.size = sizeof(attr_cpu_cycles); > > > > > attr_cpu_cycles.exclude_kernel = 1; > > > > > attr_cpu_cycles.

[gem5-users] Re: Number of architectural registers for ARM ISA

Hi, I suggest you to have a look at src/arch/arm/intregs.hh to see how the indexes are defined. You will notice how both NUM_ARCH_INTREGS and NUM_INT_REGS are defined. The first refers to the architectural limit, the second accounts for register banking (in AArch32) and it's bigger than

[gem5-users] Re: Using perf_event with the ARM PMU inside gem5 on Linux

hed but with the cycle counter. > > > > > > > > > > If you cannot open the file descriptor it means there is something > > > wrong. It means the Linux Kernel doesn't recognise a PMU. > > > > > > This could be caused by one of th

[gem5-users] Re: Using perf_event with the ARM PMU inside gem5 on Linux

> read pmus) <- PMU starts counting here M5 dumpstats > > So in a way I see why there is a difference. I plan to include the > asm_volatile of > these instructions in my C code and see again. > > Also for the probe points I can search it a little bit. > Regards > Nikos >

[gem5-users] Re: Using perf_event with the ARM PMU inside gem5 on Linux

gt; I understand, but which events in particular? Anyway as it seems like the PMU > is not correctly configured, I would defer > The handling of this problem until we are sure we are doing things right. > > Anyway I can tell you should expect a small mismatch: > > M5 restestats

[gem5-users] Re: Using perf_event with the ARM PMU inside gem5 on Linux

Hi Nikolaos > -Original Message- > From: POLYCHRONOU Nikolaos via gem5-users > Sent: 18 November 2020 07:20 > To: gem5-users@gem5.org > Cc: POLYCHRONOU Nikolaos > Subject: [gem5-users] Re: Using perf_event with the ARM PMU inside gem5 on > Linux > > Helllo. > > I encounter the following

[gem5-users] Re: Using perf_event with the ARM PMU inside gem5 on Linux

t; > > > > > > > The assemply I use to instantiate the ccnt is the one provided in > > > the libraries Armageddon/libflush. I will take a look in the one you > > > attach > me. > > > > > > As it seems all the event counters are d

[gem5-users] Re: ThreadID vs ContextID vs threadNumber

HI Farhad, ThreadID -> index of the thread within the CPU ContextID -> global index of the thread within the System As you can imagine they differ in a MP simulation, with multiple CPUs per System Kind Regards Giacomo From: Farhad Yusufali via gem5-users Sent: 13 November 2020 14:25 To: gem5

[gem5-users] Re: ThreadID vs ContextID vs threadNumber

ontent with extra caution. Hi Farhad, To clarify: * CPU ports, in all simple, minor and O3 configurations, tag generated Requests with ContextID. * Outgoing Packets from CPU ports have a Request pointer inside, via which you can get the ContextID. Kind regards, Adrian. From: Gia

[gem5-users] Re: Introducing myself

Hi Gabriel, Welcome on board! Giacomo -Original Message- From: gabriel.busnot--- via gem5-users Sent: 03 November 2020 10:03 To: gem5-users@gem5.org Cc: gabriel.bus...@arteris.com Subject: [gem5-users] Introducing myself Hi Gem5 community, I want to introduce myself as a new Gem5

[gem5-users] Re: gem5 encountered a segmentation fault when I running Arm FS mode

Hi, >From the command line you posted I can see you are using the following DTB >binary: --dtb-file=./system/arm/dt/armv8_gem5_v1_1cpu.dtb This is informing the Linux kernel there is one cpu only (armv8_gem5_v1_1cpu.dtb). That's why you don't see the other ones. You should change DTB binary

[gem5-users] Re: How to add a new pcie device on GEM5

Hi, I’d recommend having a look at the VirtIO device…. (I don’t know if there are better examples, more experienced people are welcome to chime in) Giacomo From: Liyichao via gem5-users Sent: 22 October 2020 11:51 To: gem5 users mailing list Cc: Liyichao Subject: [gem5-users] How to add a

[gem5-users] Re: Question regarding DTS under FS mode

Hi Huayi, I suggest you to have a look at the following documentation: https://elixir.free-electrons.com/linux/latest/source/Documentation/devicetree/bindings/cpu/cpu-topology.txt This should be a good starter as it covers the SMT case  Kind Regards Giacomo From: Huayi Cai via gem5-users

[gem5-users] Re: Error coming while running GEM5 in FS mode

I believe you are not providing a valid kernel to the command line: "/home/coep/gem5/full_systems_images/binaries" is likely the folder containing the kernel image. This should rather be: /home/coep/gem5/full_systems_images/binaries/ If that's not the case, I'd recommend you to use gdb to

[gem5-users] Re: SimpleMem error

Hi It seems like the VExpress_GEM5_Base.bootmem (first 64MB of memory) is overlapping with some other memory. Have you made any modifications to starter_fs.py or to other configuration scripts? By default starter_fs.py should start allocating memory at 2GB, so my guess is that you are adding

[gem5-users] Re: VExpress_GEM5_V1, Ethernet, and BARs

I think the problem lies in the DTB and more specifically in the range mapping https://github.com/gem5/gem5/blob/stable/system/arm/dt/platforms/vexpress_gem5_v1_base.dtsi#L70 Could you replace the third word with 0x0? Otherwise you could rely on DTB autogeneration (simply omit the --dtb

[gem5-users] Re: VExpress_GEM5_V1, Ethernet, and BARs

Out of curiosity, which DTB are you using? IMO the kernel shouldn't write 800 to the PCI Bar, knowing there is DRAM there and this is notified via the DTB Kind Regards Giacomo > -Original Message- > From: Bohren, Jonathan via gem5-users > Sent: 22 January 2021 12:51 > To: gem5

[gem5-users] Re: ARM PMU memory mapped registers

Hi Nikolaos > -Original Message- > From: POLYCHRONOU Nikolaos > Sent: 24 January 2021 10:38 > To: gem5 users mailing list ; Giacomo Travaglini > > Subject: ARM PMU memory mapped registers > > Good morning to all, > > I would like to ask if anyone knows if PMU registers are memory mapped

[gem5-users] Re: Errors coming while running gem5 in full system mode

> -Original Message- > From: VAIDYA ROHINI VILAS via gem5-users > Sent: 19 January 2021 06:38 > To: gem5 users mailing list > Cc: VAIDYA ROHINI VILAS > Subject: [gem5-users] Re: Errors coming while running gem5 in full system > mode > > i think i am doing mistake while adding kernel

[gem5-users] Re: Errors comming while runnig my own c code in full system mode

Hi, This simply means there is no disk image found at home/full_system_images/disks/arm-ubuntu.natty-headless.img you probably simply need to add a forward slash before home: /home/full_system_images/disks/arm-ubuntu.natty-headless.img Kind Regards Giacomo > -Original Message- >

[gem5-users] Re: Passing 2-dimension list from Python to C++ object

Hi Daecheol, As far as I am aware this is not possible. That would require something like VectorParam.VectorParam.Int which is not currently supported I would recommend you to change your python interface to accommodate for this missing feature Kind Regards Giacomo From: Daecheol You via

[gem5-users] Re: KVM Doesn't Work

FYI these patches are merged in the develop branch atm: https://gem5-review.googlesource.com/c/public/gem5/+/36795 https://gem5-review.googlesource.com/c/public/gem5/+/31218/6/tests/gem5/configs/arm_generic.py And they should fix your problem (will be part of gem5 21.0) The second one is just an

[gem5-users] Re: System() and RubySystem()

Hi Javed, You are correct in your assumptions. I believe the confusion arises from the overuse of the "System" keyword. As a summary, The System class (defined in src/sim/system.hh) is the child of the Root node and encompasses most of the simulated models (cpu, memory subsystem, devices,

[gem5-users] Re: Arm bitLITTLE config

Hi Javed > -Original Message- > From: Javed Osmany via gem5-users > Sent: 09 June 2021 15:01 > To: gem5 users mailing list > Cc: Javed Osmany > Subject: [gem5-users] Arm bitLITTLE config > > Hello > > > > The system I would like to model consists of three clusters [Big, Middle, >

[gem5-users] Re: Boot FS with kvm and multiple cores

Hi Pedro, glad it worked > -Original Message- > From: Pedro Henrique Exenberger Becker > Sent: 14 May 2021 10:48 > To: Giacomo Travaglini > Cc: gem5 users mailing list > Subject: Re: [gem5-users] Re: Boot FS with kvm and multiple cores > > Hi Giacomo, > > > > --little-cpus option

[gem5-users] Re: Using the CHI protocol for GEM5

Hi Javed, > -Original Message- > From: Javed Osmany via gem5-users > Sent: 18 May 2021 14:16 > To: gem5-users@gem5.org > Cc: Javed Osmany > Subject: [gem5-users] Using the CHI protocol for GEM5 > > Hello > > > > Previously, when experimenting with MESI or MOESI coherence protocol, > the

[gem5-users] Re: Ruby in Arm?

Hi Adrian, > -Original Message- > From: adrian via gem5-users > Sent: 07 May 2021 09:36 > To: gem5-users@gem5.org > Cc: adrian.barre...@gmail.com > Subject: [gem5-users] Ruby in Arm? > > Hi guys, > > I've always used the classic memory model when running timing simulations > using Arm,

[gem5-users] Re: Ruby in Arm?

Hi Adrian, I don't know to be honest why this is happening in fs.py only. In general, have you tried to recompile the gem5 bootloader or alternatively to download the latest precompiled version? [1] Kind Regards Giacomo [1]:

[gem5-users] Re: Qemu equivalent command/simulation to Gem5

Hi > -Original Message- > From: Đức Anh via gem5-users > Sent: 11 May 2021 13:34 > To: gem5 users mailing list > Cc: Đức Anh > Subject: [gem5-users] Qemu equivalent command/simulation to Gem5 > > Dear all, > > I have a Linux kernel v5.10.27 build for arm64 architecture that is runnable

[gem5-users] Re: Boot FS with kvm and multiple cores

Hi Pedro > The main problem I still have is fs_bigLITTLE.py with --big-cpus 8 (I want to > have an 8-core setup) causes panic: > info: Using bootloader at address 0x10 > info: Using kernel entry physical address at 0x8008 > info: Loading DTB file: m5out/system.dtb at address 0x8800 >

[gem5-users] Re: Tracing Instructions in gem5 (re: Adding a New Instruction)

Hi Jason, > -Original Message- > From: jzell001--- via gem5-users > Sent: 14 May 2021 00:44 > To: gem5-users@gem5.org > Cc: jzell...@ucr.edu > Subject: [gem5-users] Tracing Instructions in gem5 (re: Adding a New > Instruction) > > Hi Everyone, > > I am fairly new to gem5, so I apologize

[gem5-users] Re: Boot FS with kvm and multiple cores

Thanks Pedro, It seems like you are getting an undefined instruction. What is probably happening is your host CPU having a feature which is not implemented in gem5, so when you switch to the guest(gem5) the sandboxing check is skipped and an exception is thrown. As you are happy with your

[gem5-users] Re: Variable Definitions

Hi Jason, At a certain point I should really come up with an ISA documentation to upload on gem5.org Anyway, those are magic operands defined in the operands file [1]. (More specifically [2] and [3]). When the ISA parser detect those magic words, it translates them into an appropriate action

[gem5-users] Re: Boot FS with kvm and multiple cores

Hi Pedro, What happens if you try to simulate the GIC? Have a look at what we do in fs_bigLITTLE with the --kvm-userspace-gic option. You should be able to replicate that in fs.py (though I would recommend you to switch to the fs_bigLITTLE script if possible  ) Kind Regards Giacomo P.S. I

[gem5-users] Re: How to find the address range of an ARM IO device

Hi, > -Original Message- > From: Md Rubel Ahmed via gem5-users > Sent: 05 July 2021 22:24 > To: gem5 users mailing list > Cc: Md Rubel Ahmed > Subject: [gem5-users] How to find the address range of an ARM IO device > > Greetings, > > I was trying to get the address range of each device

[gem5-users] Re: SSH on ARM Full System

Hi Nikolaos, this is great! > > I would like to connect one gem5 to another through ssh (because I > would like to use MPI). > > I have installed the openssh-client packet through qemu but I get the > above connection refused. After that, I installed the openssh-server > through qemu, but it is

[gem5-users] Re: PCI Express on gem5

Hi Nikos, The author submitted a partial implementation to gerrit (Simply modelling a PCIe Link) some time ago: https://gem5-review.googlesource.com/c/public/gem5/+/13024 A Root Complex and PCI Express Switch implementation was supposed to be uploaded but this never happened as far as I know.

[gem5-users] Re: How to use HTM in gem5-20?

Hi, Arm has provided an HTM implementation. I suggest you to have a look at the following blog post by Timothy Hayes (he wrote the implementation) http://www.gem5.org/project/2020/10/27/tme.html Kind Regards Giacomo > -Original Message- > From: Taiyu Zhou via gem5-users > Sent: 28

[gem5-users] Re: How to use HTM in gem5-20?

Yes, that is correct  Kind Regards Giacomo > -Original Message- > From: Taiyu Zhou via gem5-users > Sent: 28 April 2021 13:12 > To: gem5-users@gem5.org > Cc: Taiyu Zhou > Subject: [gem5-users] Re: How to use HTM in gem5-20? > > Thank you so much for your reply. > So, is it gem5-20

[gem5-users] Re: KVM Doesn't Work

Let's say it's in our wish-list, but we don't plan to work on it anytime soon. Kind Regards Giacomo > -Original Message- > From: Liyichao > Sent: 27 January 2021 15:06 > To: Giacomo Travaglini ; gem5 users mailing > list > Cc: Tracy Mac > Subject: RE: [gem5-users] Re: KVM Doesn't

[gem5-users] Re: ARM PMU memory mapped registers

Makes sense! Feel free to post your contribution to gerrit once you manage to implement this. We would be very happy to have this merged in gem5 Kind Regards Giacomo > -Original Message- > From: POLYCHRONOU Nikolaos > Sent: 24 January 2021 20:43 > To: Giacomo Travaglini ; gem5 users

[gem5-users] Re: HLT instrution

Hi Liyichao > -Original Message- > From: Liyichao > Sent: 23 March 2021 06:54 > To: Giacomo Travaglini ; gem5 users mailing > list > Subject: 答复: HLT instrution > > Hi Giacomo: > > When I add armsemihosting in fs.py like this: > 438 from m5.objects import ArmSemihosting > 439

[gem5-users] Re: Running script after boot in full-system mode

Hi Pedro > -Original Message- > From: Pedro Becker via gem5-users > Sent: 23 March 2021 13:37 > To: gem5-users@gem5.org > Cc: Pedro Becker > Subject: [gem5-users] Running script after boot in full-system mode > > Hi all, > > I'm trying to use the --script flag to run a script after boot

[gem5-users] Re: Gem5 hang with multi core

Hi Xijing, Could you please provide us with more information (e.g. the command line) Kind Regards, Giacomo From: Xijing Han via gem5-users Sent: 26 March 2021 17:10 To: gem5-users@gem5.org Cc: Xijing Han Subject: [gem5-users] Gem5 hang with multi core Hi, I

[gem5-users] Re: IGbE_e1000 card not connected

Hi Nikos, > -Original Message- > From: Νικόλαος Ταμπουρατζής via gem5-users > Sent: 31 March 2021 21:04 > To: gem5-users@gem5.org > Cc: Νικόλαος Ταμπουρατζής > Subject: [gem5-users] IGbE_e1000 card not connected > > Dear gem5 community, > > I would like to use the IGbE_e1000 card in the

[gem5-users] Re: IGbE_e1000 card not connected

Eval_EvalFrameDefault+0x4ec3)[0x7f15362943 > 03] > /usr/lib/x86_64-linux-gnu/libpython3.6m.so.1.0(+0x17ba0f)[0x7f153628da0f] > /usr/lib/x86_64-linux-gnu/libpython3.6m.so.1.0(+0x17c0fc)[0x7f153628e0fc] > /usr/lib/x86_64-linux- > gnu/libpython3.6m.so.1.0(_PyEval_EvalFrameDefault+0x4ec3)[0x7f

[gem5-users] Re: KVM usage: x86 host, arm target

Hi Pedro, > -Original Message- > From: Pedro Becker via gem5-users > Sent: 31 March 2021 13:03 > To: gem5-users@gem5.org > Cc: Pedro Becker > Subject: [gem5-users] KVM usage: x86 host, arm target > > Hi all, > > I'm running gem5 (v20.1.0.4) on an x86 machine, targeting an ARM (aarch64)

[gem5-users] Re: Fail to Boot Multicore Arm System with KVM CPU

Hi Wenqi, First of all thanks for the detailed explanation of your problem. > -Original Message- > From: wqyin--- via gem5-users > Sent: 30 March 2021 22:47 > To: gem5-users@gem5.org; wq...@utexas.edu > Cc: wq...@utexas.edu > Subject: [gem5-users] Fail to Boot Multicore Arm System with

[gem5-users] Re: Fail to Boot Multicore Arm System with KVM CPU

Thanks Wenqi, I was about to suggest the same; please feel free to open a JIRA ticket at: https://gem5.atlassian.net/jira/software/c/projects/GEM5/issues/ Kind Regards Giacomo > -Original Message- > From: Wenqi Yin > Sent: 07 April 2021 06:40 > To: gem5 users mailing list > Cc:

[gem5-users] Re: m5 utility for ARM64

Thanks Gabe for providing support. I just want to add: judging by the disk image name (ubuntu-18.04-arm64-docker.img) I presume it is the prebuilt image provided by the gem5.org website. That should already have the new m5 binary, so recompilation won't be necessary, and you can simply use m5

[gem5-users] Re: Fail to Boot Multicore Arm System with KVM CPU

Yes, apologies, I forgot to mention that. As your host is likely using a GICv3 interrupt controller, you need to entirely emulate the GICv2 and Generic Timer in userspace (gem5). This is done via the simulate_gic (as you have already done) and by removing the system register interface info from

[gem5-users] Re: Fail to Boot Multicore Arm System with KVM CPU

Hi Wenqi, Could you provide us with the booting log of the guest kernel? Kind Regards Giacomo > -Original Message- > From: Wenqi Yin > Sent: 06 April 2021 05:48 > To: Giacomo Travaglini > Cc: gem5 users mailing list ; Wenqi Yin > > Subject: Re: [gem5-users] Fail to Boot Multicore

[gem5-users] Re: --script can't be read when using kvm

Hi, This is probably happening because 20170616/disks/linaro-minimal-aarch64.img is using the old m5 binary and as such it doesn't support the runtime --addr option (which has been added after 2017) I recommend you to either rebuild the m5 binary and replace it in the disk image, or to use the

[gem5-users] Re: HLT instrution

Hi Liyichao, That is because Halting of the PE (refer to the External Debug section of the Arm architecture reference manual for more info) is not implemented. The only use of HLT at the moment is as a semihosting call instruction 207 ThreadContext *tc = xc->tcBase(); 208 bool have_semi

[gem5-users] Re: Cannot boot full-system aarch64

Hi Pedro, I'd recommend you to rely on the "configs/example/arm/starter_fs.py" script instead and, with M5_PATH pointing to the /home/pedro/Projects/gem5/fs_files/aarch-system-201901106 folder, simply run with build/ARM/gem5.opt configs/example/arm/starter_fs.py \ --kernel

[gem5-users] Re: Cannot boot full-system aarch64

Hi Pedro, Please check inline replies for more info > -Original Message- > From: Pedro Becker via gem5-users > Sent: 22 March 2021 14:15 > To: gem5-users@gem5.org > Cc: Pedro Becker > Subject: [gem5-users] Re: Cannot boot full-system aarch64 > > Thanks, Arthur and Giocomon for the

[gem5-users] Re: Cannot boot full-system aarch64

That's great Pedro! As I mentioned in previous email, pointing to the first partition should solve the problem (use --root=/dev/vda1 or remove the option as vda1 is the default) Kind Regards Giacomo > -Original Message- > From: Pedro Becker via gem5-users > Sent: 22 March 2021 17:04

[gem5-users] Re: Cannot boot full-system aarch64

Hi Pedro > -Original Message- > From: Pedro Becker via gem5-users > Sent: 22 March 2021 16:29 > To: gem5-users@gem5.org > Cc: Pedro Becker > Subject: [gem5-users] Re: Cannot boot full-system aarch64 > > Hi Giacomo, > > Just re-build gem5 from scratch (after `rm -rf` the build folder). >

[gem5-users] Re: Simulated vs Committed Ops

Yeah, this is a quirkiness of gem5. I have tried to address it some time ago [1]; I should probably go back and rebase the patchset. Basically the numOp, by being a Counter (and not a Stat) doesn't get reset every time you reset stats. So the numOp is the total number of ops since the beginning

[gem5-users] Re: Simulated vs Committed Ops

Hi Farhad, Quick question: are you resetting the stats between one workload and the other? Kind Regards Giacomo > -Original Message- > From: Farhad Yusufali via gem5-users > Sent: 15 March 2021 16:26 > To: gem5-users@gem5.org > Cc: Farhad Yusufali > Subject: [gem5-users] Simulated vs

[gem5-users] Re: Running ARM FS mode

Hi, You are not providing a --disk-image option to fs.py You should download the latest AArch32 disk image from the link you mentioned and pass it to the command line: https://www.gem5.org/documentation/general_docs/fullsystem/guest_binaries Kind Regards Giacomo > -Original Message-

[gem5-users] Re: Errors coming while running gem5 in full system mode

Hi, I see few errors here > -Original Message- > From: VAIDYA ROHINI VILAS via gem5-users > Sent: 25 February 2021 14:29 > To: gem5 users mailing list > Cc: VAIDYA ROHINI VILAS > Subject: [gem5-users] Re: Errors coming while running gem5 in full system > mode > > Hello, > > > I want to

[gem5-users] Re: Fail to Boot Multicore Arm System with KVM CPU

Hi Wenqi, I have found the problem; in order to fix it you should recompile the bootloaders from system/arm/bootloader/arm64 and replace all of them with the ones in M5_PATH/binaries That solves the problem on my side. I am gonna update the guest binaries tarball in gem5.org (I was going to do

[gem5-users] Re: Fail to Boot Multicore Arm System with KVM CPU

Hi Wenqi > -Original Message- > From: wq...@utexas.edu > Sent: 09 April 2021 23:07 > To: Giacomo Travaglini ; gem5 users mailing > list > Subject: Re: [gem5-users] Fail to Boot Multicore Arm System with KVM CPU > > Hi Giacomo, > > Thanks for letting me know what the problem is, I am

[gem5-users] Re: Error while installing gem 5

I believe it just takes a lot of time (I have been noticing the same). Could you try to wait for completion? Kind Regards Giacomo > -Original Message- > From: VAIDYA ROHINI VILAS via gem5-users > Sent: 20 April 2021 06:32 > To: gem5 users mailing list > Cc: VAIDYA ROHINI VILAS >

[gem5-users] Re: ARM and opening a file

FYI the debug flag option is --debug-flags=SyscallAll Kind Regards Giacomo > -Original Message- > From: Gabe Black via gem5-users > Sent: 21 April 2021 01:20 > To: gem5 users mailing list > Cc: Gabe Black > Subject: [gem5-users] Re: ARM and opening a file > > If this works on x86,

[gem5-users] Re: Booting Rtems OS in Gem5 ARM FS mode

Hi Duc > -Original Message- > From: Đức Anh via gem5-users > Sent: 08 April 2021 04:31 > To: gem5 users mailing list > Cc: Đức Anh > Subject: [gem5-users] Booting Rtems OS in Gem5 ARM FS mode > > Dear all, > > I am looking for a way to run RTEMS 5 OS in Gem5 ARM FS simulation. >

[gem5-users] Re: Deactivate WFE in Full System Simulation

Hi Victor > -Original Message- > From: Víctor Soria via gem5-users > Sent: 19 February 2021 12:00 > To: gem5-users@gem5.org > Cc: Víctor Soria > Subject: [gem5-users] Deactivate WFE in Full System Simulation > > Hello, > > I am using gem5 with the ARM ISA. I am working with some locks

[gem5-users] Re: Error coming while running in fs mode

Hi Vaidya > -Original Message- > From: VAIDYA ROHINI VILAS > Sent: 22 February 2021 13:47 > To: gem5-users@gem5.org; Giacomo Travaglini > Subject: Error coming while running in fs mode > > Hello, > I am trying to run gem5 in fs mode using command : > > "build/ARM/gem5.opt

[gem5-users] Re: SE ARM C stdio fseek() function invokes a failed writeBlob in port_proxy.hh

Thanks Deric, I wonder if it is linked to this problem: https://gem5.atlassian.net/jira/software/c/projects/GEM5/issues/GEM5-1074 What happens if you cross-compile for aarch64? Kind Regards Giacomo > -Original Message- > From: Deric Cheung via gem5-users > Sent: 16 August 2021

[gem5-users] Re: atomic translation error in ARM FS Mode

Hi Burak, This is a python configuration problem. You need to make sure the table walker port is connected. Please double check the ArmMMU.walkerPorts() method is called in the FS script Kind Regards Giacomo > -Original Message- > From: Burak Öçalan via gem5-users > Sent: 22 August

[gem5-users] Re: Boot FS with kvm and multiple cores

Hi Pedro, The MSR (immediate) is the software interface for modifying the PSTATE of the PE. In this case the instruction is trying to change the PSTATE.UAO field, which is not implemented in gem5 This is why you are not able to restore the checkpoint in atomic. Implementing UAO should fix it.

[gem5-users] Re: Boot FS with kvm and multiple cores

This is great Pedro! Thanks for the pointers, other KVM users might find it useful. Regarding the Linux Kernel question, there is no preferred version from our side. You can even build a vanilla arm64 kernel and it should just work. IIRC we provided support until 5.8 in gem5 v21.0 Kind

[gem5-users] Re: Problem with SIMD instructions execution in se mode when ISA is ARM

Hi Gelin, I understand the confusion. Even if there are no SIMD operations, you are issuing FP operations and those are using vector elements as single and double precision scalar registers are elements of the SIMD vector registers Kind Regards Giacomo > -Original Message- > From:

[gem5-users] Re: SE ARM: Assertion error in rename_map.hh on call to pthread_create using m5threads

Hi Deric, This is a known issue. You can work around the problem in two different ways: 1) Cross-compile your program for aarch64 2) Hardcode the ISA.highestELIs64 to false as you are effectively cross-compiling for AArch32 Kind Regards Giacomo > -Original Message- > From: Deric

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