Re: Dr. John Ehrman

On 2/20/2018 2:50 PM, Tony Thigpen wrote: I am deeply saddened to report that John passed away this morning (Tuesday, 20 February 2018) following a protracted battle with cancer. I am also deeply saddened. John tended to speak quietly and was a kind and thoughtful person. Yet his work with

Re: CSST question

On 9/13/2017 12:26 PM, Charles Mills wrote: Question: is there any way for the 'examining' code, possibly running on a different CPU, to be assured of seeing a consistent (either 'before' or 'after') POINTER and ADDRESS contents? Possibly with serialization at some point? In general, no. The

Re: CSST question

On 9/12/2017 9:35 AM, Charles Mills wrote: Disabling for interruptions is not sufficient in a multi-processor world, right? Disabling for interrupts guarantees, even in a multi-processing world, that the executing unit of work will not lose control from the perspective of the logical CP that

Re: CSST question

On 9/10/2017 11:39 AM, Charles Mills wrote: ... Is that saying that there is a chance that another CPU might observe a condition in which the store of the first operand had occurred, but the store of the second operand had not? My understanding from earlier paragraphs was that CSST happened "all

Re: Z performance question #1 - AR mode

On 7/7/2017 7:44 AM, Binyamin Dissen wrote: How big is the performance cost of running ARMODE? Should there be a section of code that uses only ALET 0, is it best to go into primary mode for that section? Nothing, so long as AR translation is not required. And an ALET of 0 (or 1) would

Re: Z performancequestion #2 - key 9

On 7/7/2017 7:44 AM, Binyamin Dissen wrote: What is the performance cost of using key 9 storage when the PSW is not in key 9? Nothing (zip, nil, nada). Regards, Greg -- For IBM-MAIN subscribe / signoff / archive access

Re: IEAMSCHD no FRR param

On 6/23/2017 11:37 AM, contactmura...@gmail.com wrote: Hi, Thanks for the response. But while testing it is observed that if we execute FRR with a debugger then it doesn't work as expected. Mostly because the debugger places its own FRR in the FRR stack. That sounds like a concern to take up

Re: IEAMSCHD no FRR param

On 6/22/2017 4:17 AM, contactmura...@gmail.com wrote: I am new to SRBs & FRRs. I have a question regarding FRR Parameter address discussed over here. When said "If the SRB abends, its FRR receives the address of the FRR parameter area in R2 (or SDWAPARM)." Why is it (or SDWAPARM)? That means

Re: SRB Again

On 6/19/2017 2:02 AM, contactmura...@gmail.com wrote:> I was expecting 'SRB Abended, Inside FRR now' to be displayed before displaying 'Returned from SRB. In TCB mode now'. Because as per my initial understanding of SYNCH=YES, TCB will be suspended until SRB completes. But as soon as the abend

Re: Orphan control blocks

On 6/19/2017 11:51 AM, Donald Likens wrote: Does anyone see any problems with the following code... Updating free space pointer. To fully understand the possibilities for error you would need to show both sides of the processing, allocation and freeing. In cases like this there is almost

Re: Customer is Using CPACF (Crypto) purchased Crypto Express

On 6/19/2017 8:00 AM, Todd Arnold wrote: - If you need "secure keys" - keys that are protected by hardware that cannot be subverted, even by the highest-technology methods - then use CEX. (but if you need a lower level of security, consider CPACF Protected Key mode.) I would note

Re: Estae and the Linkage Stack

On 6/13/2017 2:55 AM, David Cole wrote: PRs do automagically cancel all ESTAEs created since the matching BAKR. There is a bit (in the BAKR's stack entry I think. I forget which and where.) that, when set on, causes an interrupt to occur when the PR is issued. This is how z/OS gains control so

Re: curious: Anybody still use ADDRSPC=REAL ?

On 6/9/2017 11:47 AM, Richards, Robert B. wrote: I seem to remember that V=R was used with MVS/XA running under VM/XA SF and you could bounce VM/XA SF and the guest would stay up. That was a *VM* V=R user, not a MVS V=R address space. Regards, Greg

Re: curious: Anybody still use ADDRSPC=REAL ?

On 6/8/2017 10:44 AM, John McKown wrote: This still seems to be supported in z/OS 2.2. Does anyone need to run a program V=R in today's world? I'm just curious because this support seems to be a "waste" of protect keys 10 through 15. Of course, if those keys were "freed up", what could they be

Re: Obtaining Storage in a Client Address Space

On 6/2/2017 10:59 AM, Joseph Reichman wrote: To clarify storage if not released is around for the life of the TCB I am assuming TCB ASCBXTCB is around for the life span of the address space The answer is no, so step carefully. ASCBXTCB is *not* a constant value for the life of the address

Re: Suspended SRB scheduled with SYNCH=YES?

On 5/25/2017 10:38 PM, Donald Likens wrote: SYNCH-YES does not say what happens when the SRB is suspended. I am hoping that the work unit will resume when the SRB is suspended. Now that I think about it, I do not think I should do this unless IBM says it will work (or you all say it will work

Re: ATTACH with RSAPF=YES

On 5/15/2017 11:27 AM, Paul Gilmartin wrote: What does the TSO TMP use to accomplish this? Extreme care ;-) It has been a while, but my memory is that the TMP stops all of the tasks above (or is that below?) it in the task tree and then passes the request to a special jobstep task (with

Re: ATTACH with RSAPF=YES

Be aware that what you are attempting to do is dangerous and has the potential to create system integrity exposures that would allow a problem state program to cause a system failure. I am not saying that it can not be done safely, because it can be. But to do it safely without creating a

Re: SETRP with DUMP=YES

On 4/22/2017 10:24 AM, esst...@juno.com wrote: Can I issue a SETRP DUMP=YES without other parameters. . Meaning I don't want to specify a retry routine nor do I want to specify a return code. I simply want to issue SETRP DUMP=YES and return to the next sequential instruction following the

Re: Paging subsystems in the era of bigass memory

On 4/18/2017 2:25 AM, Vernooij, Kees - KLM , ITOPT1 wrote: As I said, I remember reading this a long time ago, I don't know the details anymore, whether the source was reliable and whether it is still working this way. Only a DB2 internal expert should be able to tell. ... On 12 April 2017

Re: Paging subsystems in the era of bigass memory

On 4/11/2017 3:26 PM, Paul Gilmartin wrote: My understanding, ancient, probably outdated, and certainly naive is that there is little communication between GETMAIN/FREEMAIN and the paging subsystem. If a program touches a page that was never GETMAINed no error occurs; simply a page slot is

Re: Paging subsystems in the era of bigass memory

On 4/11/2017 1:46 PM, Jesse 1 Robinson wrote: Part of the problem, I learned some time back at SHARE, is that there is no mechanism to 'reclaim' page slots that no longer need to remain on disk. Once storage gets paged out, it sits there like a sandbag until the owning task is stopped.

Re: Paging subsystems in the era of bigass memory

On 4/11/2017 2:24 PM, Blaicher, Christopher Y. wrote: It has been a while since I worked on DB2, but it is sounding like your buffer pools are too big. With large memory systems everyone should have all of the production (and, ideally, test systems too) buffer pools define with PGFIX(YES)

Re: 64 bit execution above the bar

On 3/27/2017 3:59 PM, Paul Gilmartin wrote: It has been discussed here for a while. You could disable interrupts, branch to code above the bar, and branch back later. (I suppose the Old PSW was unconditionally scrunched.) More recently, interrupts above the bar are tolerated, but no system

Re: Problem reading GTF trace output

On 3/16/2017 2:30 AM, kalda0...@gmail.com wrote: > When I try to format the trace in IPCS the following error is received: > > BLS21082I DSNAME('SYS1.TRACE')I/O error > BLS21081I 0AB1,D,SYS00010,READ,OUT OF EXTENT,TTR UNKNOWN,BSAM > AHL10004I Input is not a GTF trace dataset. > AHL10009I No

Re: INIT terminated at end of memory

On 3/13/2017 6:00 AM, Barbara Nitz wrote: According to the books, IEF743I means "System action: The job and address space end." Unfortunately that does not seem to be the case. There is no indication that I can find in hardcopy log that the address space (Initiator) got restarted, and the dump

Re: Transactional Execution - anybody used it?

On 3/6/2017 3:15 PM, Jim wrote: I've used TBEGIN and vaguely remember reading up on TBEGINC but never ever tried it .. I'll have to hit the foils again .. My recommendation is that whenever possible, use a constrained transaction (aka, TBEGINC). It is guaranteed to complete successfully,

Re: JCL IF Condition - I'm Missing Something

On 2/22/2017 2:19 PM, John McKown wrote: ​But I agree that // ELSIF or // ELSEIF would be superior. DEFAULT / OTHERWISE is simply after the last ELSE. Perhaps instead of // IF, IBM should have have // CASE? Ahhh, but will your company *pay* IBM more $$ for z/OS if this functionality were

Re: Default Storage Subpool and Integrity

On 2/22/2017 12:57 PM, esst...@juno.com wrote: That other programs can read but not update. . Lets say I use KEY 4 as an example. If I issue a STORAGE OBTAIN with key 4 the system should use a default subpool. From an Integrity perspective is it acceptable to use the default subpool or would it

Re: VSMLIST

On 2/22/2017 10:15 AM, Joseph Reichman wrote: I know if you specify GSPV or SHPSV on the attach tasks can Share ? A subpool If this is not specified on the attach would a subtask get a S0C4 for referencing storage Obtained by the originating task No. A subpool is a logical grouping of

Re: VSMLIST

On 2/22/2017 7:17 AM, Joseph Reichman wrote: I am trying to reference storage that I ( my TCB didn't necessarily obtain ) Sometime I think if this storage has been paged out I would get a S0C4 pic 11 If VSMLIST determines it has been getmain'ed Maybe I can PGSER FIX back in I just got 2.2

Re: DB2 Locks and WLM Blocked Workload Support?

On 2/6/2017 11:46 AM, Peter Hunkeler wrote: - Are the "DB2 latches" implemented as GRS latches? - Are row, page, tables space locks actually DB2 latches? In other words, would WLM be able to recognize a low priority job holding some DB2 locks is causeing delay so it can promote it? - What have

Re: Legacy code can cost you billions. Just ask an airline.

On 2/2/2017 8:20 AM, Blaicher, Christopher Y. wrote: I think this guy has something he wants to sell because while PARS was developed on a 7074, in the early 1970's it was evolved by IBM into ACP and TPF. The 360/65 and some other 360 and 370 machines had the capability to run a 7074

Re: IEAVPSE2 in type 2 SVC

On 1/19/2017 9:24 AM, Greg Dyck wrote: Many, many, moons ago type 2 SVCs were managed differently from type 4 SVCs. It's a fuzzy memory, but I believe they had to be 2K or less in size and were loaded from SVCLIB transiently into a common 2K area. That lead to restrictions for them

Re: IEAVPSE2 in type 2 SVC

On 1/19/2017 7:55 AM, Joseph Reichman wrote: I used to work for Vendors I now work in applications Assembler I write internals code to keep those skills sharp If you look at the doc for in the Authorized Assembler guide I believe chap 23 It says type 2 SVC can not suspend their caller I am

Re: VSAM: Why MAXLRECL?

On 1/11/2017 3:30 PM, Frank Swarbrick wrote: Is there a downside to always defining VSAM files with a MAXLRECL of 32761, which seems to be the largest value for this parm for an UNSPANNED dataset? I believe it will force your CI size to be 32K which is not something I would want to do unless

Re: "task level" TIOT & XTIOT? A crazy thought?

On 1/10/2017 11:30 AM, Charles Mills wrote: The single TIOT is a limit to "virtualization." Certainly the function could be useful. While conceptually it seems easy to do, where the rubber meets the road in allocation, access methods, SMF accounting, and more, it would be a very

Re: Do the Name/Token Pair callable services need R13 to point to save area?

On 12/22/2016 1:47 AM, Peter Hunkeler wrote: When I get control, R13 points to a save area, which my code will use, but I do not yet have storage for another save area before calling IEANTRT, so I cannot change R13. The Name Token Retrieve service uses BAKR to save and restore the caller's

Re: COBOL inline CPU timer

On 12/21/2016 2:59 PM, Charles Mills wrote: When does ECTG come along? I've got high-level notes on the various z architecture levels but the "extract-CPU-time facility" is not in my notes. For those who still remember S360 architecture ;-), it is a recent addition. z9-109, circa September

Re: COBOL inline CPU timer

On 12/21/2016 10:46 AM, Paul Gilmartin wrote: How does ECTG do that? Is there information in control registers supporting it? Does it work likewise on systems other than z/OS, such as Linux? VM guests? The high level answer is that ECTG atomically fetches 8 bytes of storage from one

Re: COBOL inline CPU timer

On 12/20/2016 5:58 PM, Bill Woodger wrote: If there's some way to make it more "accurate" for what I want, I'd be pleased. Use the assembler macro- TIMEUSED STORADR=xxx,ECT=YES This will call a *short* system routine (no PC, no SVC) which will use the ECTG instruction to calculate the

Re: MIPS Calculation formula

Is there some formula to calculate a MIPS usage from the next kind of data-source and volumes estimation: Keep in mind that MIPS stands for "Meaningless Indicator of Processor Speed"... long used, usually misunderstood, and often abused. On a current processor I can write one program that

Re: AW: Re: Does >4K PGFIX make sure the frames are contiguous?

On 10/19/2016 7:51 AM, Peter Hunkeler wrote: But the net seems to be, my assumption is wrong. If an area >4k is PGFIXed, then I need to find the real address of every page and cannot assume the real storage is contiguous. This is a correct statement. PGFIXing storage guarantees the page is

Re: Help with broken CB chain

You *can* *not* safely intermix the use of CDSG and PLO without using special protocols. This is clearly documented in the POPs. You *can* safely intermix CDSG and transactional execution. Regards, Greg -- For IBM-MAIN

Re: CEEDUMP possible following 'new' failure

On 10/7/2016 1:38 PM, Jim Mulder wrote: Since memterm does not access the storage of the address being terminated, there is no connection between IEFUSI and memterm. There is no requirement for any available storage in the address space being memtermed. Task termination, yes. Memory

Re: VSAM CA reclaim for RMM

On 9/29/2016 4:18 PM, Jesse 1 Robinson wrote: Ah, that's a point I'm still fuzzy on. When you say 'Control Areas first used after CA-Reclaim is turned on', does that mean that reclaim will not affect an old cluster until it has been (re)created? That makes a difference in how to roll it out.

Re: AW: Re: Would HiperDispatch likely delay heavy multitasking job?

On 9/29/2016 10:17 AM, Peter Hunkeler wrote: So there should be enough spare capacity for the system (LPAR) to to use. But it does not. The 7 vertical low CPs are mostly parked or unparked for only a few percent. I wonder why MVS is not using more CPs and more Capacity for that job. You

Re: Would HiperDispatch likely delay heavy multitasking job?

On 9/28/2016 11:29 AM, Peter Hunkeler wrote: Job in question is DB2 reorg utlility job which runs some 30 subtasks in parallel runs for 2 hours. RMF III (60s intervals) shows that the job mostly has a good workflow (80%+), is heavily using CP (often 80%-90%) and at the same time is heavily

Re: Internals of Catalog

On 9/13/2016 11:55 AM, Jake Anderson wrote: Can some one please explain the Catalog internals with respect to the VVDS and VTOC. At the 10,000 ft level... The catalog is a VSAM KSDS dataset that (mostly) points to the volume containing the dataset. The VTOC contains where on the volume, by

Re: Some confusion about SVC99, DALRTDDN and existing allocations.

On 8/6/2016 9:49 AM, Paul Gilmartin wrote: I don't believe there's a timing hazard; DYNALLOC will go to the end of the name space and wrap before it reuses the DDNAME you got. Dynamic allocation *will* *not* reuse the DDNAME. After generating a name it checks to see if it is already in use,

Re: TCB reference following DETACH

On 8/3/2016 1:10 PM, Charles Mills wrote: I am trying to shoot a problem. The code in question makes reference to a TCB shortly after issuing a DETACH for that TCB. Am I correct in my analysis that that is a S0C4 candidate? That once you issue a DETACH, the TCB is no longer necessarily valid?

Re: Deleting FRR

On 7/28/2016 1:00 PM, Joe Reichman wrote: I have a FRR covering a SRB it not a parameter on the SCHEDULE or IEAMSCHD but rather invoked inside the SRB. The documentation says to delete it just code SETFRR D,WORKREGS However I am guessing it has to be in the context of the SRB or in the FRR on

Re: RFE on TIOT Exceeded

On 6/21/2016 1:11 PM, Lizette Koehler wrote: After the discussion, I went ahead and put in a RFE for IEF240I TIOT Exceeded message. http://www.ibm.com/developerworks/rfe/execute?use_case=viewRfe_ID=90368 Knowing the amount probably won't help you resolve a concern, given the 64K hard limit on

Re: TIOT exceeded

On 6/18/2016 11:03 AM, Jake Anderson wrote: Is there a way to know if the DD chain has approached the end or it has approached the end of Chain. Is there a way to tweak the JCL to overcome TIOT exceeded values ? The TIOT is a fixed sized array of entries, not a chain. The size is defined in

Re: LINK and high order word of R1

On 6/13/2016 11:18 AM, Charles Mills wrote: Does that mean that for standard "old-fashioned" AMODE 31 72-byte savearea linkage I am obligated to save the high word of R1 before issuing LINK in a called program? If so, this would seem to be a compatibility issue for older code that uses LINK. Or

Re: Clarification of ECBLIST

On 6/8/2016 7:07 AM, michelbutz wrote: The XMEM post is being done from a FRR resulting from an abend in a SRB the SRB is the primary address space Putting an ECB in common storage is allowed, but great care must be taken when doing so. As has already been said, if issuing the POST from

Re: SRB SUSPEND exit curiosity

On 6/7/2016 8:41 AM, michelbutz wrote: Can someone tell me what the advantage of this Is then using IEAVPSE2 is it performance I think they both set up a SSRB SUSPEND/RESUME w/TOKEN *only* works for SRBs. Pause/Release works for both tasks and SRBs. Performance wise, SUSPEND/RESUME w/Token

Re: SRB SUSPEND exit curiosity

On 6/6/2016 6:54 AM, Steve Smith wrote: > I'm wondering what an SRB SUSPEND exit is really good for. The Services Guide and Reference state that it is required, and that it is supposed to save the SUSPEND token, and decide whether to allow the SUSPEND. I can't see why the SRB mainline

Re: SUSPEND/RESUME is slower than WAIT/POST. PAUSE/RELEASE is slower than both

On 6/4/2016 6:34 AM, Ed Jaffe wrote: So, the local lock is obtained in only a subset of Pause/Release scenarios? Ed, The local lock is *never* obtained for single PET Pause/Release processing. For multiple PET Pause/Release it is obtained to serialize creation of an address space related

Re: Release code paramter of IEAVRLS2

On 6/3/2016 2:24 AM, michelbutz wrote: Does it have to be a different value on every call If I understand your question, the answer is no. You *might* use a different value to indicate the PET was released for a specific reason, such as 0 for process work, 2 for error occurred, and 3 for

Re: Release code paramter of IEAVRLS2

On 6/2/2016 9:43 PM, michelbutz wrote: So it is the same parm as the one in the pause Yes. . IEAVPSE/IEAVPSE2/IEA4PSE/IEA4PSE2 release_code . IEAVXFR/IEAVXFR2/IEA4XFR/IEA4XFR2 current_du_release_code will be set to the value specified by one of the following- .

Re: Release code paramter of IEAVRLS2

On 6/2/2016 7:08 PM, michealbutz wrote: I have a question about the 3rd paramter of IEAVRLS2 target_du_release_code it is specfied as 4 bytes. Is this the same as the 4th paramter of the Pause service release code this is specfied as being 3 bytes Sigh... I checked the code and the description

Re: AW: Re: Questions on DPMOD

On 5/29/2016 10:24 PM, Peter Hunkeler wrote: Thanks, Greg, for the pointer to the presentation. I did not read anything which would contradict my understanding. I conclude below text, which I cited previously, needs some rework. I' ll submit an RCF. > Back to the OP's topic. I read in

Re: Questions on DPMOD

On 5/26/2016 4:24 PM, Charles Mills wrote: So this is inherent in the guts of MVS -- not something in PROGxx or somewhere like that? Yes, it is inherent in the guts of MVS. There is no external knob to change the initial value that a jobstep task starts at. But there are multiple ways that

Re: AW: Re: Questions on DPMOD

On 5/26/2016 11:19 PM, Peter Hunkeler wrote: This makes my wonder. My understanding, which maybe is not entirely correct, is that the dispatcher only looks at the work unit queue (WUQ) for the type of processor, when a processor needs new work. It picks the first work element block (WEB) form

Re: Questions on DPMOD

On 5/26/2016 2:51 PM, Charles Mills wrote: 1. Where is the original dispatching and limit priority for the jobstep task set? How do I determine (not with an API at runtime, but in advance with a command or looking at a parm member) what it is presumably going to be? Sigh... the initial

Re: SUSPEND/RESUME is slower than WAIT/POST. PAUSE/RELEASE is slower than both.

On 5/26/2016 10:29 AM, Jerry Callen wrote: I wrote a simple test program to compare the performance of WAIT/POST and pause elements. The program has two tasks and simply ping-pongs back and forth between them (no overlapped execution). Each task has a synchronization gadget, either an ECB or a

Re: AW: Re: ADRDSSU PRINT function not listing KEY (of CKD) as separate item?

On 5/25/2016 11:16 AM, Peter Hunkeler wrote: Yet still the count field is printed on a line by its own. This is why I had expected the key field to printed separately from the data field as well. Someone made a decision 30 years ago on how DFDSS PRINT should format the record information,

Re: Interesting (?) 64-bit assembler surprise

On 5/19/2016 9:54 AM, Phil Smith III wrote: ... The surprise here was that since R14 had something in the top half of the grande register, Bad Things resulted (S0C4) on the line with comment "ADDR SYST LINKAGE TABLE". This seemed.unintuitive. Are we the only ones who were (or have been)

Re: Dynamic CPU ADD to a z/OS lpar

On 5/12/2016 10:17 AM, Mark Zelden wrote: On Thu, 12 May 2016 07:30:03 -0400, Richards, Robert B. wrote: I do have a follow-up question Is anyone aware of a downside to over specifying reserved CPs? LCCA/PCCA storage. But the default CBLOC has been VIRTUAL31

Re: ADR309E Message during Restore

On 5/4/2016 10:41 AM, Carlos Bodra wrote: SOURCE AND TARGET DEVICE CAPACITIES DO NOT MATCH. CYLINDER CAPACITY OF SOURCE VOLUME 2721, TARGET VOLUME 0D0B. This tells me that source volume has 2721 cylinders and target volume has 3339 cylinders (0d0b). No, the source volume has 10017 cylinders

Re: High number of samples seen in IEAVEPS1. What does this tell me?

On 5/3/2016 4:30 AM, Peter Hunkeler wrote: I'm analyzing a job using CA's MA-Tune (similar to Strobe). Question is if there is that could be optimized. Looking at the MA-Tune reports which are based on 100 samples per second for 1 minute, I see that the job is seen in IEAVEPS1 for some 20%.

Re: SRB dispatching question

On 5/1/2016 3:45 PM, michelbutz wrote: Hi If a nonpreamtable scope=global SRB does a pause And another SRB is scheduled does it get dispatched ? Being non-preemptable means that z/OS won't take control away from the unit of work without cause. Cause being something like a page fault

Re: SRB dispatching question

On 5/2/2016 12:54 PM, Blaicher, Christopher Y. wrote: What parameters were on the IEAMSCHD macros for the two SRB's? If the LLOCK=YES parm is set on both, then there is your problem. A Pause is not allowed while holding *any* class of lock. The Pause request will fail. Greg

Re: can a program determine the capacity setting of a z-box?

Tony, If you can get into supervisor state, use the STSI instruction. Under z/OS the CSRSI service uses STSI to provide the data that it returns to problem program state requestors. I don't know if VSE provides any equivalent service. Greg On 4/25/2016 10:55 AM, Tony Thigpen wrote: Is

Re: Setting up z/OSMF under 2.1

On 4/20/2016 7:25 PM, Steve Beaver wrote: DISASM is a nice little "gimme" but I don't think it's been updated in years. You might find yourself Doing a lot of coding of DISASM to get it functional for 32 and 64 bit code I believe you are thinking about a different "DISASM" than the support

Re: PDSe Question

How to determine the length of the block for a BSAM/BPAM RECFM=FB dataset is fully described in the z/OS DFSMS Using Data Sets book, Processing Sequential Data Sets, Determining the Length of a Block. Greg

Re: Fwd: Tech News 1964

What big and new (30 years old or less) companies use mainframe? Google? Facebook? Netflix? Maybe not directly, but they are certainly dependent on banks, insurance companies, the SEC, and others to accurately, quickly, securely, and with integrity and safety, maintain information about

Re: Microprocessor Optimization Primer

Rule 3 says there are events, some explicit (BCR 15,0) and some implicit (interrupts), that force conceptual completion to occur, over and above those required by rule number 1. These rules are for storage consistency, especially between multiple processors. Registers are slightly different

Re: Microprocessor Optimization Primer

Operand fetches and stores must appear to occur in proper order. So is it saying that the machine obeys Rule 1? I will bet dollars to donuts that that is not the case, that the machine performs read operations before logically preceding write operations, and that a program can be run to

Re: CSVFETCH exit

As to the question, what can you do with the information CSVFETCH makes available: can I write an SMF record from CSVFETCH? You should be able to use SMFEWTM BRANCH=YES can write a SMF record from the exit. Greg -- For

Re: SHOWzOS and PTFs UA9074n

On 1/24/2015 9:33 AM, J O Skip Robinson wrote: Yikes. I don't fully understand the impact of OA44240. The APAR text does not mention UCB lookup. We have several RYO and an indeterminate number of ISV programs that utilize the 'traditional' UCB lookup process. Will everything fall apart when

Re: Overlaid VCON in load module

From what we can see the address that ends up in the VCON is the displacement from the beginning of the module (the value presumably placed their by the binder) plus twice the load point. Has anyone seen this happen before? Is there an undocumented requirement to single thread multiple LOADs

Re: IBM United States Announcement Letters

On 1/14/2015 12:28 PM, Mike Schwab wrote: (So it looks like any individual task that is CPU bound and limited to one core will take twice as long.) What you state is always true for temporal multithreading, which timeslices the execution of CP x with CP y on a single core. But for

Re: Abend S602-0 when in AMODE 64

On 1/12/2015 7:52 AM, Donald Likens wrote: Can anyone explain why the following code did not work in AMODE 64 but works in AMODE 31? Yes... bit 32 of R15 on entry to your STIMER exit routine is on. In AMODE 64 the LA of the ECB address propagates it into R1. Thus R1 indicates it is a

Re: IEC190I message

Make sure the storage for the DCBE has the same storage key as the DCB, contains the constant 'DCBE' in the first 4 bytes, and has a minimum length value of 56 in the halfword that follows the constant 'DCBE'. Greg -- For

Re: SDUMPX questions

On 1/6/2015 8:47 AM, Binyamin Dissen wrote: SDUMPX DCB=OSVCDDCB, + ECB=(DUMPECB,WRITE),+ SUMLIST64=SUMLIST64,+ LIST64=(R7),