sue an SVC and it will make its way to the SVC target routine, otherwise
you can't (the abend SVC can be considered an exception).
The environments for issuing any service should be clearly documented as part
of the documentation for that service.
Peter Relson
z/OS Core Te
SM 14,15
Or you could have done something like
LGR 15,0
NILL 15,x'FFFE'
SAM64
BASR 14,15
Peter Relson
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orage.
Regarding the client's having an ALET to access storage in the server address
space: that is certainly possible. I don't know how "common" that is. You could
be right that it is "quite often".
Peter
the address, such as
ECB=ADDRESS_OF_MYECB, you'll get the address of ADDRESS_OF_MYECB. Things won't
go well.
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invocation within a macro so in the absence of PRINT MCALL doesn't get shown in
the listing.
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erly got 378-1C.
That input matches the explanation for 378-1C.
I hope there is no use of LE and C writeable static in this address space. That
uses subpool 1 and it would be unlikely to be a good idea to free the whole
subpool in such a case.
Peter Relson
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EL,OSREL=SYSSTATE
USING @DATA,12
CSVAPF REQUEST=LIST,ANSAREA=(2),ANSLEN=(3)
CSVAPF REQUEST=LIST,ANSAREA=AA,ANSLEN=AL
@DATADS0D
AA DSD
AL DSF
END
Assemble this and look through the expansions for things like LAE and STAM.
Peter Relson
z
e. But maybe you have a better goal in
mind.
For almost all services the rule is that an input AR (or input ALET) is ignored
if the caller is not AR mode. There are exceptions.
Peter Relson
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The obvious first thought is "the hardware name is not DR" on the system where
the definition is not working.
Look at ECVTHDNM and see what it says (among many choices, you could write a
tiny program, use REXX, use TSO TEST, use IPCS ACTIVE, use IPCS upon an SVC
Dump)
Peter Relson
obal macro variable that you set once for the whole module (perhaps via
SYSSTATE), as opposed to via a macro keyword specified on each individual macro.
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that expansion on older releases (perhaps limited to those older
releases that are still supported). Now that only z/OS 2.4 and up are supported
(other than extended support), there are opportunities to use some instructions
that were not previously OK to use.
Peter Relson
z/OS Core Technology Des
us" is uninteresting without Rent since it is just another case of "not
reentrant". And Reus with Rent is the same as Rent to z/OS.
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is fine.
If you need access to storage containing the parameter/data that was passed to
the syscall, that data won't be in this dump unless the program happens to wait
after the call.
Peter Relson
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s once per task in
a multi-tasking application). Also, be sure in a non-reentrant module to
separate your "data" from your "code" (separate cache lines) to avoid
significant degradation due to "store into instruction stream" effects.
Is user key CSA still available?
to
make sure to include secondary and/or home address spaces in the dump.
I don't know if that helps you or not.
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A expression, but not with it, then you'll
need to figure out what's wrong with that expression.
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Gil wrote
The PDF was in two-up format
and I failed to read the second column.
Just curious: which book was that? I know that PoP is, but I didn't realize
there were others.
Peter Relson
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her to go with "thumbs up" or "thumbs down"
but I suspect I know what most will choose.
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sterisk so that all they have to check are the "n"
characters preceding the asterisk in the pattern).
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For a given ASID, look at OUCB +B0. JES2, STC or TSO should appear.
That is field OUCBSUBN which is not a programming interface. Its commentary
leads me to think that there are additional possible values.
Peter Relson
z/OS Core Technology Design
able), since you can serialize against that
storage being freed by having the CPU lock, then verifying that the ASCB is
valid via LOCASCSB, and checking that ASCBFAIL is not on. If all is fine, then
the ASCB/ASSB cannot be freed until you release the CPU lock.
Peter Rels
uld pay
attention to IRRPRMxx. Started tasks that pay attention to a parmlib generally
have a parameter by which you identify the parmlib member to pay attention to
upon the start.
Peter Relson
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out column 72 to avoid confusing subsequent parsing.
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An alternative (no comment on relative performance) for this case since you
know the intended data is:
SPKA user-key
MVI first-byte
MVC overlapping
SPKA your-key
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look at the result such as by DISPLAY PROG,LPA,MOD=xxx?
At least with that you can get an idea of what your expectations should be.
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lable one)
Then there is dynamic dump allocation which, apparently, is not active.
This relates to DUMPDS (DD) command options such as DD ALLOC and DD ADD. And
you can define the naming pattern for the dump data set.
Peter Relson
z/
z-Architecture, locations 0-7 were the restart old PSW, generally 0's
until a restart had been done (if ever).
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MMA resolved to a displacement with no base register
Peter Relson
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The references to TS7700 Statistical Data Format appear to be to SMF 94.
The query was SMF 194 which, I believe, is not owned by IBM.
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t TSO is to consider
as an authorized command. PARMLIB is documented as an authorized command (but I
don't know if that is "built-in" or needs to be specified).
Peter Relson
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data store".
Can you clarify?
Peter Relson
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Mike Schwab wrote
Most exits are assembler, right?
Most system exits, surely. Metal C (or anything that does not need an
environment such as C and REXX do) is another choice typically.
Bob Bridges wrote:
Although I gather z/OS now allows them to be in REXX.
Certainly not in general. Most sy
de effects within the current
IPL,
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The PER SLIP matches only a non-zero register with zeros in it like this:
L Rx,PSAAOLD(0,4) <-- SLIP will match if R4 contains zeros
And, also, will match for this if R4 contains zeros:
L Rx,PSAAOLD(4,0)
Peter Relson
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ue and see what you get.
Peter Relson
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uot; (especially when the possible values are not knowable to a parser)
to be an "INVALID KEYWORD" (as opposed to if the user had coded PLANN(DSNTEP1)
it might have complained that PLANN was an invalid keyword.
Peter
han
"careless"). Thank you for submitting feedback to get that corrected.
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text as the basis for a display.
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iated with that RB.
Of at least as much importance: Show the data. Including the 8-byte
translation exception address.
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that routine as REFReshable and
put it in SYS1.LINKLIB.
This behavior, when marking the module as refreshable, applies only when the
REFRPROT option of PROGxx is active.
That applies system-wide. As long as that is OK, and you have control of
setting REFRPROT, have at it.
Peter Relson
z/OS
for placing a reentrant program into key 0
non-fetch-protected storage depend on authorization and various system-wide
options, along with the possibility of doing an ATTACHX with the KEY=NINE
parameter (which will place into key 0 storage without relying on
authorization).
Peter Relson
z/OS
so can get away with using the 4-byte name.
These days, the L/N/SRL has many better alternatives, such as
LLC (of the 2nd byte of RBOPSW) / NILL (to clear the low 4 bits if for some
reason you need to do so).
Peter Relson
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-
e a dataset is being opened. And as you showed you
have TAPEAUTHDSN=YES.
I have no idea if temporary data sets "count" when OPEN is processing, but it
wouldn't shock me.
Peter Relson
z/OS Core Technology Design
for
the caller's regs (for which the answer is different than the psw/key, but
similarly depends on the type of the SVC.
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to what we refer to as low-core protect).
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u'd have to check for SDWAPRIM =
current primary ASID (such as by using EPAR to extract the current primary ASN).
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, serialization may be required when
accessing something other than your address space's data.
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important to identify to which RB you refer.
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IEANTRTR, exactly like IEANTRT, has authorization-related "limitations" and
authorization-related opportunities.
If you look closely, the non-authorized IEANTRT shows that the level parameter
has 4 choices. The authorized IEANTRT shows that the level parameter has 7
choices. The same is true for
You can cancel an STIMER via TTIMER CANCEL.
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y
do not need to build/touch IQE/IRB. The parameters on SCHEDIRB (such as EPPTR,
MODE, KEY et al) generally cover all the pieces of data that you would set in
the IRB. They do cover all that you showed in your code example. It is
documented that SCHEDIRB is sugg
there (which
locates the STAE Control Block, SCB).
When you are providing a code example and there is any possibility that someone
will want to assemble it (perhaps even to try it), please make sure it
assembles or provide guidance on what to do to get it to assemb
these are sometimes provided by RTM; SDWAMODN and SDWACSCT are often
set by the recovery routine itself.
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overy (and options)
that you are using. SDWAFMID is set in only a few circumstances, it seems (such
as DAT error), so you won't find that helpful generally.
Note that none of this discussion mentioned (or had a reason to mention) an
RB/XSB pair.
Peter Relson
z/OS Core Te
what
you want (whatever that is) in all cases. And no one is going to try to figure
out the exceptions.
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an see that the WKAREA default, to register 1, requires that you have set
up AR1 appropriately (to 0 would be most appropriate)
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older time stamp than the one
already captured).
If these two threads were serialized by an ENQ against each other the above
scenario would not happen because thread two would not have been able to get to
the point of capturing its clock value.
Peter Rels
th an address and it
finds it (based on such things as your search criteria - JPALPA or just JPA,
for example), then you have a change to get an XTL64.
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In contents supervisor speak, an extent list contains header information and
then information about the length and address of each (module) extent (whether
mapped by IHAXTLST or IHAXTL64.
As the name implies, XTL64E_EXTENTADDR contains the address of the extent for
this entry. And, not surpris
AFAIK (which admittedly might not be "far" enough), TFP prior to z16 had no
information relevant to STSI.
There are now TFP hardware records that apply variable capacity for which STSI
surfaces information. Possibly QVS should surface that too and might be
enhanced to do so.
Peter Relsonz/OS Cor
The fact that registers are saved (or at least land) in the "new RB" and the
PSW in the "old RB" was described many posts earlier. That applies in all cases
where a new (not "first") RB is created. Note that just when that saving
happens can be kind of funky for a case such as XCTL(X).
The prob
It was my understanding probably erroneously that when a RB I guess I am
talking about a PRB gets interrupted and that can happen in one of two
instances
1) An SVC
2) A Program check e.g. S0C1,4
It is true that the understanding is erroneous. There are many more cases where
any RB can be i
How about: STSI returns a lot of data that is not returned by SYSEVENT QVS? (or
so I assume)
How about: SYSEVENT QVS returns a lot of data that is not provided by STSI? (or
so I assume)
Now, if you were to ask about specific fields in SYSEVENT QVS, I think for
certain ones the answer is "none"
ified, they could have the same trailing characters, but
the first (numeric) characters would differ.
If you are referring to data spaces owned by different ASIDs, you might need to
use an ASIDLST and identify the proper set of ASIDs.
intent is that the security product know
what to do to provide you the "decrypted" info
Charles M helped me realize that I was mis-thinking. It's the utoken that can
be "encrypted", not the ACEE.
Thanks, Charles.
Peter
as-is. It's not truly encrypted such that you need some
cryptography to decrypt it, but the intent is that the security product know
what to do to provide you the "decrypted" info
Peter Relson
z/OS Core Technology Design
---
Are you implying that an ESTAE(X) routine with SDWALOC=31 is guaranteed an
SDWA and there is no reason to check R0 for 12 and alternate code paths?
Jon P did write what I meant. Answer: no, it just makes it a lot more likely
that the storage obtain for the SDWA will succeed.
Peter Relson
z/OS
ve to deal with multiple such STIMER's
associated with a task). A single exploiter can use STIMER TASK within the same
task that has multiple exploiters using STIMERM REAL
Using STIMER REAL to monitor task CPU time is not a good fit.
Peter Relson
z/OS Core Te
;CPU Time limit" (most would not think of it that way if
they see only "time limit").
And there is no "time interval". The STIMER remains in effect as long as it
takes to use that much CPU time.
Peter Relson
z/OS Core Technology Design
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use SDWALOC31=YES (as is the
case always for such recovery as ESTAEX and ARR).
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ontrol via SYNCH(X) and thus begins running in a PRB
created by SYNCH processing.
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e that error to user recovery.
If you're asking about a space-switch PC, that restricts the choices, but the
approach applies.
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trol to an ESTAE. And that's
why the PRB for your ESTAE is separated from the PRB for your mainline by an
SVRB for the SVC D that got you into RTM.
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possibly a message such as HZS0025I that mentions BPX1QDB or BPX1ENV)
HZS0109E IBM HEALTH CHECKER FOR Z/OS ADDRESS SPACE USER IDENTITY DOES NOT HAVE
ACCESS TO z/OS UNIX SYSTEM SERVICES
Peter Relson
z/OS Core Technology Design
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sdawgrsv wasn’t in either TCB regs or rb regs
If you had done what I written, you would have looked at all the relevant RBs,
not only at a single RB.You apparently looked at the oldest RB. That sounds
like it was the RB associated with the "mainline". Did you look at the
next-oldest RB?
TCBRBP p
Simple experimentation will show what you need to know about what is saved
where.
For example, suppose your mainline links to another routine.You mainline's RB
and the LINK target's RB can be examined.
Or suppose your mainline has an ESTAE and abends.You can examine the mainline's
RB, then the (
>Could you share why it matters to you if there is a linkage stack entry
(whether before or after getting to the "true routine", even if my guess is
right about what you think of as the "true routines")?
Performance.
That doesn't provide much insight.
What the callable services stub and the
Joe R wrote
I got to a X'89' is a header the doc say that decrementing that would
bring to a new linkage frame I specifically remember looking - 32 bytes from
there and it was all zeros.
Not having ready access to that document, but knowing who wrote it, I'll bet
that it does not say that. It
Here is the SDWA as you can see the PSW matches how come the registers
don't?
Because the registers are not saved in the same RB that the
scrunched-to-8-bytes PSW is saved in.
Peter Relsonz/OS Core Technology Design
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The technical reason "why" is because it would be very difficult to do, would
have adverse performance effects for the system, and there is not at this point
a business case for providing it. So you're not going to get it just because
you think it sounds nice (and even because it sounds "logical
Binyamin wrote does that means that the CSFDLL functions do not create a
linkage stack entry before calling the true routines/
Could you share why it matters to you if there is a linkage stack entry
(whether before or after getting to the "true routine", even if my guess is
right about what you t
You originally asked about the syntax error message.
The syntax of the command used was incorrect, and I think the syntax error
message was pretty reasonable.
F HZSPROC,ADDREPLACE,CHECK=(IBMUSS,USS_HFS_DETECTED),USS=YES
ASA101I SYNTAX ERROR: WAS SEEN, WHERE ONE OF 826
(CHECKROUTINE DATE EXEC
ng the PSW as "from a linkage stack entry", that would be good to know.
And for that, the information I mentioned above (plus all the data from the
RBs/XSBs) would be needed for diagnosis.
Peter Relson
z/OS Core Technology Design
primary address space when the recovery was established)
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last doing (and thus how the recovery routine needed to react). The recovery
routine of the PC target would typically not care about where the PC was issued
from. A diagnostician, of course, might well care about both, but they would
typically be looking at a dump.
Pe
acterize as supervisor state or PSW key 0-7). SRBs (key 0
supervisor state typically) can run in unauthorized address spaces. The
authorization of the address space is not related to the authorization of an
SRB running within that addres
please help
others too by making sure that the flaw is pointed out to those in charge of
changing it (and pointing out on IBM-Main is generally not as helpful as
getting the publication itself updated).
Peter Relson
z/OS Core Technology Design
--
n-authorized address space at various points code runs
authorized (such as after an SVC or a non-space-switching PC that is defined to
execute in supervisor state and/or a system key).
Peter Relson
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---
R15 has bit 63 on I would assume
Yes, reg 15 would be set up to be suitable for use by BSM 0,15 (AKA
"pointer-defined")
hence having bit 63 on when you want the target to be AMODE 64
(as you would need for an address above 2G).
Peter Relson
z/OS Core Technol
to
the target located by reg 15.
The system trace entry for that retry contains the value from reg 15, not the
address of CVTBSM0F.
Aside from the trace entry manipulation, you could accomplish this by yourself
with some other register if you had a need.
Peter Relson
z/OS Core Te
s has an address >= x'7000', that correlates
to "the extent is actually above 2G" and in that same entry the length is "1"
(these being indicators that the real extent definition is in the XTL64 because
it does not fit in the XTLST.
Peter Relson
z/OS
would now be x'0C4000'.
Special-Case: if you have established SPIE/ESPIE for a program interrupt, that
exit will get control even if there is a newer-established ESTAE-type recovery
routine.
Peter Relson
z/OS Core Technology Design
-
low).
It could be a dump of some type. In the "freeing storage" case,
maybe the recovery isn't so much about freeing the storage but more about
capturing data to help someone figure out what went wrong
Peter Relson
z/OS Core Technology Design
-
A is in the primary address space of the recovery routine given control
(for an FRR, it's in common storage, so the ALET is not important).
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a page fault
doesn't even need to be backed up to get to the right place to re-execute.
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e this". Maybe you
have embedded within a structure; maybe your program has a highly limited
amount of dynamic storage available. Those could be cases where you cannot
"tolerate this".
Peter Relson
z/OS Core Technology Design
tation.
I.e. do your due diligence and "prove it".
Lack of PLISTVER=MAX on the list form can result in the area for the parameter
list being too small, with the result that the execute form expansion overlays
something following it which perhaps something relies upon.
Peter
your
program, you can use the LOCTR directive to help to "move" data to a separate
area. You might have an area for your "code" and an area for your "static data"
and an area for your "dynamic data&qu
does require that all the routines have access to the
field where the current level has been saved (so they can increment/decrement
as appropriate), unless (for example) each routine has a recovery block that
keeps track "for it" and some over-arching code can run these blocks and
det
system LX
does not require use of ETCON (aside from by the creator).
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