Re: [Intel-gfx] [PATCH 2/4] drm/i915/skl+: calculate ddb minimum allocation (v6)

Reviewed-by: Kumar Mahesh On Tuesday 31 May 2016 10:28 PM, Matt Roper wrote: From: "Kumar, Mahesh" don't always use 8 ddb as minimum, instead calculate using proper algorithm. v2: optimizations as per Matt's comments. v3 (by Matt): - Fix

Re: [Intel-gfx] [PATCH 2/4] drm/i915/skl+: calculate ddb minimum allocation (v5)

On Friday 27 May 2016 03:43 AM, Matt Roper wrote: From: "Kumar, Mahesh" don't always use 8 ddb as minimum, instead calculate using proper algorithm. v2: optimizations as per Matt's comments. v3 (by Matt): - Fix boolean logic for !fb test in skl_ddb_min_alloc()

Re: [Intel-gfx] [PATCH 3/4] drm/i915/skl+: calculate plane pixel rate (v4)

Reviewed-by: Kumar Mahesh On Tuesday 17 May 2016 04:22 AM, Matt Roper wrote: From: "Kumar, Mahesh" Don't use pipe pixel rate for plane pixel rate. Calculate plane pixel according to formula adjusted plane_pixel_rate = adjusted

Re: [Intel-gfx] [PATCH 4/4] drm/i915/skl+: Use scaling amount for plane data rate calculation (v4)

Reviewed-by: Kumar Mahesh On Friday 20 May 2016 03:33 AM, Matt Roper wrote: From: "Kumar, Mahesh" if downscaling is enabled plane data rate increases according to scaling amount. take scaling amount under consideration while calculating plane

[Intel-gfx] [PATCH 3/3] drm/i915/gen9: WM memory bandwidth related workaround

changes in series Changes since v3: - Rebase the patch - Address Paulo's review comments - introduce ww_mutex to protect WM operations - Protect system memory bandwidth calculation with ww_mutex Changes since v4: - drop goto label - fix compilation warning Signed-off-by: Mahesh Kumar <mahesh1

Re: [Intel-gfx] [PATCH 1/3] drm/i915/bxt: Enable IPC support

Hi, On Tuesday 31 January 2017 09:26 PM, Ander Conselvan De Oliveira wrote: On Tue, 2017-01-31 at 20:27 +0530, Mahesh Kumar wrote: This patch adds IPC support for platforms. This patch enables IPC only for BXT/KBL platform as for SKL recommendation is to keep it disabled. IPC (Isochronous

[Intel-gfx] [PATCH 2/3] drm/i915: Decode system memory bandwidth

inputs - Addresses review comments Changes from v3: - Fix compilation warning Changes from v4: - Address review comments - Round-off the frequency & bandwidth results Signed-off-by: Mahesh Kumar <mahesh1.ku...@intel.com> --- drivers/gpu/drm/i915/i915_d

[Intel-gfx] [PATCH 3/3] drm/i915/gen9: WM memory bandwidth related workaround

changes in series Changes since v3: - Rebase the patch - introduce ww_mutex to protect WM operations - Protect system memory bandwidth calculation with ww_mutex Signed-off-by: Mahesh Kumar <mahesh1.ku...@intel.com> --- drivers/gpu/drm/i915/i915_drv.c | 1 + drivers/gpu/drm/i915/i915

[Intel-gfx] [PATCH 1/3] drm/i915/bxt: Enable IPC support

: - Re-enable IPC after suspend/resume Signed-off-by: Mahesh Kumar <mahesh1.ku...@intel.com> --- drivers/gpu/drm/i915/i915_drv.c | 4 +++- drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/intel_display.c | 1 + drivers/gpu/drm/i915/intel_drv.h | 1 + drivers/gpu/dr

[Intel-gfx] [PATCH 0/3] Enable IPC & WM related WA's

This series include remaining patches from following series to enable IPC and Enable/update memory BW related WA's for WM. https://patchwork.freedesktop.org/series/15562/ Mahesh Kumar (3): drm/i915/bxt: Enable IPC support drm/i915: Decode system memory bandwidth drm/i915/gen9: WM memory

[Intel-gfx] [PATCH 1/3] drm/i915/bxt: Enable IPC support

: - Re-enable IPC after suspend/resume Signed-off-by: Mahesh Kumar <mahesh1.ku...@intel.com> --- drivers/gpu/drm/i915/i915_drv.c | 4 +++- drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/intel_display.c | 1 + drivers/gpu/drm/i915/intel_drv.h | 1 + drivers/gpu/dr

[Intel-gfx] [PATCH 0/3] Enable IPC & WM related WA's

This series include remaining patches from following series to enable IPC and Enable/update memory BW related WA's for WM. https://patchwork.freedesktop.org/series/15562/ Mahesh Kumar (3): drm/i915/bxt: Enable IPC support drm/i915: Decode system memory bandwidth drm/i915/gen9: WM memory

[Intel-gfx] [PATCH 3/3] drm/i915/gen9: WM memory bandwidth related workaround

Signed-off-by: Mahesh Kumar <mahesh1.ku...@intel.com> --- drivers/gpu/drm/i915/i915_drv.c | 1 + drivers/gpu/drm/i915/i915_drv.h | 15 +++ drivers/gpu/drm/i915/intel_display.c | 34 +++ drivers/gpu/drm/i915/intel_pm.c | 187 ++- 4 files c

[Intel-gfx] [PATCH 2/3] drm/i915: Decode system memory bandwidth

inputs - Addresses review comments Changes from v3: - Fix compilation warning Changes from v4: - Address review comments from Paulo - Round-off the frequency & bandwidth results (Paulo) Signed-off-by: Mahesh Kumar <mahesh1.ku...@intel.com> --- drivers/gpu/drm/i915/i915_d

Re: [Intel-gfx] [PATCH v7 7/8] drm/i915: Decode system memory bandwidth

Hi, On Friday 09 December 2016 05:25 AM, Paulo Zanoni wrote: Em Qui, 2016-12-01 às 21:19 +0530, Mahesh Kumar escreveu: This patch adds support to decode system memory bandwidth which will be used for arbitrated display memory percentage calculation in GEN9 based system. Changes from v1

Re: [Intel-gfx] [PATCH v7 8/8] drm/i915/gen9: WM memory bandwidth related workaround

Hi, On Thursday 15 December 2016 10:37 PM, Paulo Zanoni wrote: Em Qui, 2016-12-01 às 21:19 +0530, Mahesh Kumar escreveu: This patch implemnets Workariunds related to display arbitrated memory bandwidth. These WA are applicabe for all gen-9 based platforms. 3 typos above. The WA is already

[Intel-gfx] [PATCH 7/8] drm/i915/skl: New ddb allocation algorithm

: - Rebase on drm-tip - Added separate function to enable WM levels Signed-off-by: Mahesh Kumar <mahesh1.ku...@intel.com> --- drivers/gpu/drm/i915/intel_pm.c | 251 1 file changed, 150 insertions(+), 101 deletions(-) diff --git a/drivers/gpu/drm/i915/inte

[Intel-gfx] [PATCH 2/8] drm/i915/skl+: use linetime latency if ddb size is not available

Use common function for timetime_us calculation (Paulo) - rebase on drm-tip Signed-off-by: "Mahesh Kumar" <mahesh1.ku...@intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 7 +++ drivers/gpu/drm/i915/intel_pm.c | 42 - 2 files changed, 40

[Intel-gfx] [PATCH 0/8] Implement DDB algorithm and WM cleanup

k to see how many buffer allocation are left and enable the best case. In this case since we have 476 blocks we can enable WM0-7 on all 4 planes. Let's say if we have only 200 block available then the best cases allocation is to enable Level2 which requires 168 blocks Mahesh Kumar (8): drm/

[Intel-gfx] [PATCH 4/8] drm/i915/skl+: no need to memset again

We are already doing memset of ddb structure at the begining of skl_allocatE_pipe_ddb function, No need to again do a memset. Signed-off-by: Mahesh Kumar <mahesh1.ku...@intel.com> --- drivers/gpu/drm/i915/intel_pm.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/d

[Intel-gfx] [PATCH 3/8] drm/i915/skl: Fail the flip if no FB for WM calculation

Fail the flip if no FB is present but plane_state is set as visible, that is not a valid combination so instead of continue fail the flip. Signed-off-by: Mahesh Kumar <mahesh1.ku...@intel.com> --- drivers/gpu/drm/i915/intel_pm.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff

[Intel-gfx] [PATCH 1/8] drm/i915/skl+: calculate pixel_rate & relative_data_rate in fixed point

This patch make changes to calculate adjusted plane pixel rate & plane downscale amount using fixed_point functions available. This also adds few fixed point function to facilitate calculation. Signed-off-by: Mahesh Kumar <mahesh1.ku...@intel.com> --- drivers/gpu/drm/i915/i915_

[Intel-gfx] [PATCH 8/8] drm/i915/skl+: consider max supported plane pixel rate while scaling

= Pipe Ratio / Pipe down scale amount } Pipe maximum pixel rate = CDCLK frequency * Pipe Ratio Signed-off-by: Mahesh Kumar <mahesh1.ku...@intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 11 + drivers/gpu/drm/i915/intel_display.c | 3 ++ drivers/gpu/drm/i915/intel_drv.h

[Intel-gfx] [PATCH 6/8] drm/i915/skl+: Watermark calculation cleanup

This patch cleans the watermark calculation functions. This patch make use of already available macro to walk through plane_state list instead of calculating plane_state in function itself. Now we iterate over WM levels in skl_compute_wm_level function. Signed-off-by: Mahesh Kumar <mahesh1

[Intel-gfx] [PATCH 5/8] drm/i915/skl+: ddb min requirement may exceed allocation

DDB minimum requirement may also exceed the allocated DDB for CRTC. Instead of directly deducting from alloc_size, check against total_min_ddb requirement. if exceeding fail the flip. Signed-off-by: Mahesh Kumar <mahesh1.ku...@intel.com> --- drivers/gpu/drm/i915/intel_pm.c | 13 ++

Re: [Intel-gfx] [PATCH] FOR_UPSTREAM [VPG]: drm/i915/skl+: Implement Transition WM

Hi, On Wednesday 31 August 2016 07:17 PM, Zanoni, Paulo R wrote: Em Ter, 2016-08-30 às 19:32 +, Zanoni, Paulo R escreveu: Hi Em Seg, 2016-08-29 às 18:05 +0530, Kumar, Mahesh escreveu: This patch enables Transition WM for SKL+ platforms. Transition WM are used if IPC is enabled, to

Re: [Intel-gfx] [PATCH 4/7] drm/i915/skl: New ddb allocation algorithm

Hi, In this series, I'm not equalizing watermarks among planes of all CRTC's, these patches equalizing it only among Planes of single CRTC from DDB pool allocated for that CRTC, which doesn't require wait_for_vblank So it'll not affect the FPS. On Wednesday 31 August 2016 07:08 PM, Maarten

Re: [Intel-gfx] [PATCH 1/7] drm/i915/hsw+: set intel_crtc active once pipe is active

earlier implementation of "DDB writing" was using this flag before wait_for_vblank if we need to expand the DDB & it overlap with other pipe's DDB. In that case, I observed on corner case requiring a cd-clock change, intel_update_watermarks was waiting for vblank, when it was called from

Re: [Intel-gfx] [PATCH v4] drm/i915/skl: New ddb allocation algorithm

ankhorst wrote: Op 13-09-16 om 14:15 schreef Kumar, Mahesh: From: Mahesh Kumar <mahesh1.ku...@intel.com> This patch implements new DDB allocation algorithm as per HW team suggestion. This algo takecare of scenario where we allocate less DDB for the planes with lower relative pixel rate, bu

Re: [Intel-gfx] [PATCH v3 3/9] drm/i915/skl: New ddb allocation algorithm

hesh: From: Mahesh Kumar <mahesh1.ku...@intel.com> This patch implements new DDB allocation algorithm as per HW team suggestion. This algo takecare of scenario where we allocate less DDB for the planes with lower relative pixel rate, but they require more DDB to work. It also takes care of ena

Re: [Intel-gfx] [PATCH v4] drm/i915/skl: New ddb allocation algorithm

ches. -Mahesh On Monday 19 September 2016 03:25 PM, Maarten Lankhorst wrote: Op 14-09-16 om 14:36 schreef Mahesh Kumar: Hi, There was an issue with transition WM, it was getting enabled & causing fifo underrun. I fixed the condition, After that tested kms_plane & not getting any unde

Re: [Intel-gfx] [PATCH v3 1/9] drm/i915/skl: pass pipe_wm in skl_compute_(wm_level/plane_wm) functions

Tuesday 20 September 2016 05:47 PM, Paulo Zanoni wrote: Em Sex, 2016-09-09 às 13:30 +0530, Kumar, Mahesh escreveu: From: Mahesh Kumar <mahesh1.ku...@intel.com> This patch make use of plane_wm variable directly instead of passing skl_plane_wm struct. this way reduces number of argument require

Re: [Intel-gfx] [PATCH v3 4/9] drm/i915: Decode system memory bandwidth

On Friday 16 September 2016 01:32 PM, Pandiyan, Dhinakaran wrote: On Fri, 2016-09-09 at 13:31 +0530, Kumar, Mahesh wrote: From: Mahesh Kumar <mahesh1.ku...@intel.com> This patch adds support to decode system memory bandwidth which will be used for arbitrated display memory perc

Re: [Intel-gfx] [PATCH v3 8/9] drm/i915/bxt: set chicken bit as IPC y-tile WA

Hi, On Thursday 22 September 2016 01:53 AM, Paulo Zanoni wrote: Em Sex, 2016-09-09 às 13:31 +0530, Kumar, Mahesh escreveu: From: Mahesh Kumar <mahesh1.ku...@intel.com> It implements the WA to enable IDLE_WAKEMEM bit of CHICKEN_DCPR_1 register for Broxton platform. When IPC is enabl

Re: [Intel-gfx] [PATCH v3 2/9] drm/i915/skl+: use linetime latency instead of ddb size

Hi, On Monday 19 September 2016 11:54 PM, Zanoni, Paulo R wrote: Em Seg, 2016-09-19 às 15:19 -0300, Paulo Zanoni escreveu: Em Sex, 2016-09-09 às 13:30 +0530, Kumar, Mahesh escreveu: From: Mahesh Kumar <mahesh1.ku...@intel.com> This patch make changes to use linetime latency i

Re: [Intel-gfx] [PATCH v3 7/9] drm/i915/bxt: Enable IPC support

Hi, On Thursday 22 September 2016 01:36 AM, Paulo Zanoni wrote: Hi Lots of nitpicking in my review. Feel free to disagree with them. Em Sex, 2016-09-09 às 13:31 +0530, Kumar, Mahesh escreveu: From: Mahesh Kumar <mahesh1.ku...@intel.com> This patch adds IPC support for pla

Re: [Intel-gfx] [PATCH v3 6/9] drm/i915/skl+: change WM calc to fixed point 16.16

Hi, On Thursday 22 September 2016 12:02 AM, Paulo Zanoni wrote: Hi Em Sex, 2016-09-09 às 13:31 +0530, Kumar, Mahesh escreveu: From: Mahesh Kumar <mahesh1.ku...@intel.com> First of all, good catch with this patch! This patch changes Watermak calculation to fixed point calculation. P

Re: [Intel-gfx] [PATCH v4 1/8] drm/i915/skl+: use linetime latency instead of ddb size

Hi, On Monday 31 October 2016 11:33 PM, Paulo Zanoni wrote: Em Qui, 2016-10-13 às 16:28 +0530, Kumar, Mahesh escreveu: This patch make changes to use linetime latency instead of allocated DDB size during plane watermark calculation in switch case, This is required to implement new DDB

Re: [Intel-gfx] [PATCH v4 4/8] drm/i915/gen9: WM memory bandwidth related workaround

Hi, On Friday 04 November 2016 10:39 PM, Paulo Zanoni wrote: Em Qui, 2016-10-13 às 16:28 +0530, Kumar, Mahesh escreveu: This patch implemnets Workariunds related to display arbitrated memory bandwidth. These WA are applicabe for all gen-9 based platforms. Changes since v1: - Rebase on top

[Intel-gfx] [PATCH v6 5/8] drm/i915/skl+: change WM calc to fixed point 16.16

required. Which leads to flickers. Changes since V1: - Add fixed point data type as per Paulo's review Changes since V1: - use fixed_point instead of fp_16_16 Signed-off-by: Mahesh Kumar <mahesh1.ku...@intel.com> --- drivers/gpu/drm/i915/i915_drv.

[Intel-gfx] [PATCH v6 6/8] drm/i915: Add intel_atomic_get_existing_crtc_state function

This patch Adds a function to extract intel_crtc_state from the atomic_state, if not available it returns NULL. Signed-off-by: Mahesh Kumar <mahesh1.ku...@intel.com> Reviewed-by: Paulo Zanoni <paulo.r.zan...@intel.com> --- drivers/gpu/drm/i915/intel_drv.h | 14 ++ 1 file

[Intel-gfx] [PATCH v6 8/8] drm/i915/gen9: WM memory bandwidth related workaround

Signed-off-by: Mahesh Kumar <mahesh1.ku...@intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 9 +++ drivers/gpu/drm/i915/intel_pm.c | 149 +--- 2 files changed, 149 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/dr

[Intel-gfx] [PATCH v6 3/8] drm/i915/kbl: IPC workaround for kabylake

IPC (Isoch Priority Control) may cause underflows. KBL WA: When IPC is enabled, watermark latency values must be increased by 4us across all levels. This brings level 0 up to 6us. Signed-off-by: Mahesh Kumar <mahesh1.ku...@intel.com> Reviewed-by: Paulo Zanoni <paulo.r.zan...@

[Intel-gfx] [PATCH v5 0/8] GEN-9 Arbitrated Bandwidth WM WA's & IPC

memory Bandwidth related WM WA's Mahesh Kumar (8): drm/i915/skl: Add variables to check x_tile and y_tile drm/i915/bxt: IPC WA for Broxton drm/i915/kbl: IPC workaround for kabylake drm/i915/bxt: Enable IPC support drm/i915/skl+: change WM calc to fixed point 16.16 drm/i915: Add

[Intel-gfx] [PATCH v6 1/8] drm/i915/skl: Add variables to check x_tile and y_tile

This patch adds variable to check for X_tiled & y_tiled planes, instead of always checking against framebuffer-modifiers. Changes: - Created separate patch as per Paulo's comment - Added x_tiled variable as well Changes since V2: - Incorporate Paulo's comments - Rebase Signed-off-by: Ma

[Intel-gfx] [PATCH v6 7/8] drm/i915: Decode system memory bandwidth

inputs - Addresses review comments Signed-off-by: Mahesh Kumar <mahesh1.ku...@intel.com> --- drivers/gpu/drm/i915/i915_drv.c | 173 drivers/gpu/drm/i915/i915_drv.h | 12 +++ drivers/gpu/drm/i915/i915_reg.h | 37 + 3 files changed, 222 inse

[Intel-gfx] [PATCH v6 2/8] drm/i915/bxt: IPC WA for Broxton

If IPC is enabled in BXT, display underruns are observed. WA: The Line Time programmed in the WM_LINETIME register should be half of the actual calculated Line Time. Programmed Line Time = 1/2*Calculated Line Time Signed-off-by: Mahesh Kumar <mahesh1.ku...@intel.com> Reviewed-by: Paulo

[Intel-gfx] [PATCH v6 4/8] drm/i915/bxt: Enable IPC support

-by: Mahesh Kumar <mahesh1.ku...@intel.com> --- drivers/gpu/drm/i915/i915_drv.c | 2 +- drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/intel_drv.h | 1 + drivers/gpu/drm/i915/intel_pm.c | 16 4 files changed, 19 insertions(+), 1 deletion(-) diff --git a/drivers/g

Re: [Intel-gfx] [PATCH v5 4/8] drm/i915/bxt: Enable IPC support

Hi, On Tuesday 22 November 2016 08:15 PM, Paulo Zanoni wrote: Em Ter, 2016-11-22 às 19:05 +0530, Mahesh Kumar escreveu: Hi, On Tuesday 22 November 2016 12:16 AM, Paulo Zanoni wrote: Em Sex, 2016-11-18 às 20:39 +0530, Mahesh Kumar escreveu: This patch adds IPC support for platforms

Re: [Intel-gfx] [PATCH v5 4/8] drm/i915/bxt: Enable IPC support

Hi, On Tuesday 22 November 2016 12:16 AM, Paulo Zanoni wrote: Em Sex, 2016-11-18 às 20:39 +0530, Mahesh Kumar escreveu: This patch adds IPC support for platforms. This patch enables IPC only for BXT/KBL platform as for SKL recommendation is to keep is disabled. IPC (Isochronous Priority

Re: [Intel-gfx] [PATCH v5 5/8] drm/i915/skl+: change WM calc to fixed point 16.16

On Tuesday 22 November 2016 06:12 PM, Paulo Zanoni wrote: Em Sex, 2016-11-18 às 20:39 +0530, Mahesh Kumar escreveu: This patch changes Watermak calculation to fixed point calculation. Problem with current calculation is during plane_blocks_per_line calculation we divide intermediate blocks

Re: [Intel-gfx] [PATCH v6 2/8] drm/i915/bxt: IPC WA for Broxton

Hi, Will keep WA number in commit message/WA location. thanks, Regards, -Mahesh On Thursday 24 November 2016 06:21 PM, Lankhorst, Maarten wrote: Mahesh Kumar schreef op do 24-11-2016 om 09:31 [+0530]: If IPC is enabled in BXT, display underruns are observed. WA: The Line Time programmed

Re: [Intel-gfx] [PATCH v6 8/8] drm/i915/gen9: WM memory bandwidth related workaround

Hi, On Thursday 24 November 2016 06:21 PM, Lankhorst, Maarten wrote: Mahesh Kumar schreef op do 24-11-2016 om 09:31 [+0530]: This patch implemnets Workariunds related to display arbitrated memory bandwidth. These WA are applicabe for all gen-9 based platforms. Changes since v1: - Rebase

Re: [Intel-gfx] [PATCH v4 3/8] drm/i915: Decode system memory bandwidth

Hi, On Friday 04 November 2016 12:36 AM, Paulo Zanoni wrote: Em Qui, 2016-10-13 às 16:28 +0530, Kumar, Mahesh escreveu: This patch adds support to decode system memory bandwidth which will be used for arbitrated display memory percentage calculation in GEN9 based system. Changes from v1: -

[Intel-gfx] [PATCH v5 0/8] GEN-9 Arbitrated Bandwidth WM WA's & IPC

related WM WA's Mahesh Kumar (8): drm/i915/skl: Add variables to check x_tile and y_tile drm/i915/bxt: IPC WA for Broxton drm/i915/kbl: IPC workaround for kabylake drm/i915/bxt: Enable IPC support drm/i915/skl+: change WM calc to fixed point 16.16 drm/i915: Add

[Intel-gfx] [PATCH v5 5/8] drm/i915/skl+: change WM calc to fixed point 16.16

required. Which leads to flickers. Changes since V1: - Add fixed point data type as per Paulo's review Signed-off-by: Mahesh Kumar <mahesh1.ku...@intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 84 + drivers/gpu/drm/i915/intel_pm.

[Intel-gfx] [PATCH v5 7/8] drm/i915: Decode system memory bandwidth

inputs - Addresses review comments Signed-off-by: Mahesh Kumar <mahesh1.ku...@intel.com> --- drivers/gpu/drm/i915/i915_drv.c | 173 drivers/gpu/drm/i915/i915_drv.h | 12 +++ drivers/gpu/drm/i915/i915_reg.h | 37 + 3 files changed, 222 inse

[Intel-gfx] [PATCH v5 8/8] drm/i915/gen9: WM memory bandwidth related workaround

Signed-off-by: Mahesh Kumar <mahesh1.ku...@intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 9 +++ drivers/gpu/drm/i915/intel_pm.c | 149 +--- 2 files changed, 149 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/dr

[Intel-gfx] [PATCH v5 6/8] drm/i915: Add intel_atomic_get_existing_crtc_state function

This patch Adds a function to extract intel_crtc_state from the atomic_state, if not available it returns NULL. Signed-off-by: Mahesh Kumar <mahesh1.ku...@intel.com> --- drivers/gpu/drm/i915/intel_drv.h | 14 ++ 1 file changed, 14 insertions(+) diff --git a/drivers/gpu/dr

[Intel-gfx] [PATCH v5 3/8] drm/i915/kbl: IPC workaround for kabylake

IPC (Isoch Priority Control) may cause underflows. KBL WA: When IPC is enabled, watermark latency values must be increased by 4us across all levels. This brings level 0 up to 6us. Signed-off-by: Mahesh Kumar <mahesh1.ku...@intel.com> --- drivers/gpu/drm/i915/intel_pm.c | 4 1 file c

[Intel-gfx] [PATCH v5 2/8] drm/i915/bxt: IPC WA for Broxton

If IPC is enabled in BXT, display underruns are observed. WA: The Line Time programmed in the WM_LINETIME register should be half of the actual calculated Line Time. Programmed Line Time = 1/2*Calculated Line Time Signed-off-by: Mahesh Kumar <mahesh1.ku...@intel.com> --- drivers/gpu/dr

[Intel-gfx] [PATCH v5 1/8] drm/i915/skl: Add variables to check x_tile and y_tile

This patch adds variable to check for X_tiled & y_tiled planes, instead of always checking against framebuffer-modifiers. Changes: - Created separate patch as per Paulo's comment - Added x_tiled variable as well Changes since V2: - Incorporate Paulo's comments - Rebase Signed-off-by: Ma

[Intel-gfx] [PATCH v5 4/8] drm/i915/bxt: Enable IPC support

requests are sent at high priority. Changes since V1: - Remove commandline parameter to disable ipc - Address Paulo's comments Changes since V2: - Address review comments - Set ipc_enabled flag Signed-off-by: Mahesh Kumar <mahesh1.ku...@intel.com> --- drivers/gpu/drm/i915/i915_drv.c

Re: [Intel-gfx] [PATCH v4 8/8] drm/i915/bxt: Enable IPC support

Hi, On Thursday 13 October 2016 04:49 PM, Maarten Lankhorst wrote: Op 13-10-16 om 12:58 schreef Kumar, Mahesh: From: Mahesh Kumar <mahesh1.ku...@intel.com> This patch adds IPC support for platforms. This patch enables IPC only for BXT/KBL platform as for SKL recommendation is t

Re: [Intel-gfx] [PATCH v5 4/8] drm/i915/bxt: Enable IPC support

Hi, On Tuesday 22 November 2016 08:15 PM, Paulo Zanoni wrote: Em Ter, 2016-11-22 às 19:05 +0530, Mahesh Kumar escreveu: Hi, On Tuesday 22 November 2016 12:16 AM, Paulo Zanoni wrote: Em Sex, 2016-11-18 às 20:39 +0530, Mahesh Kumar escreveu: This patch adds IPC support for platforms

[Intel-gfx] [PATCH v7 7/8] drm/i915: Decode system memory bandwidth

inputs - Addresses review comments Changes from v3: - Fix compilation warning Signed-off-by: Mahesh Kumar <mahesh1.ku...@intel.com> --- drivers/gpu/drm/i915/i915_drv.c | 173 drivers/gpu/drm/i915/i915_drv.h | 12 +++ drivers/gpu/drm/i915/i915

[Intel-gfx] [PATCH v7 5/8] drm/i915/skl+: change WM calc to fixed point 16.16

required. Which leads to flickers. Changes since V1: - Add fixed point data type as per Paulo's review Changes since V2: - use fixed_point instead of fp_16_16 Changes since V3: - rebase Signed-off-by: Mahesh Kumar <mahesh1.ku...@intel.com> --- drivers/gpu/drm/i915/i915_drv.

[Intel-gfx] [PATCH v7 4/8] drm/i915/bxt: Enable IPC support

-by: Mahesh Kumar <mahesh1.ku...@intel.com> --- drivers/gpu/drm/i915/i915_drv.c | 2 +- drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/intel_drv.h | 1 + drivers/gpu/drm/i915/intel_pm.c | 16 4 files changed, 19 insertions(+), 1 deletion(-) diff --git a/drivers/g

[Intel-gfx] [PATCH v7 0/8] GEN-9 Arbitrated Bandwidth WM WA's & IPC

memory Bandwidth related WM WA's Mahesh Kumar (8): drm/i915/skl: Add variables to check x_tile and y_tile drm/i915/bxt: IPC WA for Broxton drm/i915/kbl: IPC workaround for kabylake drm/i915/bxt: Enable IPC support drm/i915/skl+: change WM calc to fixed point 16.16 drm/i915: Add

[Intel-gfx] [PATCH v7 1/8] drm/i915/skl: Add variables to check x_tile and y_tile

This patch adds variable to check for X_tiled & y_tiled planes, instead of always checking against framebuffer-modifiers. Changes: - Created separate patch as per Paulo's comment - Added x_tiled variable as well Changes since V2: - Incorporate Paulo's comments - Rebase Signed-off-by: Ma

[Intel-gfx] [PATCH v7 2/8] drm/i915/bxt: IPC WA for Broxton

& code Signed-off-by: Mahesh Kumar <mahesh1.ku...@intel.com> Reviewed-by: Paulo Zanoni <paulo.r.zan...@intel.com> --- drivers/gpu/drm/i915/i915_drv.c | 2 ++ drivers/gpu/drm/i915/i915_drv.h | 2 ++ drivers/gpu/drm/i915/intel_pm.c | 12 ++-- 3 files changed, 14 insertions

[Intel-gfx] [PATCH v7 6/8] drm/i915: Add intel_atomic_get_existing_crtc_state function

This patch Adds a function to extract intel_crtc_state from the atomic_state, if not available it returns NULL. Signed-off-by: Mahesh Kumar <mahesh1.ku...@intel.com> Reviewed-by: Paulo Zanoni <paulo.r.zan...@intel.com> --- drivers/gpu/drm/i915/intel_drv.h | 14 ++ 1 file

[Intel-gfx] [PATCH v7 8/8] drm/i915/gen9: WM memory bandwidth related workaround

Changes since v3: - Rework based on Maarten's comments Signed-off-by: Mahesh Kumar <mahesh1.ku...@intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 11 +++ drivers/gpu/drm/i915/intel_display.c | 24 ++ drivers/gpu/drm/i915/intel_pm.c | 155 +-- 3

[Intel-gfx] [PATCH v7 3/8] drm/i915/kbl: IPC workaround for kabylake

Display Workarounds #1141 IPC (Isoch Priority Control) may cause underflows. KBL WA: When IPC is enabled, watermark latency values must be increased by 4us across all levels. This brings level 0 up to 6us. Changes since V1: - Add Workaround number in commit & code Signed-off-by: Mahesh K

Re: [Intel-gfx] [PATCH v6 8/8] drm/i915/gen9: WM memory bandwidth related workaround

On Tuesday 29 November 2016 03:16 PM, Lankhorst, Maarten wrote: Mahesh Kumar schreef op di 29-11-2016 om 11:12 [+0530]: Hi, On Thursday 24 November 2016 06:21 PM, Lankhorst, Maarten wrote: Mahesh Kumar schreef op do 24-11-2016 om 09:31 [+0530]: This patch implemnets Workariunds related

[Intel-gfx] [RFC]: Arbitrated system memory bandwidth workarounds implementation for watermark.

*Arbitrated system bandwidth workarounds for watermark.* All GEN-9 based platforms require watermark related WA to be enabled if Display memory bandwidth requirement is exceeding XX% of total available system memory bandwidth. This XX% depend on multiple factors. *e.g.* if all the enabled

Re: [Intel-gfx] [RFC]: Arbitrated system memory bandwidth workarounds implementation for watermark.

going > 20% & Y-tile is enabled, then only we may need to take the mutex of all CRTC, so there will be fairly less changes of holding any lock. Regards, -Mahesh On Tuesday 28 March 2017 01:38 PM, Maarten Lankhorst wrote: Op 27-03-17 om 17:52 schreef Mahesh Kumar: *Arbitrated system bandwidt

Re: [Intel-gfx] [PATCH 5/8] drm/i915/skl+: ddb min requirement may exceed allocation

Hi Ander, Thanks for review On Wednesday 12 April 2017 02:47 PM, Ander Conselvan De Oliveira wrote: On Tue, 2017-02-28 at 17:01 +0530, Mahesh Kumar wrote: DDB minimum requirement may also exceed the allocated DDB for CRTC. Instead of directly deducting from alloc_size, check against

Re: [Intel-gfx] [PATCH 1/8] drm/i915: Change use get_new_plane_state instead of existing plane state

Hi, On Thursday 20 July 2017 06:45 PM, Maarten Lankhorst wrote: The get_existing macros are deprecated and should be replaced by get_old/new_state for clarity. Signed-off-by: Maarten Lankhorst --- drivers/gpu/drm/i915/intel_atomic.c | 4 ++--

Re: [Intel-gfx] [PATCH 3/8] drm/i915: Use new atomic helpers in intel_plane_atomic_check

Hi, On Thursday 20 July 2017 06:45 PM, Maarten Lankhorst wrote: Remove the use of plane->state and drm_atomic_get_existing_state, instead use the new helpers, and also add intel_atomic_get_new_crtc_state as it's needed. Signed-off-by: Maarten Lankhorst ---

Re: [Intel-gfx] [PATCH 4/8] drm/i915: Use intel_atomic_get_new_crtc_state in intel_fbc.c

Hi, patch looks ok to me. Reviewed-by: Mahesh Kumar <mahesh1.ku...@intel.com> On Thursday 20 July 2017 06:45 PM, Maarten Lankhorst wrote: The previous commit added intel_atomic_get_new_crtc_state, convert intel_fbc.c to the new helper. Signed-off-by: Maarten Lankhorst <maart

Re: [Intel-gfx] [PATCH 2/8] drm/i915: Change get_existing_crtc_state to old state

On Tuesday 01 August 2017 01:23 PM, Maarten Lankhorst wrote: Hey, Op 01-08-17 om 08:46 schreef Mahesh Kumar: Hi, As per my understanding "get_existing_*_state == get_new_*_state" It looks like you are trying to use currently available unused wrapper for completely differe

Re: [Intel-gfx] [PATCH] drm/i915/gen10: implement gen 10 watermarks calculations

patch looks good to me, Reviewed-by: Mahesh Kumar <mahesh1.ku...@intel.com> On Saturday 12 August 2017 05:08 AM, Rodrigo Vivi wrote: comment. Code matches recent spec. v3: Rebase on top of latest skl code using new fp16.16 and fixing a logic issue. Auto rebase bot has appa

Re: [Intel-gfx] [PATCH 5/6] drm/i915/gen10: implement gen 10 watermarks calculations

Hi, On Thursday 10 August 2017 02:22 AM, Rodrigo Vivi wrote: From: Paulo Zanoni <paulo.r.zan...@intel.com> They're slightly different than the gen 9 calculations. v2: Remove TODO comment. Code matches recent spec. Cc: Mahesh Kumar <mahesh1.ku...@intel.com> Cc: Maart

Re: [Intel-gfx] [PATCH 8/8] drm/i915/skl+: debugfs entry to control IPC

Hi, On Wednesday 09 August 2017 03:16 PM, Maarten Lankhorst wrote: Op 18-07-17 om 14:49 schreef Mahesh Kumar: From: "Kumar, Mahesh" <mahesh1.ku...@intel.com> This patch creates an entry in debugfs to check the status of IPC. This can also be used to enable/disable IPC in sup

Re: [Intel-gfx] [PATCH] drm/i915: Fix bad comparison in skl_compute_plane_wm.

Reviewed-by: Mahesh Kumar <mahesh1.ku...@intel.com> On Monday 17 July 2017 04:43 PM, Maarten Lankhorst wrote: ddb_allocation && ddb_allocation / blocks_per_line >= 1 is the same as ddb_allocation >= blocks_per_line, so use the latter to simplify this. This fixes the follow

Re: [Intel-gfx] drivers/gpu/drm/i915/intel_pm.c:4467: bad comparison ?

Hi, On Monday 17 July 2017 03:22 PM, Jani Nikula wrote: On Mon, 17 Jul 2017, David Binderman wrote: Hello there, Hello. No need to include LKML for stuff like this. But Cc'd the folks from the broken commit. drivers/gpu/drm/i915/intel_pm.c:4467]: (warning) Comparison

Re: [Intel-gfx] drivers/gpu/drm/i915/intel_pm.c:4467: bad comparison ?

Hi, On Monday 17 July 2017 04:01 PM, Maarten Lankhorst wrote: Op 17-07-17 om 12:32 schreef Mahesh Kumar: Hi, On Monday 17 July 2017 03:22 PM, Jani Nikula wrote: On Mon, 17 Jul 2017, David Binderman <dcb...@hotmail.com> wrote: Hello there, Hello. No need to include LKML for stuf

[Intel-gfx] [PATCH 11/13] drm/i915/bxt: Enable IPC support

since V4: - Re-enable IPC after suspend/resume Changes since V5: - Enable IPC for all gen >=9 except SKL Changes since V6: - fix commit msg - after resume program IPC based on SW state. Signed-off-by: Mahesh Kumar <mahesh1.ku...@intel.com> --- drivers/gpu/drm/i915/i915_drv.c | 4 +

Re: [Intel-gfx] [PATCH 11/13] drm/i915/bxt: Enable IPC support

Hi, On Thursday 13 July 2017 04:18 PM, Chris Wilson wrote: Quoting Mahesh Kumar (2017-07-13 11:39:02) +void intel_enable_ipc(struct drm_i915_private *dev_priv) +{ + u32 val; + + val = I915_READ(DISP_ARB_CTL2); + + if (dev_priv->ipc_enabled) +

Re: [Intel-gfx] [PATCH 06/11] drm/i915/skl+: unify cpp value in WM calculation

Hi Jani, Thanks for review. On Friday 14 July 2017 03:56 PM, Jani Nikula wrote: On Thu, 13 Jul 2017, Maarten Lankhorst <maarten.lankho...@linux.intel.com> wrote: Op 05-07-17 om 16:31 schreef Mahesh Kumar: From: "Kumar, Mahesh" <mahesh1.ku...@intel.com> use same

[Intel-gfx] [PATCH 4/8] drm/i915/glk: IPC linetime watermark workaround for GLK

cts that as well. Signed-off-by: Mahesh Kumar <mahesh1.ku...@intel.com> --- drivers/gpu/drm/i915/intel_pm.c | 7 --- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 9a2ed1b734d5..dac0fcf8b54e 100644 ---

[Intel-gfx] [PATCH 5/8] drm/i915/cnl: Extend WM workaround with IPC for CNL

From: "Kumar, Mahesh" <mahesh1.ku...@intel.com> CNL:A & CNL:B have same workaround as KBL to increase wm level latency by 4us if IPC is enabled. Signed-off-by: Mahesh Kumar <mahesh1.ku...@intel.com> --- drivers/gpu/drm/i915/intel_pm.c | 3 ++- 1 file changed, 2

[Intel-gfx] [PATCH 6/8] drm/i915/gen9+: Add has_ipc flag in device info structure

From: "Kumar, Mahesh" <mahesh1.ku...@intel.com> New Isochronous Priority Control (IPC) capability is introduced in newer GEN platforms. This patch adds a device info flag to indicate if platform supports IPC. Patch also sets this flag in supported platforms. Signed-off-by: Mahes

[Intel-gfx] [PATCH 8/8] drm/i915/skl+: debugfs entry to control IPC

From: "Kumar, Mahesh" <mahesh1.ku...@intel.com> This patch creates an entry in debugfs to check the status of IPC. This can also be used to enable/disable IPC in supported platforms. Signed-off-by: Mahesh Kumar <mahesh1.ku...@intel.com> --- drivers/gpu/drm/i9

[Intel-gfx] [PATCH 7/8] drm/i915/bxt+: Enable IPC support

Chris) Signed-off-by: Mahesh Kumar <mahesh1.ku...@intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> --- drivers/gpu/drm/i915/i915_drv.c | 4 +++- drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/intel_display.c | 1 + drivers/gpu/drm/i915/intel_drv.h | 2 ++

Re: [Intel-gfx] [PATCH v3 0/2] Handle unsupported configuration with IF-ID

Hi Daniel, On Monday 17 July 2017 12:56 PM, Daniel Vetter wrote: On Fri, Jun 30, 2017 at 05:40:58PM +0530, Mahesh Kumar wrote: Gen9+ Interlace fetch mode doesn't support few plane configurations & pipe scaling. - Y-tile - 90/270 rotation - pipe/plane scaling - 420 planar formats

[Intel-gfx] [PATCH 2/8] drm/i915/skl+: Optimize WM calculation

during each level-wm calculation. Signed-off-by: Mahesh Kumar <mahesh1.ku...@intel.com> Acked-by: Maarten Lankhorst <maarten.lankho...@linux.intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 13 +++ drivers/gpu/drm/i915/intel_pm.c | 179 ++-- 2 files changed,

[Intel-gfx] [PATCH 3/8] drm/i915/gen10: Calculate and enable transition WM

riods of high and lower priority reads. Keeping transition amount to 10 in this patch, as suggested by HW team. Signed-off-by: Mahesh Kumar <mahesh1.ku...@intel.com> Acked-by: Maarten Lankhorst <maarten.lankho...@linux.intel.com> --- drivers/gpu/drm/i915/intel_pm.c | 51 ++

[Intel-gfx] [PATCH 1/8] drm/i915: Fixed point fixed16 wrapper cleanup

From: "Kumar, Mahesh" <mahesh1.ku...@intel.com> As per suggestion from Jani, cleanup the code. Cleanup includes - Instead of left shifting & check, compare with U32/16_MAX - Use typecast instead of clamp_t Signed-off-by: Mahesh Kumar <mahesh1.ku...@intel.com>

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