s occurred. When testing UTS under VM it worked, but when running native it
failed. Sometimes VM can mask these kinds of problems.
-Original Message-
From: Phil Payne [mailto:[EMAIL PROTECTED]
Sent: Tuesday, December 16, 2003 5:15 AM
To: [EMAIL PROTECTED]
Subject: Re: Technical Specs
On Tuesday, 12/16/2003 at 02:14 CET, Phil Payne <[EMAIL PROTECTED]>
wrote:
> > I imagined that MVC was "atomic" in nature meaning that the second
processor
> > couldn't "garble" things until the MVC had run it's course.
>
> I think that's "implementation-dependent", as IBM would say. Unwise to
rel
On Tue, 2003-12-16 at 08:14, Phil Payne wrote:
> > I imagined that MVC was "atomic" in nature meaning that the second processor
> > couldn't
> "garble" things until the MVC had run it's course.
>
> I think that's "implementation-dependent", as IBM would say. Unwise to rely on it.
Phil is right.
> I wonder what the significance of being interruptible is if not garbling
results.
MVCL came along with System/370 - at that time uniprocessors were more common and a
lot of IBM
hardware had strict timing considerations - 1419 interrupts HAD to be handled within
so many
milliseconds or you "los
Phil,
I wonder what the significance of being interruptible is if not garbling
results. I imagined that MVC was "atomic" in nature meaning that the second
processor couldn't "garble" things until the MVC had run it's course.
Well, this probably isn't of much interest to anyone here but thanks for
> You can rely on MVCL to operate the way the POP says it will. My impression
from reading the POP is that the MVCL is an interruptible instruction so if
you're coding first level on a multi processor configuration without an
operating system to manager things for you the results of the MVCL can be
Phil,
Is the source, less OCO modules, for CP still distributed with VM? I wonder
if the CP maclibs or source for z/VM would have a MVCL burdied somewhere in
them following a lock of some kind.
Paul
MVCL and CAS are for different purposes, even though they do similar things.
MVCL us used to mov
Alan,
You can rely on MVCL to operate the way the POP says it will. My impression
from reading the POP is that the MVCL is an interruptible instruction so if
you're coding first level on a multi processor configuration without an
operating system to manager things for you the results of the MVCL c
Check the proceedings of recent SHARE conferences at www.share.org.
Bob's talk was given there; it was based on a presentation by Graham
Ewart at the Nashville SHARE meeting.
John Ehrman
(-- Referenced Note Follows )
Date:Sun, 14 Dec 2003 21:44:02 -0500
F
3 9:58 AM
> To: [EMAIL PROTECTED]
> Subject: Re: [LINUX-390] Technical Specs
>
> On Mon, 2003-12-15 at 08:07, Alan Altmark wrote:
> > Prime Directive [apologies to G.L.]
>
> G.R., surely?
>
> Adam
On Monday, 12/15/2003 at 08:40 PST, "Fargusson.Alan"
<[EMAIL PROTECTED]> wrote:
> The only thing I can think of that is related to reliability is that a
MOVCL
> will not work for multiprocessor synchronization since it will not
prevent two
> processor from modifying the same memory at the same tim
: [EMAIL PROTECTED]
Subject: Re: Technical Specs
Phil,
By themsleves the cycle times might not be of interest. The cycle times in
conjunction with explanation of fetch operations and how instructions and
their addresses are really resolved would probably be very instructive.
Not complex examples but a
On Mon, 2003-12-15 at 08:07, Alan Altmark wrote:
> Prime Directive [apologies to G.L.]
G.R., surely?
Adam
On Saturday, 12/13/2003 at 06:50 EST, Paul Hanrahan
<[EMAIL PROTECTED]> wrote:
> By themsleves the cycle times might not be of interest. The cycle times
in
> conjunction with explanation of fetch operations and how instructions
and
> their addresses are really resolved would probably be very instru
t: Re: Technical Specs
At the zExpo in Munich last year, Bob Rogers did a terrific talk on
instruction pipelining and scheduling and the zSeries processor. I don't
know if that presentation was restricted, but perhaps someone inside IBM
could find out and make it available. It did a very good job o
At the zExpo in Munich last year, Bob Rogers did a terrific talk on
instruction pipelining and scheduling and the zSeries processor. I don't
know if that presentation was restricted, but perhaps someone inside IBM
could find out and make it available. It did a very good job of covering
exactly the
Hi,
I'm trying to recall. Was there a LRAE?
Paul
e capping that was supposed to improve
how the dispatcher divided up resources between users more fairly.
HCPRUN always bothered me.
Paul
-Original Message-
From: Linux on 390 Port [mailto:[EMAIL PROTECTED] On Behalf Of Phil
Payne
Sent: Saturday, December 13, 2003 7:26 AM
To: [EMAIL PROTECTED
> Multi level cache, translation lookaside buffers and a number of other items
come to mind.
Segment Table Origin Register Save Stacks. Each TLB entry is "tagged" with the STO it
corresponds to. If an address space switch occurs, a new STO is loaded but the old
one is
saved in a stack and its T
Hi,
Multi level cache, translation lookaside buffers and a number of other items
come to mind.
Paul
-Original Message-
From: Linux on 390 Port [mailto:[EMAIL PROTECTED] On Behalf Of Phil
Payne
Sent: Saturday, December 13, 2003 5:30 AM
To: [EMAIL PROTECTED]
Subject: Re: Technical Specs
is
more reliable in a multi processor environment and an MVCL isn't.
Paul
-Original Message-
From: Linux on 390 Port [mailto:[EMAIL PROTECTED] On Behalf Of Phil
Payne
Sent: Saturday, December 13, 2003 5:22 AM
To: [EMAIL PROTECTED]
Subject: Re: Technical Specs
> Actually, I beli
> As you said, a meaningless question. I don't know if IBM even publishes this
> information. However, just for fun, Phil Payne's site
> (http://www.isham-research.com/mips_z800.html) rates a 2066-001 at 192 MIPS.
I like the "just for fun".
The disclaimer on that page still applies.
--
Phil Pa
> And in each generation the pipelining abilities get better and better.
Not always. 3033 ---> 3081?
> For those who aren't up on the latest in processor design, "pipelining" is
> a way for the CPU to actually execute more than one instruction (or parts
> of a multi-cycle instruction) a single c
> Actually, I believe they do. Take the cycle time (which I believe they do
> publish somewhere) and invert, and voila. I seem to recall from some
> comments that Barton Robinson made many months ago that the first generation
> zSeries boxes were 200Mhz machines (5ns cycle time). I'm sure someon
On Fri, 2003-12-12 at 10:59, Barton Robinson wrote:
> Alan, I'd take one small exception. you don't need to be up
> on the "latest in processor design", i'm pretty sure pipeline
> technology shipped as part of the early 370 series, at
> least i remember studying it in the 70's. (158/168 if anyone
>
On Friday, 12/12/2003 at 07:59 PST, Barton Robinson
<[EMAIL PROTECTED]> wrote:
> Alan, I'd take one small exception. you don't need to be up
> on the "latest in processor design", i'm pretty sure pipeline
> technology shipped as part of the early 370 series, at
> least i remember studying it in the
prediction.
-Original Message-
From: Alan Altmark [mailto:[EMAIL PROTECTED]
Sent: Friday, December 12, 2003 6:35 AM
To: [EMAIL PROTECTED]
Subject: Re: Technical Specs
On Wednesday, 12/10/2003 at 11:12 PST, "Wolfe, Gordon W"
<[EMAIL PROTECTED]> wrote:
> On a microcoded
Alan, I'd take one small exception. you don't need to be up
on the "latest in processor design", i'm pretty sure pipeline
technology shipped as part of the early 370 series, at
least i remember studying it in the 70's. (158/168 if anyone
remembers?).
>From: Alan Altmark <[EMAIL PROTECTED]>
>
>
>An
On Wednesday, 12/10/2003 at 11:12 PST, "Wolfe, Gordon W"
<[EMAIL PROTECTED]> wrote:
> On a microcoded machine, megahertz numbers are totally useless. They're
> useless in general anyway because an instruction may take one, or two,
or many
> clock cycles. With level-two and level-three cache and in
Introduction at:
http://www.redbooks.ibm.com/redbooks/pdfs/sg246863.pdf
Bob
-Original Message-
From: Linux on 390 Port [mailto:[EMAIL PROTECTED] On Behalf Of Michael Short
Sent: Wednesday, December 10, 2003 1:23 PM
To: [EMAIL PROTECTED]
Subject:Re: Technical Specs
This
AIL PROTECTED]
> Subject: Re: Technical Specs
>
> As you said, a meaningless question. I don't know if IBM even publishes this
> information. However, just for fun, Phil Payne's site
> (http://www.isham-research.com/mips_z800.html) rates a 2066-001 at 192 MIPS.
> I am
age-
> From: Jason Herne [SMTP:[EMAIL PROTECTED]
> Sent: Tuesday, December 09, 2003 12:28 PM
> To: [EMAIL PROTECTED]
> Subject: Technical Specs
>
> We are running a 2066-OLF (z/800 Linux only model). Can anyone point me
> to some IBM documenation that tells me the s
Manual GM13-0117-04 z800 Reference Guide page 19,
lists the cycle time for the z800 0LF as 1.6ns.
Here is the z800 MHz along with other recent iron:
9672 G4 = 400 MHz
9672 G5 = 500 MHz
9672 G6 = 637 MHz
2064 z900 = 769 MHz (from 1000/1.3ns)
2066 z800 = 625 MHz (from 1000/1.6ns)
2084 z990
Duhhyea, it calls homeno reason for a person on site to be
envolved!
Tom Duerbusch
THD Consulting
>>> [EMAIL PROTECTED] 12/10/03 12:12PM >>>
Tom:
Actually, I believe the answer is "It monitors itself".
Romney
On Wed, 10 Dec 2003 11:19:14 -0600 Tom Duerbusch said:
>You can't anymore? T
To: [EMAIL PROTECTED]
Mark Postcc: (bcc: Michael Short/Towers
Perrin)
<[EMAIL PROTECTED]Subject: Re: Technical Specs
et>
Sent by: Linux on
Tom:
Actually, I believe the answer is "It monitors itself".
Romney
On Wed, 10 Dec 2003 11:19:14 -0600 Tom Duerbusch said:
>You can't anymore? The IBM 4341 use to show you its temperature when
>you went into CEKEY mode on the console.
>
>Tom Duerbusch
>THD Consulting
>
>This question is right u
e who
knows for sure can confirm or refute that.
Mark Post
-Original Message-
From: Linux on 390 Port [mailto:[EMAIL PROTECTED] Behalf Of
Little, Chris
Sent: Wednesday, December 10, 2003 12:01 PM
To: [EMAIL PROTECTED]
Subject: Re: Technical Specs
Ack! Run away! Here we go again!
IBM do
You can't anymore? The IBM 4341 use to show you its temperature when
you went into CEKEY mode on the console.
Tom Duerbusch
THD Consulting
This question is right up there with the one our ops manager wanted to
know:
"How do I monitor the z800's CPU temperature like I do the Intel
servers?"
Answe
From: Jason Herne [mailto:[EMAIL PROTECTED]
> Sent: Tuesday, December 09, 2003 11:28 AM
> To: [EMAIL PROTECTED]
> Subject: Technical Specs
>
>
> We are running a 2066-OLF (z/800 Linux only model). Can
> anyone point me
> to some IBM documenation that tells me the speed of the pro
M
> To: [EMAIL PROTECTED]
> Subject: Technical Specs
>
>
> We are running a 2066-OLF (z/800 Linux only model). Can
> anyone point me
> to some IBM documenation that tells me the speed of the processor in
> Mhz? I understand that this metric means very little but
> someone
We are running a 2066-OLF (z/800 Linux only model). Can anyone point me
to some IBM documenation that tells me the speed of the processor in
Mhz? I understand that this metric means very little but someone higher
up in the management chain would like to know :-)
- Jason Herne ([EMAIL PROTECTED])
41 matches
Mail list logo
