Re: [Mesa-dev] Getting write permissions on the mesa repo to push panfrost stuff
Boris Brezillon writes: > Hello, > > Alyssa recently proposed that I push my own panfrost-related > submissions once they received proper review and are considered > ready to merged (meaning that received enough A-b/R-b tags). > > In order to do that, I'd need to obtain write permissions on the git > repo. Note that I already have an account on fd.o (my nick is > bbrezillon). I guess Alyssa and/or Tomew will ack this request soon. Let > me know if you need anything else from me. I've added you -- you certainly did good work when we were working on vc4. Coordinate with Alyssa and Tomeu on expectations for merging to panfrost :) signature.asc Description: PGP signature ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [MR] Update README to recommend MRs instead of `git send-email`
Jason Ekstrand writes: > On Tue, Jul 9, 2019 at 11:19 AM Kristian Høgsberg > wrote: > >> On Tue, Jul 9, 2019 at 12:17 AM Daniel Stone wrote: >> > >> > Hi, >> > >> > On Sat, 6 Jul 2019 at 18:39, Ilia Mirkin wrote: >> > > I see this as driving away contributions, esp from new people. MR's >> > > are annoying to create, since they require dealing with the hosting >> > > provider, getting it to host clones, etc. Everyone has email. >> > >> > My position - and the evidence of velocity from projects who have >> > switched - is already pretty clear, but you might be interested to >> > read that even kernel.org admins are trying to move away from email: >> > >> https://people.kernel.org/monsieuricon/patches-carved-into-developer-sigchains >> >> I have the same experience - I've used git since before it was usable >> and I'm more than happy to not have to worry about making git >> send-email work. I'm pretty sure that gitlab in general lowers the bar >> for contributions considerably, I know I find my self doing a lot more >> reviews and drive-by comments because of how easy it feels > > > I know I'm a gitlab fan-boy so you all know I like this. What I will say > is that it's not only easier for new developers because PRs are a concept > they already know from GitHub and the like but it's also easier for > maintainers. I've actually started getting annoyed when people send > patches to the list and I have to apply them from e-mail. It's so much > easier to just check that they've added all the tags and click a couple > buttons in the web UI than to have to find the thing on patchwork, download > it, hope it applies, and push it. Same. I'm actually not reading patches on the mailing list any more. If you want my input, put it in the system where I don't have to waste my time tracking if it's been merged or not and whether you responded to my comments from the last round. I don't think we're quite to "make sure they've added the tags and click the button" safely since we don't have pre-merge testing happening (you have to trust that the submitter tested, and master hasn't regressed things since then). I'm working on that. signature.asc Description: PGP signature ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] radv/gfx10: do not set alignment on the ngg_emit pointer
R-b On Thu, Jul 11, 2019, 6:33 PM Samuel Pitoiset wrote: > This is invalid and this fixes a crash in LLVM. > > Signed-off-by: Samuel Pitoiset > --- > src/amd/vulkan/radv_nir_to_llvm.c | 1 - > 1 file changed, 1 deletion(-) > > diff --git a/src/amd/vulkan/radv_nir_to_llvm.c > b/src/amd/vulkan/radv_nir_to_llvm.c > index bf712b7fe45..32548857b57 100644 > --- a/src/amd/vulkan/radv_nir_to_llvm.c > +++ b/src/amd/vulkan/radv_nir_to_llvm.c > @@ -4326,7 +4326,6 @@ LLVMModuleRef ac_translate_nir_to_llvm(struct > ac_llvm_compiler *ac_llvm, > ctx.gs_ngg_emit = > LLVMBuildIntToPtr(ctx.ac.builder, > ctx.ac.i32_0, > > LLVMPointerType(LLVMArrayType(ctx.ac.i32, 0), AC_ADDR_SPACE_LDS), > "ngg_emit"); > - LLVMSetAlignment(ctx.gs_ngg_emit, 4); > } > > ctx.gs_max_out_vertices = > shaders[i]->info.gs.vertices_out; > -- > 2.22.0 > > ___ > mesa-dev mailing list > mesa-dev@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/mesa-dev ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 2/2] radv: report shader stage name when dumping LLVM IR
R-b for the series
On Thu, Jul 11, 2019, 6:04 PM Samuel Pitoiset
wrote:
> For debugging purposes.
>
> Signed-off-by: Samuel Pitoiset
> ---
> src/amd/vulkan/radv_nir_to_llvm.c | 21 +
> 1 file changed, 17 insertions(+), 4 deletions(-)
>
> diff --git a/src/amd/vulkan/radv_nir_to_llvm.c
> b/src/amd/vulkan/radv_nir_to_llvm.c
> index 32548857b57..e4ab5847729 100644
> --- a/src/amd/vulkan/radv_nir_to_llvm.c
> +++ b/src/amd/vulkan/radv_nir_to_llvm.c
> @@ -4434,8 +4434,13 @@ LLVMModuleRef ac_translate_nir_to_llvm(struct
> ac_llvm_compiler *ac_llvm,
>
> LLVMBuildRetVoid(ctx.ac.builder);
>
> - if (options->dump_preoptir)
> + if (options->dump_preoptir) {
> + fprintf(stderr, "%s LLVM IR:\n\n",
> + radv_get_shader_name(shader_info,
> +shaders[shader_count -
> 1]->info.stage));
> ac_dump_module(ctx.ac.module);
> + fprintf(stderr, "\n");
> + }
>
> ac_llvm_finalize_module(, ac_llvm->passmgr, options);
>
> @@ -4489,13 +4494,18 @@ static void ac_compile_llvm_module(struct
> ac_llvm_compiler *ac_llvm,
>struct radv_shader_binary **rbinary,
>struct radv_shader_variant_info
> *shader_info,
>gl_shader_stage stage,
> + const char *name,
>const struct radv_nir_compiler_options
> *options)
> {
> char *elf_buffer = NULL;
> size_t elf_size = 0;
> char *llvm_ir_string = NULL;
> - if (options->dump_shader)
> +
> + if (options->dump_shader) {
> + fprintf(stderr, "%s LLVM IR:\n\n", name);
> ac_dump_module(llvm_module);
> + fprintf(stderr, "\n");
> + }
>
> if (options->record_llvm_ir) {
> char *llvm_ir = LLVMPrintModuleToString(llvm_module);
> @@ -4585,7 +4595,10 @@ radv_compile_nir_shader(struct ac_llvm_compiler
> *ac_llvm,
>options);
>
> ac_compile_llvm_module(ac_llvm, llvm_module, rbinary, shader_info,
> - nir[nir_count - 1]->info.stage, options);
> + nir[nir_count - 1]->info.stage,
> + radv_get_shader_name(shader_info,
> + nir[nir_count -
> 1]->info.stage),
> + options);
>
> for (int i = 0; i < nir_count; ++i)
> ac_fill_shader_info(shader_info, nir[i], options);
> @@ -4737,7 +4750,7 @@ radv_compile_gs_copy_shader(struct ac_llvm_compiler
> *ac_llvm,
> ac_llvm_finalize_module(, ac_llvm->passmgr, options);
>
> ac_compile_llvm_module(ac_llvm, ctx.ac.module, rbinary,
> shader_info,
> - MESA_SHADER_VERTEX, options);
> + MESA_SHADER_VERTEX, "GS Copy Shader",
> options);
> (*rbinary)->is_gs_copy_shader = true;
>
> }
> --
> 2.22.0
>
> ___
> mesa-dev mailing list
> mesa-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/mesa-dev
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 2/2] radv/gfx10: fix exporting clip/cull distances for GS
R-b On Thu, Jul 11, 2019, 5:02 PM Samuel Pitoiset wrote: > This fixes dEQP-VK.clipping.user_defined.clip_distance.*geom*. > > Signed-off-by: Samuel Pitoiset > --- > src/amd/vulkan/radv_nir_to_llvm.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/src/amd/vulkan/radv_nir_to_llvm.c > b/src/amd/vulkan/radv_nir_to_llvm.c > index 7da061f7f33..bf712b7fe45 100644 > --- a/src/amd/vulkan/radv_nir_to_llvm.c > +++ b/src/amd/vulkan/radv_nir_to_llvm.c > @@ -3656,7 +3656,8 @@ static void gfx10_ngg_gs_emit_epilogue_2(struct > radv_shader_context *ctx) > noutput++; > } > > - radv_llvm_export_vs(ctx, outputs, noutput, outinfo, false); > + radv_llvm_export_vs(ctx, outputs, noutput, outinfo, > + > ctx->options->key.vs_common_out.export_clip_dists); > FREE(outputs); > } > ac_build_endif(>ac, 5145); > -- > 2.22.0 > > ___ > mesa-dev mailing list > mesa-dev@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/mesa-dev ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 1/2] radv/gfx10: fix exporting the subpass view index for GS
R-b
On Thu, Jul 11, 2019, 5:02 PM Samuel Pitoiset
wrote:
> This fixes dEQP-VK.multiview.*geometry*.
>
> Signed-off-by: Samuel Pitoiset
> ---
> src/amd/vulkan/radv_nir_to_llvm.c | 16 +++-
> 1 file changed, 15 insertions(+), 1 deletion(-)
>
> diff --git a/src/amd/vulkan/radv_nir_to_llvm.c
> b/src/amd/vulkan/radv_nir_to_llvm.c
> index 11498bc27aa..7da061f7f33 100644
> --- a/src/amd/vulkan/radv_nir_to_llvm.c
> +++ b/src/amd/vulkan/radv_nir_to_llvm.c
> @@ -3583,11 +3583,12 @@ static void gfx10_ngg_gs_emit_epilogue_2(struct
> radv_shader_context *ctx)
> ac_build_ifcc(>ac, tmp, 5145);
> {
> struct radv_vs_output_info *outinfo =
> >shader_info->vs.outinfo;
> + bool export_view_index =
> ctx->options->key.has_multiview_view_index;
> struct radv_shader_output_values *outputs;
> unsigned noutput = 0;
>
> /* Allocate a temporary array for the output values. */
> - unsigned num_outputs = util_bitcount64(ctx->output_mask);
> + unsigned num_outputs = util_bitcount64(ctx->output_mask) +
> export_view_index;
> outputs = calloc(num_outputs, sizeof(outputs[0]));
>
> memset(outinfo->vs_output_param_offset,
> AC_EXP_PARAM_UNDEFINED,
> @@ -3642,6 +3643,19 @@ static void gfx10_ngg_gs_emit_epilogue_2(struct
> radv_shader_context *ctx)
> noutput++;
> }
>
> + /* Export ViewIndex. */
> + if (export_view_index) {
> + outinfo->writes_layer = true;
> +
> + outputs[noutput].slot_name = VARYING_SLOT_LAYER;
> + outputs[noutput].slot_index = 0;
> + outputs[noutput].usage_mask = 0x1;
> + outputs[noutput].values[0] = ac_to_float(>ac,
> ctx->abi.view_index);
> + for (unsigned j = 1; j < 4; j++)
> + outputs[noutput].values[j] = ctx->ac.f32_0;
> + noutput++;
> + }
> +
> radv_llvm_export_vs(ctx, outputs, noutput, outinfo, false);
> FREE(outputs);
> }
> --
> 2.22.0
>
> ___
> mesa-dev mailing list
> mesa-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/mesa-dev
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH] radeon/vcn: adding engine type for new fw interface
From: Boyuan Zhang Signed-off-by: Boyuan Zhang --- src/gallium/drivers/radeon/radeon_vcn_enc.h | 2 ++ src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c | 1 + src/gallium/drivers/radeon/radeon_vcn_enc_2_0.c | 4 ++-- 3 files changed, 5 insertions(+), 2 deletions(-) diff --git a/src/gallium/drivers/radeon/radeon_vcn_enc.h b/src/gallium/drivers/radeon/radeon_vcn_enc.h index fb800c3c6a3..bcff114ff18 100644 --- a/src/gallium/drivers/radeon/radeon_vcn_enc.h +++ b/src/gallium/drivers/radeon/radeon_vcn_enc.h @@ -42,6 +42,8 @@ #define RENCODE_IF_MINOR_VERSION_MASK 0x #define RENCODE_IF_MINOR_VERSION_SHIFT 0 +#define RENCODE_ENGINE_TYPE_ENCODE 1 + #define RENCODE_ENCODE_STANDARD_HEVC 0 #define RENCODE_ENCODE_STANDARD_H264 1 diff --git a/src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c b/src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c index 9a47affd14b..a437add48ee 100644 --- a/src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c +++ b/src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c @@ -69,6 +69,7 @@ static void radeon_enc_session_info(struct radeon_encoder *enc) RADEON_ENC_BEGIN(enc->cmd.session_info); RADEON_ENC_CS(enc->enc_pic.session_info.interface_version); RADEON_ENC_READWRITE(enc->si->res->buf, enc->si->res->domains, 0x0); + RADEON_ENC_CS(RENCODE_ENGINE_TYPE_ENCODE); RADEON_ENC_END(); } diff --git a/src/gallium/drivers/radeon/radeon_vcn_enc_2_0.c b/src/gallium/drivers/radeon/radeon_vcn_enc_2_0.c index dfad95a4dd9..d2c6378a055 100644 --- a/src/gallium/drivers/radeon/radeon_vcn_enc_2_0.c +++ b/src/gallium/drivers/radeon/radeon_vcn_enc_2_0.c @@ -35,8 +35,8 @@ #include "radeon_video.h" #include "radeon_vcn_enc.h" -#define RENCODE_FW_INTERFACE_MAJOR_VERSION 0 -#define RENCODE_FW_INTERFACE_MINOR_VERSION 2 +#define RENCODE_FW_INTERFACE_MAJOR_VERSION 1 +#define RENCODE_FW_INTERFACE_MINOR_VERSION 1 #define RENCODE_IB_PARAM_SESSION_INFO 0x0001 #define RENCODE_IB_PARAM_TASK_INFO 0x0002 -- 2.17.1 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] radv/gfx10: update OVERWRITE_COMBINER_{MRT_SHARING, WATERMARK}
r-b.
On Thu, 11 Jul 2019 at 23:51, Samuel Pitoiset wrote:
>
> DCC related, mirror RadeonSI.
>
> Signed-off-by: Samuel Pitoiset
> ---
> src/amd/vulkan/radv_cmd_buffer.c | 20
> 1 file changed, 4 insertions(+), 16 deletions(-)
>
> diff --git a/src/amd/vulkan/radv_cmd_buffer.c
> b/src/amd/vulkan/radv_cmd_buffer.c
> index b7ee0ff6422..a2a4cb0adb2 100644
> --- a/src/amd/vulkan/radv_cmd_buffer.c
> +++ b/src/amd/vulkan/radv_cmd_buffer.c
> @@ -1856,7 +1856,6 @@ radv_emit_framebuffer_state(struct radv_cmd_buffer
> *cmd_buffer)
> int i;
> struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
> const struct radv_subpass *subpass = cmd_buffer->state.subpass;
> - unsigned num_bpp64_colorbufs = 0;
>
> /* this may happen for inherited secondary recording */
> if (!framebuffer)
> @@ -1872,7 +1871,6 @@ radv_emit_framebuffer_state(struct radv_cmd_buffer
> *cmd_buffer)
> int idx = subpass->color_attachments[i].attachment;
> struct radv_attachment_info *att =
> >attachments[idx];
> struct radv_image_view *iview = att->attachment;
> - struct radv_image *image = iview->image;
> VkImageLayout layout = subpass->color_attachments[i].layout;
>
> radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
> att->attachment->bo);
> @@ -1882,9 +1880,6 @@ radv_emit_framebuffer_state(struct radv_cmd_buffer
> *cmd_buffer)
> radv_emit_fb_color_state(cmd_buffer, i, att, iview, layout);
>
> radv_load_color_clear_metadata(cmd_buffer, iview, i);
> -
> - if (image->planes[0].surface.bpe >= 8)
> - num_bpp64_colorbufs++;
> }
>
> if (subpass->depth_stencil_attachment) {
> @@ -1923,19 +1918,12 @@ radv_emit_framebuffer_state(struct radv_cmd_buffer
> *cmd_buffer)
> if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8)
> {
> bool disable_constant_encode =
>
> cmd_buffer->device->physical_device->has_dcc_constant_encode;
> - uint8_t watermark = 4; /* Default value for GFX8. */
> -
> - /* For optimal DCC performance. */
> - if (cmd_buffer->device->physical_device->rad_info.chip_class
> >= GFX9) {
> - if (num_bpp64_colorbufs >= 5) {
> - watermark = 8;
> - } else {
> - watermark = 6;
> - }
> - }
> + enum chip_class chip_class =
> +
> cmd_buffer->device->physical_device->rad_info.chip_class;
> + uint8_t watermark = chip_class >= GFX10 ? 6 : 4;
>
> radeon_set_context_reg(cmd_buffer->cs,
> R_028424_CB_DCC_CONTROL,
> -
> S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
> +
> S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(chip_class <= GFX9) |
>
> S_028424_OVERWRITE_COMBINER_WATERMARK(watermark) |
>
> S_028424_DISABLE_CONSTANT_ENCODE_REG(disable_constant_encode));
> }
> --
> 2.22.0
>
> ___
> mesa-dev mailing list
> mesa-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/mesa-dev
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] radv/gfx10: enable 1D textures
r-b
On Thu, Jul 11, 2019 at 5:22 PM Samuel Pitoiset
wrote:
>
> Mirror RadeonSI. This also fixes crashes in addrlib.
>
> Signed-off-by: Samuel Pitoiset
> ---
> src/amd/vulkan/radv_image.c| 4 ++--
> src/amd/vulkan/winsys/amdgpu/radv_amdgpu_surface.c | 6 --
> 2 files changed, 6 insertions(+), 4 deletions(-)
>
> diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
> index 368bd5d839d..ccbec36849e 100644
> --- a/src/amd/vulkan/radv_image.c
> +++ b/src/amd/vulkan/radv_image.c
> @@ -649,7 +649,7 @@ gfx10_make_texture_descriptor(struct radv_device *device,
> }
>
> type = radv_tex_dim(image->type, view_type, image->info.array_size,
> image->info.samples,
> - is_storage_image,
> device->physical_device->rad_info.chip_class >= GFX9);
> + is_storage_image,
> device->physical_device->rad_info.chip_class == GFX9);
> if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
> height = 1;
> depth = image->info.array_size;
> @@ -796,7 +796,7 @@ si_make_texture_descriptor(struct radv_device *device,
> data_format = V_008F14_IMG_DATA_FORMAT_S8_16;
> }
> type = radv_tex_dim(image->type, view_type, image->info.array_size,
> image->info.samples,
> - is_storage_image,
> device->physical_device->rad_info.chip_class >= GFX9);
> + is_storage_image,
> device->physical_device->rad_info.chip_class == GFX9);
> if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
> height = 1;
> depth = image->info.array_size;
> diff --git a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_surface.c
> b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_surface.c
> index 3f4cad861c2..598baa2addc 100644
> --- a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_surface.c
> +++ b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_surface.c
> @@ -90,8 +90,10 @@ static int radv_amdgpu_winsys_surface_init(struct
> radeon_winsys *_ws,
> struct ac_surf_config config;
>
> memcpy(, surf_info, sizeof(config.info));
> - config.is_3d = !!(type == RADEON_SURF_TYPE_3D);
> - config.is_cube = !!(type == RADEON_SURF_TYPE_CUBEMAP);
> + config.is_1d = type == RADEON_SURF_TYPE_1D ||
> + type == RADEON_SURF_TYPE_1D_ARRAY;
> + config.is_3d = type == RADEON_SURF_TYPE_3D;
> + config.is_cube = type == RADEON_SURF_TYPE_CUBEMAP;
>
> return ac_compute_surface(ws->addrlib, >info, , mode,
> surf);
> }
> --
> 2.22.0
>
> ___
> mesa-dev mailing list
> mesa-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/mesa-dev
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] mesa: save/restore SSO flag when using ARB_get_program_binary
Reviewed-by: Jordan Justen
On 2019-07-10 17:39:24, Timothy Arceri wrote:
> Ping! The spec bug was updated and they have agreed to update the spec
> to define this behavior.
>
> I've also sent a piglit test for this:
>
> https://patchwork.freedesktop.org/patch/317112/
>
> On 1/7/19 12:25 pm, Timothy Arceri wrote:
> > Without this the restored program will fail the pipeline validation
> > checks when we attempt to use an SSO program.
> >
> > Fixes: c20fd744fef1 ("mesa: Add Mesa ARB_get_program_binary helper
> > functions")
> >
> > Cc: Jordan Justen
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111010
> > ---
> > src/mesa/main/program_binary.c | 4
> > 1 file changed, 4 insertions(+)
> >
> > diff --git a/src/mesa/main/program_binary.c b/src/mesa/main/program_binary.c
> > index 7390fef5887..39537cfccce 100644
> > --- a/src/mesa/main/program_binary.c
> > +++ b/src/mesa/main/program_binary.c
> > @@ -178,6 +178,8 @@ write_program_payload(struct gl_context *ctx, struct
> > blob *blob,
> > shader->Program);
> > }
> >
> > + blob_write_uint32(blob, sh_prog->SeparateShader);
> > +
> > serialize_glsl_program(blob, ctx, sh_prog);
> >
> > for (unsigned stage = 0; stage < MESA_SHADER_STAGES; stage++) {
> > @@ -195,6 +197,8 @@ static bool
> > read_program_payload(struct gl_context *ctx, struct blob_reader *blob,
> >GLenum binary_format, struct gl_shader_program
> > *sh_prog)
> > {
> > + sh_prog->SeparateShader = blob_read_uint32(blob);
> > +
> > if (!deserialize_glsl_program(blob, ctx, sh_prog))
> > return false;
> >
> >
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] st/mesa: accelerate glCopyPixels(STENCIL)
The test passes here. I wouldn't push a commit that doesn't pass. It looks
like v3d can't blit stencil.
Marek
On Thu, Jul 11, 2019 at 6:29 AM apinheiro wrote:
> Hi, the following piglit test:
>
> ./bin/fbo-stencil copypixels GL_DEPTH32F_STENCIL8 -auto -fbo
>
> regressed after this patch landed master with the v3d driver. So Marek
> and anyone reading this email, could you execute that test and confirms
> if only regress with v3d?
>
> Thanks in advance.
>
> On 25/6/19 2:12, Marek Olšák wrote:
> > From: Marek Olšák
> >
> > ---
> > src/mesa/state_tracker/st_cb_drawpixels.c | 58 +++
> > 1 file changed, 38 insertions(+), 20 deletions(-)
> >
> > diff --git a/src/mesa/state_tracker/st_cb_drawpixels.c
> b/src/mesa/state_tracker/st_cb_drawpixels.c
> > index 59868d3ff1d..26d3cc33e5c 100644
> > --- a/src/mesa/state_tracker/st_cb_drawpixels.c
> > +++ b/src/mesa/state_tracker/st_cb_drawpixels.c
> > @@ -1508,35 +1508,35 @@ static GLboolean
> > blit_copy_pixels(struct gl_context *ctx, GLint srcx, GLint srcy,
> >GLsizei width, GLsizei height,
> >GLint dstx, GLint dsty, GLenum type)
> > {
> > struct st_context *st = st_context(ctx);
> > struct pipe_context *pipe = st->pipe;
> > struct pipe_screen *screen = pipe->screen;
> > struct gl_pixelstore_attrib pack, unpack;
> > GLint readX, readY, readW, readH, drawX, drawY, drawW, drawH;
> >
> > - if (type == GL_COLOR &&
> > - ctx->Pixel.ZoomX == 1.0 &&
> > + if (ctx->Pixel.ZoomX == 1.0 &&
> > ctx->Pixel.ZoomY == 1.0 &&
> > - ctx->_ImageTransferState == 0x0 &&
> > - !ctx->Color.BlendEnabled &&
> > - !ctx->Color.AlphaEnabled &&
> > - (!ctx->Color.ColorLogicOpEnabled || ctx->Color.LogicOp ==
> GL_COPY) &&
> > - !ctx->Depth.Test &&
> > - !ctx->Fog.Enabled &&
> > - !ctx->Stencil.Enabled &&
> > - !ctx->FragmentProgram.Enabled &&
> > - !ctx->VertexProgram.Enabled &&
> > - !ctx->_Shader->CurrentProgram[MESA_SHADER_FRAGMENT] &&
> > - !_mesa_ati_fragment_shader_enabled(ctx) &&
> > - ctx->DrawBuffer->_NumColorDrawBuffers == 1 &&
> > + (type != GL_COLOR ||
> > +(ctx->_ImageTransferState == 0x0 &&
> > + !ctx->Color.BlendEnabled &&
> > + !ctx->Color.AlphaEnabled &&
> > + (!ctx->Color.ColorLogicOpEnabled || ctx->Color.LogicOp ==
> GL_COPY) &&
> > + !ctx->Depth.Test &&
> > + !ctx->Fog.Enabled &&
> > + !ctx->Stencil.Enabled &&
> > + !ctx->FragmentProgram.Enabled &&
> > + !ctx->VertexProgram.Enabled &&
> > + !ctx->_Shader->CurrentProgram[MESA_SHADER_FRAGMENT] &&
> > + !_mesa_ati_fragment_shader_enabled(ctx) &&
> > + ctx->DrawBuffer->_NumColorDrawBuffers == 1)) &&
> > !ctx->Query.CondRenderQuery &&
> > !ctx->Query.CurrentOcclusionObject) {
> > struct st_renderbuffer *rbRead, *rbDraw;
> >
> > /*
> > * Clip the read region against the src buffer bounds.
> > * We'll still allocate a temporary buffer/texture for the
> original
> > * src region size but we'll only read the region which is
> on-screen.
> > * This may mean that we draw garbage pixels into the dest
> region, but
> > * that's expected.
> > @@ -1555,22 +1555,32 @@ blit_copy_pixels(struct gl_context *ctx, GLint
> srcx, GLint srcy,
> > unpack = pack;
> > if (!_mesa_clip_drawpixels(ctx, , , , ,
> ))
> >return GL_TRUE; /* all done */
> >
> > readX = readX - pack.SkipPixels + unpack.SkipPixels;
> > readY = readY - pack.SkipRows + unpack.SkipRows;
> >
> > drawW = readW;
> > drawH = readH;
> >
> > - rbRead = st_get_color_read_renderbuffer(ctx);
> > - rbDraw = st_renderbuffer(ctx->DrawBuffer->_ColorDrawBuffers[0]);
> > + if (type == GL_COLOR) {
> > + rbRead = st_get_color_read_renderbuffer(ctx);
> > + rbDraw =
> st_renderbuffer(ctx->DrawBuffer->_ColorDrawBuffers[0]);
> > + } else if (type == GL_DEPTH || type == GL_DEPTH_STENCIL) {
> > + rbRead =
> st_renderbuffer(ctx->ReadBuffer->Attachment[BUFFER_DEPTH].Renderbuffer);
> > + rbDraw =
> st_renderbuffer(ctx->DrawBuffer->Attachment[BUFFER_DEPTH].Renderbuffer);
> > + } else if (type == GL_STENCIL) {
> > + rbRead =
> st_renderbuffer(ctx->ReadBuffer->Attachment[BUFFER_STENCIL].Renderbuffer);
> > + rbDraw =
> st_renderbuffer(ctx->DrawBuffer->Attachment[BUFFER_STENCIL].Renderbuffer);
> > + } else {
> > + return false;
> > + }
> >
> > /* Flip src/dst position depending on the orientation of
> buffers. */
> > if (st_fb_orientation(ctx->ReadBuffer) == Y_0_TOP) {
> >readY = rbRead->Base.Height - readY;
> >readH = -readH;
> > }
> >
> > if (st_fb_orientation(ctx->DrawBuffer) == Y_0_TOP) {
> >/* We can't flip the destination for
[Mesa-dev] [PATCH] pipe-loader: use radeonsi for MM if amdgpu dri is used
From: Jeremy Newton
The amdgpu dri is used for the closed source AMD driver. Since this driver
does not implement multimedia, we fall back to radeonsi in mesa to do
multimedia. This corrects the dri driver name for when it is set to amdgpu.
Signed-off-by: Jeremy Newton
Signed-off-by: Marek Olšák
---
src/gallium/auxiliary/pipe-loader/pipe_loader_drm.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/src/gallium/auxiliary/pipe-loader/pipe_loader_drm.c
b/src/gallium/auxiliary/pipe-loader/pipe_loader_drm.c
index 960d63b2c31..6e889539c92 100644
--- a/src/gallium/auxiliary/pipe-loader/pipe_loader_drm.c
+++ b/src/gallium/auxiliary/pipe-loader/pipe_loader_drm.c
@@ -187,20 +187,25 @@ pipe_loader_drm_probe_fd_nodup(struct pipe_loader_device
**dev, int fd)
} else {
ddev->base.type = PIPE_LOADER_DEVICE_PLATFORM;
}
ddev->base.ops = _loader_drm_ops;
ddev->fd = fd;
ddev->base.driver_name = loader_get_driver_for_fd(fd);
if (!ddev->base.driver_name)
goto fail;
+ if (strcmp(ddev->base.driver_name, "amdgpu") == 0) {
+ FREE(ddev->base.driver_name);
+ ddev->base.driver_name = strdup("radeonsi");
+ }
+
struct util_dl_library **plib = NULL;
#ifndef GALLIUM_STATIC_TARGETS
plib = >lib;
#endif
ddev->dd = get_driver_descriptor(ddev->base.driver_name, plib);
if (!ddev->dd)
goto fail;
*dev = >base;
return true;
--
2.17.1
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH] radv/gfx10: do not set alignment on the ngg_emit pointer
This is invalid and this fixes a crash in LLVM. Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_nir_to_llvm.c | 1 - 1 file changed, 1 deletion(-) diff --git a/src/amd/vulkan/radv_nir_to_llvm.c b/src/amd/vulkan/radv_nir_to_llvm.c index bf712b7fe45..32548857b57 100644 --- a/src/amd/vulkan/radv_nir_to_llvm.c +++ b/src/amd/vulkan/radv_nir_to_llvm.c @@ -4326,7 +4326,6 @@ LLVMModuleRef ac_translate_nir_to_llvm(struct ac_llvm_compiler *ac_llvm, ctx.gs_ngg_emit = LLVMBuildIntToPtr(ctx.ac.builder, ctx.ac.i32_0, LLVMPointerType(LLVMArrayType(ctx.ac.i32, 0), AC_ADDR_SPACE_LDS), "ngg_emit"); - LLVMSetAlignment(ctx.gs_ngg_emit, 4); } ctx.gs_max_out_vertices = shaders[i]->info.gs.vertices_out; -- 2.22.0 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH] radv/gfx10: enable 1D textures
Mirror RadeonSI. This also fixes crashes in addrlib.
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_image.c| 4 ++--
src/amd/vulkan/winsys/amdgpu/radv_amdgpu_surface.c | 6 --
2 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index 368bd5d839d..ccbec36849e 100644
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -649,7 +649,7 @@ gfx10_make_texture_descriptor(struct radv_device *device,
}
type = radv_tex_dim(image->type, view_type, image->info.array_size,
image->info.samples,
- is_storage_image,
device->physical_device->rad_info.chip_class >= GFX9);
+ is_storage_image,
device->physical_device->rad_info.chip_class == GFX9);
if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
height = 1;
depth = image->info.array_size;
@@ -796,7 +796,7 @@ si_make_texture_descriptor(struct radv_device *device,
data_format = V_008F14_IMG_DATA_FORMAT_S8_16;
}
type = radv_tex_dim(image->type, view_type, image->info.array_size,
image->info.samples,
- is_storage_image,
device->physical_device->rad_info.chip_class >= GFX9);
+ is_storage_image,
device->physical_device->rad_info.chip_class == GFX9);
if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
height = 1;
depth = image->info.array_size;
diff --git a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_surface.c
b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_surface.c
index 3f4cad861c2..598baa2addc 100644
--- a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_surface.c
+++ b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_surface.c
@@ -90,8 +90,10 @@ static int radv_amdgpu_winsys_surface_init(struct
radeon_winsys *_ws,
struct ac_surf_config config;
memcpy(, surf_info, sizeof(config.info));
- config.is_3d = !!(type == RADEON_SURF_TYPE_3D);
- config.is_cube = !!(type == RADEON_SURF_TYPE_CUBEMAP);
+ config.is_1d = type == RADEON_SURF_TYPE_1D ||
+ type == RADEON_SURF_TYPE_1D_ARRAY;
+ config.is_3d = type == RADEON_SURF_TYPE_3D;
+ config.is_cube = type == RADEON_SURF_TYPE_CUBEMAP;
return ac_compute_surface(ws->addrlib, >info, , mode, surf);
}
--
2.22.0
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 2/2] radv: report shader stage name when dumping LLVM IR
For debugging purposes.
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_nir_to_llvm.c | 21 +
1 file changed, 17 insertions(+), 4 deletions(-)
diff --git a/src/amd/vulkan/radv_nir_to_llvm.c
b/src/amd/vulkan/radv_nir_to_llvm.c
index 32548857b57..e4ab5847729 100644
--- a/src/amd/vulkan/radv_nir_to_llvm.c
+++ b/src/amd/vulkan/radv_nir_to_llvm.c
@@ -4434,8 +4434,13 @@ LLVMModuleRef ac_translate_nir_to_llvm(struct
ac_llvm_compiler *ac_llvm,
LLVMBuildRetVoid(ctx.ac.builder);
- if (options->dump_preoptir)
+ if (options->dump_preoptir) {
+ fprintf(stderr, "%s LLVM IR:\n\n",
+ radv_get_shader_name(shader_info,
+shaders[shader_count -
1]->info.stage));
ac_dump_module(ctx.ac.module);
+ fprintf(stderr, "\n");
+ }
ac_llvm_finalize_module(, ac_llvm->passmgr, options);
@@ -4489,13 +4494,18 @@ static void ac_compile_llvm_module(struct
ac_llvm_compiler *ac_llvm,
struct radv_shader_binary **rbinary,
struct radv_shader_variant_info *shader_info,
gl_shader_stage stage,
+ const char *name,
const struct radv_nir_compiler_options
*options)
{
char *elf_buffer = NULL;
size_t elf_size = 0;
char *llvm_ir_string = NULL;
- if (options->dump_shader)
+
+ if (options->dump_shader) {
+ fprintf(stderr, "%s LLVM IR:\n\n", name);
ac_dump_module(llvm_module);
+ fprintf(stderr, "\n");
+ }
if (options->record_llvm_ir) {
char *llvm_ir = LLVMPrintModuleToString(llvm_module);
@@ -4585,7 +4595,10 @@ radv_compile_nir_shader(struct ac_llvm_compiler *ac_llvm,
options);
ac_compile_llvm_module(ac_llvm, llvm_module, rbinary, shader_info,
- nir[nir_count - 1]->info.stage, options);
+ nir[nir_count - 1]->info.stage,
+ radv_get_shader_name(shader_info,
+ nir[nir_count -
1]->info.stage),
+ options);
for (int i = 0; i < nir_count; ++i)
ac_fill_shader_info(shader_info, nir[i], options);
@@ -4737,7 +4750,7 @@ radv_compile_gs_copy_shader(struct ac_llvm_compiler
*ac_llvm,
ac_llvm_finalize_module(, ac_llvm->passmgr, options);
ac_compile_llvm_module(ac_llvm, ctx.ac.module, rbinary, shader_info,
- MESA_SHADER_VERTEX, options);
+ MESA_SHADER_VERTEX, "GS Copy Shader", options);
(*rbinary)->is_gs_copy_shader = true;
}
--
2.22.0
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 1/2] radv: tidy up radv_get_shader_name() and add NGG stages
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_debug.c | 4 ++--
src/amd/vulkan/radv_shader.c | 37 +++-
src/amd/vulkan/radv_shader.h | 3 ++-
3 files changed, 32 insertions(+), 12 deletions(-)
diff --git a/src/amd/vulkan/radv_debug.c b/src/amd/vulkan/radv_debug.c
index 42296745543..49b7417e988 100644
--- a/src/amd/vulkan/radv_debug.c
+++ b/src/amd/vulkan/radv_debug.c
@@ -406,7 +406,7 @@ radv_dump_annotated_shader(struct radv_shader_variant
*shader,
start_addr, _inst, instructions);
fprintf(f, COLOR_YELLOW "%s - annotated disassembly:" COLOR_RESET "\n",
- radv_get_shader_name(shader, stage));
+ radv_get_shader_name(>info, stage));
/* Print instructions with annotations. */
for (i = 0; i < num_inst; i++) {
@@ -490,7 +490,7 @@ radv_dump_shader(struct radv_pipeline *pipeline,
if (!shader)
return;
- fprintf(f, "%s:\n\n", radv_get_shader_name(shader, stage));
+ fprintf(f, "%s:\n\n", radv_get_shader_name(>info, stage));
if (shader->spirv) {
unsigned char sha1[21];
diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
index 4ec4e88349d..8f37c2bfb67 100644
--- a/src/amd/vulkan/radv_shader.c
+++ b/src/amd/vulkan/radv_shader.c
@@ -1152,15 +1152,34 @@ radv_shader_variant_destroy(struct radv_device *device,
}
const char *
-radv_get_shader_name(struct radv_shader_variant *var, gl_shader_stage stage)
+radv_get_shader_name(struct radv_shader_variant_info *info,
+gl_shader_stage stage)
{
switch (stage) {
- case MESA_SHADER_VERTEX: return var->info.vs.as_ls ? "Vertex Shader as
LS" : var->info.vs.as_es ? "Vertex Shader as ES" : "Vertex Shader as VS";
- case MESA_SHADER_GEOMETRY: return "Geometry Shader";
- case MESA_SHADER_FRAGMENT: return "Pixel Shader";
- case MESA_SHADER_COMPUTE: return "Compute Shader";
- case MESA_SHADER_TESS_CTRL: return "Tessellation Control Shader";
- case MESA_SHADER_TESS_EVAL: return var->info.tes.as_es ? "Tessellation
Evaluation Shader as ES" : "Tessellation Evaluation Shader as VS";
+ case MESA_SHADER_VERTEX:
+ if (info->vs.as_ls)
+ return "Vertex Shader as LS";
+ else if (info->vs.as_es)
+ return "Vertex Shader as ES";
+ else if (info->is_ngg)
+ return "Vertex Shader as ESGS";
+ else
+ return "Vertex Shader as VS";
+ case MESA_SHADER_TESS_CTRL:
+ return "Tessellation Control Shader";
+ case MESA_SHADER_TESS_EVAL:
+ if (info->tes.as_es)
+ return "Tessellation Evaluation Shader as ES";
+ else if (info->is_ngg)
+ return "Tessellation Evaluation Shader as ESGS";
+ else
+ return "Tessellation Evaluation Shader as VS";
+ case MESA_SHADER_GEOMETRY:
+ return "Geometry Shader";
+ case MESA_SHADER_FRAGMENT:
+ return "Pixel Shader";
+ case MESA_SHADER_COMPUTE:
+ return "Compute Shader";
default:
return "Unknown shader";
};
@@ -1244,7 +1263,7 @@ radv_shader_dump_stats(struct radv_device *device,
generate_shader_stats(device, variant, stage, buf);
- fprintf(file, "\n%s:\n", radv_get_shader_name(variant, stage));
+ fprintf(file, "\n%s:\n", radv_get_shader_name(>info, stage));
fprintf(file, "%s", buf->buf);
_mesa_string_buffer_destroy(buf);
@@ -1317,7 +1336,7 @@ radv_GetShaderInfoAMD(VkDevice _device,
case VK_SHADER_INFO_TYPE_DISASSEMBLY_AMD:
buf = _mesa_string_buffer_create(NULL, 1024);
- _mesa_string_buffer_printf(buf, "%s:\n",
radv_get_shader_name(variant, stage));
+ _mesa_string_buffer_printf(buf, "%s:\n",
radv_get_shader_name(>info, stage));
_mesa_string_buffer_printf(buf, "%s\n\n",
variant->llvm_ir_string);
_mesa_string_buffer_printf(buf, "%s\n\n",
variant->disasm_string);
generate_shader_stats(device, variant, stage, buf);
diff --git a/src/amd/vulkan/radv_shader.h b/src/amd/vulkan/radv_shader.h
index 8506aa1d9f0..360591349a8 100644
--- a/src/amd/vulkan/radv_shader.h
+++ b/src/amd/vulkan/radv_shader.h
@@ -421,7 +421,8 @@ radv_shader_variant_destroy(struct radv_device *device,
struct radv_shader_variant *variant);
const char *
-radv_get_shader_name(struct radv_shader_variant *var, gl_shader_stage stage);
+radv_get_shader_name(struct radv_shader_variant_info *info,
+gl_shader_stage stage);
void
radv_shader_dump_stats(struct radv_device *device,
--
2.22.0
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
[Mesa-dev] [PATCH] radv/gfx10: enable 1D textures
Mirror RadeonSI. This also fixes crashes in addrlib.
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_image.c| 4 ++--
src/amd/vulkan/winsys/amdgpu/radv_amdgpu_surface.c | 6 --
2 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index 368bd5d839d..ccbec36849e 100644
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -649,7 +649,7 @@ gfx10_make_texture_descriptor(struct radv_device *device,
}
type = radv_tex_dim(image->type, view_type, image->info.array_size,
image->info.samples,
- is_storage_image,
device->physical_device->rad_info.chip_class >= GFX9);
+ is_storage_image,
device->physical_device->rad_info.chip_class == GFX9);
if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
height = 1;
depth = image->info.array_size;
@@ -796,7 +796,7 @@ si_make_texture_descriptor(struct radv_device *device,
data_format = V_008F14_IMG_DATA_FORMAT_S8_16;
}
type = radv_tex_dim(image->type, view_type, image->info.array_size,
image->info.samples,
- is_storage_image,
device->physical_device->rad_info.chip_class >= GFX9);
+ is_storage_image,
device->physical_device->rad_info.chip_class == GFX9);
if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
height = 1;
depth = image->info.array_size;
diff --git a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_surface.c
b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_surface.c
index 3f4cad861c2..598baa2addc 100644
--- a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_surface.c
+++ b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_surface.c
@@ -90,8 +90,10 @@ static int radv_amdgpu_winsys_surface_init(struct
radeon_winsys *_ws,
struct ac_surf_config config;
memcpy(, surf_info, sizeof(config.info));
- config.is_3d = !!(type == RADEON_SURF_TYPE_3D);
- config.is_cube = !!(type == RADEON_SURF_TYPE_CUBEMAP);
+ config.is_1d = type == RADEON_SURF_TYPE_1D ||
+ type == RADEON_SURF_TYPE_1D_ARRAY;
+ config.is_3d = type == RADEON_SURF_TYPE_3D;
+ config.is_cube = type == RADEON_SURF_TYPE_CUBEMAP;
return ac_compute_surface(ws->addrlib, >info, , mode, surf);
}
--
2.22.0
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 2/2] radv/gfx10: fix exporting clip/cull distances for GS
This fixes dEQP-VK.clipping.user_defined.clip_distance.*geom*. Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_nir_to_llvm.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/amd/vulkan/radv_nir_to_llvm.c b/src/amd/vulkan/radv_nir_to_llvm.c index 7da061f7f33..bf712b7fe45 100644 --- a/src/amd/vulkan/radv_nir_to_llvm.c +++ b/src/amd/vulkan/radv_nir_to_llvm.c @@ -3656,7 +3656,8 @@ static void gfx10_ngg_gs_emit_epilogue_2(struct radv_shader_context *ctx) noutput++; } - radv_llvm_export_vs(ctx, outputs, noutput, outinfo, false); + radv_llvm_export_vs(ctx, outputs, noutput, outinfo, + ctx->options->key.vs_common_out.export_clip_dists); FREE(outputs); } ac_build_endif(>ac, 5145); -- 2.22.0 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 1/2] radv/gfx10: fix exporting the subpass view index for GS
This fixes dEQP-VK.multiview.*geometry*.
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_nir_to_llvm.c | 16 +++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff --git a/src/amd/vulkan/radv_nir_to_llvm.c
b/src/amd/vulkan/radv_nir_to_llvm.c
index 11498bc27aa..7da061f7f33 100644
--- a/src/amd/vulkan/radv_nir_to_llvm.c
+++ b/src/amd/vulkan/radv_nir_to_llvm.c
@@ -3583,11 +3583,12 @@ static void gfx10_ngg_gs_emit_epilogue_2(struct
radv_shader_context *ctx)
ac_build_ifcc(>ac, tmp, 5145);
{
struct radv_vs_output_info *outinfo =
>shader_info->vs.outinfo;
+ bool export_view_index =
ctx->options->key.has_multiview_view_index;
struct radv_shader_output_values *outputs;
unsigned noutput = 0;
/* Allocate a temporary array for the output values. */
- unsigned num_outputs = util_bitcount64(ctx->output_mask);
+ unsigned num_outputs = util_bitcount64(ctx->output_mask) +
export_view_index;
outputs = calloc(num_outputs, sizeof(outputs[0]));
memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
@@ -3642,6 +3643,19 @@ static void gfx10_ngg_gs_emit_epilogue_2(struct
radv_shader_context *ctx)
noutput++;
}
+ /* Export ViewIndex. */
+ if (export_view_index) {
+ outinfo->writes_layer = true;
+
+ outputs[noutput].slot_name = VARYING_SLOT_LAYER;
+ outputs[noutput].slot_index = 0;
+ outputs[noutput].usage_mask = 0x1;
+ outputs[noutput].values[0] = ac_to_float(>ac,
ctx->abi.view_index);
+ for (unsigned j = 1; j < 4; j++)
+ outputs[noutput].values[j] = ctx->ac.f32_0;
+ noutput++;
+ }
+
radv_llvm_export_vs(ctx, outputs, noutput, outinfo, false);
FREE(outputs);
}
--
2.22.0
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] st/mesa: accelerate glCopyPixels(STENCIL)
On 2019-07-11 12:29 p.m., apinheiro wrote: > Hi, the following piglit test: > > ./bin/fbo-stencil copypixels GL_DEPTH32F_STENCIL8 -auto -fbo > > regressed after this patch landed master with the v3d driver. So Marek > and anyone reading this email, could you execute that test and confirms > if only regress with v3d? It still passes for me with radeonsi & llvmpipe. -- Earthling Michel Dänzer | https://www.amd.com Libre software enthusiast | Mesa and X developer ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH] radv/gfx10: update OVERWRITE_COMBINER_{MRT_SHARING, WATERMARK}
DCC related, mirror RadeonSI.
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_cmd_buffer.c | 20
1 file changed, 4 insertions(+), 16 deletions(-)
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index b7ee0ff6422..a2a4cb0adb2 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -1856,7 +1856,6 @@ radv_emit_framebuffer_state(struct radv_cmd_buffer
*cmd_buffer)
int i;
struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
const struct radv_subpass *subpass = cmd_buffer->state.subpass;
- unsigned num_bpp64_colorbufs = 0;
/* this may happen for inherited secondary recording */
if (!framebuffer)
@@ -1872,7 +1871,6 @@ radv_emit_framebuffer_state(struct radv_cmd_buffer
*cmd_buffer)
int idx = subpass->color_attachments[i].attachment;
struct radv_attachment_info *att =
>attachments[idx];
struct radv_image_view *iview = att->attachment;
- struct radv_image *image = iview->image;
VkImageLayout layout = subpass->color_attachments[i].layout;
radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
att->attachment->bo);
@@ -1882,9 +1880,6 @@ radv_emit_framebuffer_state(struct radv_cmd_buffer
*cmd_buffer)
radv_emit_fb_color_state(cmd_buffer, i, att, iview, layout);
radv_load_color_clear_metadata(cmd_buffer, iview, i);
-
- if (image->planes[0].surface.bpe >= 8)
- num_bpp64_colorbufs++;
}
if (subpass->depth_stencil_attachment) {
@@ -1923,19 +1918,12 @@ radv_emit_framebuffer_state(struct radv_cmd_buffer
*cmd_buffer)
if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8) {
bool disable_constant_encode =
cmd_buffer->device->physical_device->has_dcc_constant_encode;
- uint8_t watermark = 4; /* Default value for GFX8. */
-
- /* For optimal DCC performance. */
- if (cmd_buffer->device->physical_device->rad_info.chip_class >=
GFX9) {
- if (num_bpp64_colorbufs >= 5) {
- watermark = 8;
- } else {
- watermark = 6;
- }
- }
+ enum chip_class chip_class =
+
cmd_buffer->device->physical_device->rad_info.chip_class;
+ uint8_t watermark = chip_class >= GFX10 ? 6 : 4;
radeon_set_context_reg(cmd_buffer->cs, R_028424_CB_DCC_CONTROL,
-
S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
+
S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(chip_class <= GFX9) |
S_028424_OVERWRITE_COMBINER_WATERMARK(watermark) |
S_028424_DISABLE_CONSTANT_ENCODE_REG(disable_constant_encode));
}
--
2.22.0
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 111109] mythtv rendering on gles surface gives black screen on lima/mali450
https://bugs.freedesktop.org/show_bug.cgi?id=09 Bug ID: 09 Summary: mythtv rendering on gles surface gives black screen on lima/mali450 Product: Mesa Version: git Hardware: ARM OS: Linux (All) Status: NEW Severity: normal Priority: medium Component: Drivers/Gallium/Lima Assignee: mesa-dev@lists.freedesktop.org Reporter: war...@o2.pl Created attachment 144763 --> https://bugs.freedesktop.org/attachment.cgi?id=144763=edit api trace from gles rendering on rpi3 Playback of video with gles rendering in mythtv gives black screen on lima/mali450 (amlogic s905). The same software/os plays ok on mesa/vc4 (rpi3). API trace attached. -- You are receiving this mail because: You are the assignee for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] panfrost/midgard: Use _safe iterator
R-b signature.asc Description: PGP signature ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH v2] panfrost: Place the height value in the height field
This hunk is R-b, the rest are NAK-ed due to reasons I'm sure you realize (breaking MFBD ;) ) signature.asc Description: PGP signature ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] radv/gfx10: fix maximum number of mip levels for 3D images
r-b
On Thu, Jul 11, 2019 at 2:24 PM Samuel Pitoiset
wrote:
>
> The dimensions also have to be adjusted if the number of supported
> mip levels is changed.
>
> This fixes dEQP-VK.api.info.image_format_properties.3d.*.
>
> Signed-off-by: Samuel Pitoiset
> ---
> src/amd/vulkan/radv_formats.c | 14 ++
> 1 file changed, 10 insertions(+), 4 deletions(-)
>
> diff --git a/src/amd/vulkan/radv_formats.c b/src/amd/vulkan/radv_formats.c
> index 26fc4b9ba18..98c84edbdc1 100644
> --- a/src/amd/vulkan/radv_formats.c
> +++ b/src/amd/vulkan/radv_formats.c
> @@ -1150,10 +1150,16 @@ static VkResult
> radv_get_image_format_properties(struct radv_physical_device *ph
> maxArraySize = chip_class >= GFX10 ? 8192 : 2048;
> break;
> case VK_IMAGE_TYPE_3D:
> - maxExtent.width = 2048;
> - maxExtent.height = 2048;
> - maxExtent.depth = 2048;
> - maxMipLevels = chip_class >= GFX10 ? 14 : 12; /*
> log2(maxWidth) + 1 */
> + if (chip_class >= GFX10) {
> + maxExtent.width = 8192;
> + maxExtent.height = 8192;
> + maxExtent.depth = 8192;
> + } else {
> + maxExtent.width = 2048;
> + maxExtent.height = 2048;
> + maxExtent.depth = 2048;
> + }
> + maxMipLevels = util_logbase2(maxExtent.width) + 1;
> maxArraySize = 1;
> break;
> }
> --
> 2.22.0
>
> ___
> mesa-dev mailing list
> mesa-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/mesa-dev
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH] radv/gfx10: fix maximum number of mip levels for 3D images
The dimensions also have to be adjusted if the number of supported
mip levels is changed.
This fixes dEQP-VK.api.info.image_format_properties.3d.*.
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_formats.c | 14 ++
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/src/amd/vulkan/radv_formats.c b/src/amd/vulkan/radv_formats.c
index 26fc4b9ba18..98c84edbdc1 100644
--- a/src/amd/vulkan/radv_formats.c
+++ b/src/amd/vulkan/radv_formats.c
@@ -1150,10 +1150,16 @@ static VkResult radv_get_image_format_properties(struct
radv_physical_device *ph
maxArraySize = chip_class >= GFX10 ? 8192 : 2048;
break;
case VK_IMAGE_TYPE_3D:
- maxExtent.width = 2048;
- maxExtent.height = 2048;
- maxExtent.depth = 2048;
- maxMipLevels = chip_class >= GFX10 ? 14 : 12; /* log2(maxWidth)
+ 1 */
+ if (chip_class >= GFX10) {
+ maxExtent.width = 8192;
+ maxExtent.height = 8192;
+ maxExtent.depth = 8192;
+ } else {
+ maxExtent.width = 2048;
+ maxExtent.height = 2048;
+ maxExtent.depth = 2048;
+ }
+ maxMipLevels = util_logbase2(maxExtent.width) + 1;
maxArraySize = 1;
break;
}
--
2.22.0
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 111107] 726a31df705b causes the in memory shader cache to use up to 5x more memory
https://bugs.freedesktop.org/show_bug.cgi?id=07 Bug ID: 07 Summary: 726a31df705b causes the in memory shader cache to use up to 5x more memory Product: Mesa Version: git Hardware: Other OS: All Status: NEW Severity: normal Priority: medium Component: Drivers/Vulkan/radeon Assignee: mesa-dev@lists.freedesktop.org Reporter: t_arc...@yahoo.com.au QA Contact: mesa-dev@lists.freedesktop.org For example using fossilize-replay to replay the fossilze db from the free to play game WarFrame [1] results in memory use going from 1GB+ before the commit to 5GB+ after the commit. I've looked into it briefly and fixed one memory leak from the commit but extra memory use remained unchanged. I'm noting it here in a bug report until this is investigated properly. [1] ~/.steam/steamapps/shadercache/230410/fozpipelinesv4/steam_pipeline_cache.foz -- You are receiving this mail because: You are the QA Contact for the bug. You are the assignee for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] radv/gfx10: disable TC-compat HTILE for multisampled D32_SFLOAT format
r-b On Thu, Jul 11, 2019 at 11:54 AM Samuel Pitoiset wrote: > > For some reasons D32_SFLOAT is also affected on GFX10, it works > fine with previous generations. > > This fixes some dEQP-VK.renderpass2.depth_stencil_resolve.*. > > Signed-off-by: Samuel Pitoiset > --- > src/amd/vulkan/radv_image.c | 7 +-- > 1 file changed, 5 insertions(+), 2 deletions(-) > > diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c > index 6245873a4ed..368bd5d839d 100644 > --- a/src/amd/vulkan/radv_image.c > +++ b/src/amd/vulkan/radv_image.c > @@ -83,9 +83,12 @@ radv_use_tc_compat_htile_for_image(struct radv_device > *device, > return false; > > /* FIXME: for some reason TC compat with 2/4/8 samples breaks some cts > -* tests - disable for now */ > +* tests - disable for now. On GFX10 D32_SFLOAT is affected as well. > +*/ > if (pCreateInfo->samples >= 2 && > - pCreateInfo->format == VK_FORMAT_D32_SFLOAT_S8_UINT) > + (pCreateInfo->format == VK_FORMAT_D32_SFLOAT_S8_UINT || > +(pCreateInfo->format == VK_FORMAT_D32_SFLOAT && > + device->physical_device->rad_info.chip_class == GFX10))) > return false; > > /* GFX9 supports both 32-bit and 16-bit depth surfaces, while GFX8 > only > -- > 2.22.0 > > ___ > mesa-dev mailing list > mesa-dev@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/mesa-dev ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] st/mesa: accelerate glCopyPixels(STENCIL)
Hi, the following piglit test:
./bin/fbo-stencil copypixels GL_DEPTH32F_STENCIL8 -auto -fbo
regressed after this patch landed master with the v3d driver. So Marek
and anyone reading this email, could you execute that test and confirms
if only regress with v3d?
Thanks in advance.
On 25/6/19 2:12, Marek Olšák wrote:
From: Marek Olšák
---
src/mesa/state_tracker/st_cb_drawpixels.c | 58 +++
1 file changed, 38 insertions(+), 20 deletions(-)
diff --git a/src/mesa/state_tracker/st_cb_drawpixels.c
b/src/mesa/state_tracker/st_cb_drawpixels.c
index 59868d3ff1d..26d3cc33e5c 100644
--- a/src/mesa/state_tracker/st_cb_drawpixels.c
+++ b/src/mesa/state_tracker/st_cb_drawpixels.c
@@ -1508,35 +1508,35 @@ static GLboolean
blit_copy_pixels(struct gl_context *ctx, GLint srcx, GLint srcy,
GLsizei width, GLsizei height,
GLint dstx, GLint dsty, GLenum type)
{
struct st_context *st = st_context(ctx);
struct pipe_context *pipe = st->pipe;
struct pipe_screen *screen = pipe->screen;
struct gl_pixelstore_attrib pack, unpack;
GLint readX, readY, readW, readH, drawX, drawY, drawW, drawH;
- if (type == GL_COLOR &&
- ctx->Pixel.ZoomX == 1.0 &&
+ if (ctx->Pixel.ZoomX == 1.0 &&
ctx->Pixel.ZoomY == 1.0 &&
- ctx->_ImageTransferState == 0x0 &&
- !ctx->Color.BlendEnabled &&
- !ctx->Color.AlphaEnabled &&
- (!ctx->Color.ColorLogicOpEnabled || ctx->Color.LogicOp == GL_COPY) &&
- !ctx->Depth.Test &&
- !ctx->Fog.Enabled &&
- !ctx->Stencil.Enabled &&
- !ctx->FragmentProgram.Enabled &&
- !ctx->VertexProgram.Enabled &&
- !ctx->_Shader->CurrentProgram[MESA_SHADER_FRAGMENT] &&
- !_mesa_ati_fragment_shader_enabled(ctx) &&
- ctx->DrawBuffer->_NumColorDrawBuffers == 1 &&
+ (type != GL_COLOR ||
+(ctx->_ImageTransferState == 0x0 &&
+ !ctx->Color.BlendEnabled &&
+ !ctx->Color.AlphaEnabled &&
+ (!ctx->Color.ColorLogicOpEnabled || ctx->Color.LogicOp == GL_COPY) &&
+ !ctx->Depth.Test &&
+ !ctx->Fog.Enabled &&
+ !ctx->Stencil.Enabled &&
+ !ctx->FragmentProgram.Enabled &&
+ !ctx->VertexProgram.Enabled &&
+ !ctx->_Shader->CurrentProgram[MESA_SHADER_FRAGMENT] &&
+ !_mesa_ati_fragment_shader_enabled(ctx) &&
+ ctx->DrawBuffer->_NumColorDrawBuffers == 1)) &&
!ctx->Query.CondRenderQuery &&
!ctx->Query.CurrentOcclusionObject) {
struct st_renderbuffer *rbRead, *rbDraw;
/*
* Clip the read region against the src buffer bounds.
* We'll still allocate a temporary buffer/texture for the original
* src region size but we'll only read the region which is on-screen.
* This may mean that we draw garbage pixels into the dest region, but
* that's expected.
@@ -1555,22 +1555,32 @@ blit_copy_pixels(struct gl_context *ctx, GLint srcx,
GLint srcy,
unpack = pack;
if (!_mesa_clip_drawpixels(ctx, , , , ,
))
return GL_TRUE; /* all done */
readX = readX - pack.SkipPixels + unpack.SkipPixels;
readY = readY - pack.SkipRows + unpack.SkipRows;
drawW = readW;
drawH = readH;
- rbRead = st_get_color_read_renderbuffer(ctx);
- rbDraw = st_renderbuffer(ctx->DrawBuffer->_ColorDrawBuffers[0]);
+ if (type == GL_COLOR) {
+ rbRead = st_get_color_read_renderbuffer(ctx);
+ rbDraw = st_renderbuffer(ctx->DrawBuffer->_ColorDrawBuffers[0]);
+ } else if (type == GL_DEPTH || type == GL_DEPTH_STENCIL) {
+ rbRead =
st_renderbuffer(ctx->ReadBuffer->Attachment[BUFFER_DEPTH].Renderbuffer);
+ rbDraw =
st_renderbuffer(ctx->DrawBuffer->Attachment[BUFFER_DEPTH].Renderbuffer);
+ } else if (type == GL_STENCIL) {
+ rbRead =
st_renderbuffer(ctx->ReadBuffer->Attachment[BUFFER_STENCIL].Renderbuffer);
+ rbDraw =
st_renderbuffer(ctx->DrawBuffer->Attachment[BUFFER_STENCIL].Renderbuffer);
+ } else {
+ return false;
+ }
/* Flip src/dst position depending on the orientation of buffers. */
if (st_fb_orientation(ctx->ReadBuffer) == Y_0_TOP) {
readY = rbRead->Base.Height - readY;
readH = -readH;
}
if (st_fb_orientation(ctx->DrawBuffer) == Y_0_TOP) {
/* We can't flip the destination for pipe->blit, so we only adjust
* its position and flip the source.
@@ -1597,23 +1607,31 @@ blit_copy_pixels(struct gl_context *ctx, GLint srcx,
GLint srcy,
blit.src.box.depth = 1;
blit.dst.resource = rbDraw->texture;
blit.dst.level = rbDraw->surface->u.tex.level;
blit.dst.format = rbDraw->texture->format;
blit.dst.box.x = drawX;
blit.dst.box.y = drawY;
blit.dst.box.z = rbDraw->surface->u.tex.first_layer;
blit.dst.box.width = drawW;
[Mesa-dev] [PATCH] panfrost/midgard: Use _safe iterator
Fixes this assertion:
../mesa/src/panfrost/midgard/midgard_schedule.c:507:schedule_block: Assertion
`ins == __next && "use _safe iterator"' failed.
Trace/breakpoint trap
Signed-off-by: Tomeu Vizoso
---
src/panfrost/midgard/midgard_schedule.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/panfrost/midgard/midgard_schedule.c
b/src/panfrost/midgard/midgard_schedule.c
index 7a3841e4d44d..3e78020f6d68 100644
--- a/src/panfrost/midgard/midgard_schedule.c
+++ b/src/panfrost/midgard/midgard_schedule.c
@@ -504,7 +504,7 @@ schedule_block(compiler_context *ctx, midgard_block *block)
block->quadword_count = 0;
-mir_foreach_instr_in_block(block, ins) {
+mir_foreach_instr_in_block_safe(block, ins) {
int skip;
midgard_bundle bundle = schedule_bundle(ctx, block, ins,
);
util_dynarray_append(>bundles, midgard_bundle, bundle);
--
2.20.1
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH v2] panfrost: Place the height value in the height field
In the mali_single_framebuffer descriptor.
Signed-off-by: Tomeu Vizoso
v2: Remove unwanted chunks
---
src/gallium/drivers/panfrost/pan_context.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/gallium/drivers/panfrost/pan_context.c
b/src/gallium/drivers/panfrost/pan_context.c
index cb55dc66e799..b3545e1748a7 100644
--- a/src/gallium/drivers/panfrost/pan_context.c
+++ b/src/gallium/drivers/panfrost/pan_context.c
@@ -141,7 +141,7 @@ panfrost_emit_sfbd(struct panfrost_context *ctx, unsigned
vertex_count)
struct mali_single_framebuffer framebuffer = {
.width = MALI_POSITIVE(width),
-.height = MALI_POSITIVE(width),
+.height = MALI_POSITIVE(height),
.unknown2 = 0x1f,
.format = 0x3000,
.clear_flags = 0x1000,
--
2.20.1
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH] panfrost: Place the height value in the height field
In the mali_single_framebuffer descriptor.
Signed-off-by: Tomeu Vizoso
---
src/gallium/drivers/panfrost/pan_context.c | 12
src/gallium/drivers/panfrost/pan_tiler.c | 12
src/gallium/drivers/panfrost/pan_tiler.h | 6 --
3 files changed, 20 insertions(+), 10 deletions(-)
diff --git a/src/gallium/drivers/panfrost/pan_context.c
b/src/gallium/drivers/panfrost/pan_context.c
index cb55dc66e799..9a378ccbfc03 100644
--- a/src/gallium/drivers/panfrost/pan_context.c
+++ b/src/gallium/drivers/panfrost/pan_context.c
@@ -102,7 +102,7 @@ panfrost_emit_midg_tiler(
unsigned total_size = header_size + body_size;
-if (t.hierarchy_mask) {
+if (t.hierarchy_mask != PAN_TILER_HIERARCHY_MASK_DISABLED) {
assert(ctx->tiler_polygon_list.bo->size >= total_size);
/* Specify allocated tiler structures */
@@ -113,6 +113,8 @@ panfrost_emit_midg_tiler(
t.heap_end =
ctx->tiler_heap.bo->gpu + ctx->tiler_heap.bo->size;
} else {
+assert(ctx->tiler_dummy.bo->size >= total_size);
+
/* The tiler is disabled, so don't allow the tiler heap */
t.heap_start = ctx->tiler_heap.bo->gpu;
t.heap_end = t.heap_start;
@@ -120,8 +122,10 @@ panfrost_emit_midg_tiler(
/* Use a dummy polygon list */
t.polygon_list = ctx->tiler_dummy.bo->gpu;
-/* Also, set a "tiler disabled?" flag? */
-t.hierarchy_mask |= 0x1000;
+/* We don't have a SET_VALUE job, so write the polygon list
manually */
+uint32_t *polygon_list_body = (uint32_t *)
+(ctx->tiler_dummy.bo->cpu + header_size);
+polygon_list_body[0] = 0xa000; /* TODO: Just that? */
}
t.polygon_list_body =
@@ -141,7 +145,7 @@ panfrost_emit_sfbd(struct panfrost_context *ctx, unsigned
vertex_count)
struct mali_single_framebuffer framebuffer = {
.width = MALI_POSITIVE(width),
-.height = MALI_POSITIVE(width),
+.height = MALI_POSITIVE(height),
.unknown2 = 0x1f,
.format = 0x3000,
.clear_flags = 0x1000,
diff --git a/src/gallium/drivers/panfrost/pan_tiler.c
b/src/gallium/drivers/panfrost/pan_tiler.c
index fc0de7d8842d..a1a1f8475ad7 100644
--- a/src/gallium/drivers/panfrost/pan_tiler.c
+++ b/src/gallium/drivers/panfrost/pan_tiler.c
@@ -229,12 +229,12 @@ panfrost_raw_header_size(unsigned width, unsigned height,
unsigned masked_count)
/* Given a hierarchy mask and a framebuffer size, compute the header size */
unsigned
-panfrost_tiler_header_size(unsigned width, unsigned height, uint8_t mask)
+panfrost_tiler_header_size(unsigned width, unsigned height, unsigned mask)
{
/* If no hierarchy levels are enabled, that means there is no geometry
* for the tiler to process, so use a minimum size. Used for clears */
-if (mask == 0x00)
+if (mask == PAN_TILER_HIERARCHY_MASK_DISABLED)
return MINIMUM_HEADER_SIZE;
/* Some levels are enabled. Ensure that only smaller levels are
@@ -262,9 +262,13 @@ panfrost_tiler_header_size(unsigned width, unsigned
height, uint8_t mask)
* out how to actually implement this. */
unsigned
-panfrost_tiler_body_size(unsigned width, unsigned height, uint8_t mask)
+panfrost_tiler_body_size(unsigned width, unsigned height, unsigned mask)
{
unsigned header_size = panfrost_tiler_header_size(width, height, mask);
+
+if (mask == PAN_TILER_HIERARCHY_MASK_DISABLED)
+return 0;
+
return ALIGN_POT(header_size * 512 / 8, 512);
}
@@ -283,7 +287,7 @@ panfrost_choose_hierarchy_mask(
/* If there is no geometry, we don't bother enabling anything */
if (!vertex_count)
-return 0x00;
+return PAN_TILER_HIERARCHY_MASK_DISABLED;
/* Otherwise, default everything on. TODO: Proper tests */
diff --git a/src/gallium/drivers/panfrost/pan_tiler.h
b/src/gallium/drivers/panfrost/pan_tiler.h
index 8d7f6f29de0b..153829dd299a 100644
--- a/src/gallium/drivers/panfrost/pan_tiler.h
+++ b/src/gallium/drivers/panfrost/pan_tiler.h
@@ -28,11 +28,13 @@
#ifndef __PAN_TILER_H__
#define __PAN_TILER_H__
+#define PAN_TILER_HIERARCHY_MASK_DISABLED 0xFFF
+
unsigned
-panfrost_tiler_header_size(unsigned width, unsigned height, uint8_t mask);
+panfrost_tiler_header_size(unsigned width, unsigned height, unsigned mask);
unsigned
-panfrost_tiler_body_size(unsigned width, unsigned height, uint8_t mask);
+panfrost_tiler_body_size(unsigned width, unsigned height, unsigned mask);
unsigned
panfrost_choose_hierarchy_mask(
--
2.20.1
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
[Mesa-dev] [PATCH] radv/gfx10: disable TC-compat HTILE for multisampled D32_SFLOAT format
For some reasons D32_SFLOAT is also affected on GFX10, it works fine with previous generations. This fixes some dEQP-VK.renderpass2.depth_stencil_resolve.*. Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_image.c | 7 +-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c index 6245873a4ed..368bd5d839d 100644 --- a/src/amd/vulkan/radv_image.c +++ b/src/amd/vulkan/radv_image.c @@ -83,9 +83,12 @@ radv_use_tc_compat_htile_for_image(struct radv_device *device, return false; /* FIXME: for some reason TC compat with 2/4/8 samples breaks some cts -* tests - disable for now */ +* tests - disable for now. On GFX10 D32_SFLOAT is affected as well. +*/ if (pCreateInfo->samples >= 2 && - pCreateInfo->format == VK_FORMAT_D32_SFLOAT_S8_UINT) + (pCreateInfo->format == VK_FORMAT_D32_SFLOAT_S8_UINT || +(pCreateInfo->format == VK_FORMAT_D32_SFLOAT && + device->physical_device->rad_info.chip_class == GFX10))) return false; /* GFX9 supports both 32-bit and 16-bit depth surfaces, while GFX8 only -- 2.22.0 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 5/9] radv/gfx10: implement support for GS as NGG
Reviewed-by: Bas Nieuwenhuizen
for the series.
On Thu, Jul 11, 2019 at 8:44 AM Samuel Pitoiset
wrote:
>
> Signed-off-by: Samuel Pitoiset
> ---
> src/amd/vulkan/radv_nir_to_llvm.c | 540 +-
> src/amd/vulkan/radv_pipeline.c| 5 +-
> src/amd/vulkan/radv_private.h | 24 ++
> src/amd/vulkan/radv_shader.c | 5 +
> 4 files changed, 568 insertions(+), 6 deletions(-)
>
> diff --git a/src/amd/vulkan/radv_nir_to_llvm.c
> b/src/amd/vulkan/radv_nir_to_llvm.c
> index 176e95537c1..dc37c937155 100644
> --- a/src/amd/vulkan/radv_nir_to_llvm.c
> +++ b/src/amd/vulkan/radv_nir_to_llvm.c
> @@ -105,7 +105,12 @@ struct radv_shader_context {
>
> bool is_gs_copy_shader;
> LLVMValueRef gs_next_vertex[4];
> + LLVMValueRef gs_curprim_verts[4];
> + LLVMValueRef gs_generated_prims[4];
> + LLVMValueRef gs_ngg_emit;
> + LLVMValueRef gs_ngg_scratch;
> unsigned gs_max_out_vertices;
> + unsigned gs_output_prim;
>
> unsigned tes_primitive_mode;
>
> @@ -116,6 +121,8 @@ struct radv_shader_context {
> uint32_t tcs_num_patches;
> uint32_t max_gsvs_emit_size;
> uint32_t gsvs_vertex_size;
> +
> + LLVMValueRef vertexptr; /* GFX10 only */
> };
>
> enum radeon_llvm_calling_convention {
> @@ -1846,6 +1853,10 @@ static LLVMValueRef load_sample_mask_in(struct
> ac_shader_abi *abi)
> }
>
>
> +static void gfx10_ngg_gs_emit_vertex(struct radv_shader_context *ctx,
> +unsigned stream,
> +LLVMValueRef *addrs);
> +
> static void
> visit_emit_vertex(struct ac_shader_abi *abi, unsigned stream, LLVMValueRef
> *addrs)
> {
> @@ -1854,6 +1865,11 @@ visit_emit_vertex(struct ac_shader_abi *abi, unsigned
> stream, LLVMValueRef *addr
> unsigned offset = 0;
> struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
>
> + if (ctx->options->key.vs_common_out.as_ngg) {
> + gfx10_ngg_gs_emit_vertex(ctx, stream, addrs);
> + return;
> + }
> +
> /* Write vertex attribute values to GSVS ring */
> gs_next_vertex = LLVMBuildLoad(ctx->ac.builder,
>ctx->gs_next_vertex[stream],
> @@ -1919,6 +1935,12 @@ static void
> visit_end_primitive(struct ac_shader_abi *abi, unsigned stream)
> {
> struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
> +
> + if (ctx->options->key.vs_common_out.as_ngg) {
> + LLVMBuildStore(ctx->ac.builder, ctx->ac.i32_0,
> ctx->gs_curprim_verts[stream]);
> + return;
> + }
> +
> ac_build_sendmsg(>ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS |
> (stream << 8), ctx->gs_wave_id);
> }
>
> @@ -2571,8 +2593,20 @@ radv_export_param(struct radv_shader_context *ctx,
> unsigned index,
> static LLVMValueRef
> radv_load_output(struct radv_shader_context *ctx, unsigned index, unsigned
> chan)
> {
> - LLVMValueRef output =
> - ctx->abi.outputs[ac_llvm_reg_index_soa(index, chan)];
> + LLVMValueRef output;
> +
> + if (ctx->vertexptr) {
> + LLVMValueRef gep_idx[3] = {
> + ctx->ac.i32_0, /* implicit C-style array */
> + ctx->ac.i32_0, /* second value of struct */
> + ctx->ac.i32_1, /* stream 1: source data index */
> + };
> +
> + gep_idx[2] = LLVMConstInt(ctx->ac.i32,
> ac_llvm_reg_index_soa(index, chan), false);
> + output = LLVMBuildGEP(ctx->ac.builder, ctx->vertexptr,
> gep_idx, 3, "");
> + } else {
> + output = ctx->abi.outputs[ac_llvm_reg_index_soa(index, chan)];
> + }
>
> return LLVMBuildLoad(ctx->ac.builder, output, "");
> }
> @@ -2940,7 +2974,7 @@ handle_vs_outputs_post(struct radv_shader_context *ctx,
> outputs[noutput].usage_mask =
>
> ctx->shader_info->info.tes.output_usage_mask[i];
> } else {
> - assert(ctx->is_gs_copy_shader);
> + assert(ctx->is_gs_copy_shader ||
> ctx->options->key.vs_common_out.as_ngg);
> outputs[noutput].usage_mask =
>
> ctx->shader_info->info.gs.output_usage_mask[i];
> }
> @@ -3090,6 +3124,20 @@ static LLVMValueRef get_wave_id_in_tg(struct
> radv_shader_context *ctx)
> return ac_unpack_param(>ac, ctx->merged_wave_info, 24, 4);
> }
>
> +static LLVMValueRef get_tgsize(struct radv_shader_context *ctx)
> +{
> + return ac_unpack_param(>ac, ctx->merged_wave_info, 28, 4);
> +}
> +
> +static LLVMValueRef get_thread_id_in_tg(struct radv_shader_context *ctx)
> +{
> + LLVMBuilderRef builder = ctx->ac.builder;
> + LLVMValueRef tmp;
> + tmp = LLVMBuildMul(builder, get_wave_id_in_tg(ctx),
> +
[Mesa-dev] [Bug 111104] aaki_bug1
https://bugs.freedesktop.org/show_bug.cgi?id=04 Bug ID: 04 Summary: aaki_bug1 Product: Mesa Version: unspecified Hardware: Other OS: Windows (All) Status: NEW Severity: normal Priority: medium Component: Other Assignee: mesa-dev@lists.freedesktop.org Reporter: poojabe...@mdbstech.com QA Contact: mesa-dev@lists.freedesktop.org first -- You are receiving this mail because: You are the assignee for the bug. You are the QA Contact for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] EGL_BAD_CONTEXT error when creating shared context
Hi， Is there a solution to this problem? Because the following problems have arisen now: [ERROR:gl_context_egl.cc(198)] eglCreateContext failed with error EGL_BAD_MATCH [ERROR:gles2_command_buffer_stub.cc(263)] ContextResult::kFatalFailure: Failed to create shared context for virtualization. Please reply. Thanks! ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 1/9] radv/gfx10: fix number of GS invocations for NGG
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_pipeline.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index f259f01bd75..2ea984c8328 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -1651,7 +1651,7 @@ calculate_ngg_info(const VkGraphicsPipelineCreateInfo
*pCreateInfo,
unsigned max_verts_per_prim = radv_get_num_input_vertices(pipeline);
unsigned min_verts_per_prim =
gs_type == MESA_SHADER_GEOMETRY ? max_verts_per_prim : 1;
- unsigned gs_num_invocations = 1;//MAX2(gs_info->gs.invocations, 1);
+ unsigned gs_num_invocations = radv_pipeline_has_gs(pipeline) ?
MAX2(gs_info->gs.invocations, 1) : 1;
bool uses_adjacency;
switch(pCreateInfo->pInputAssemblyState->topology) {
case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
--
2.22.0
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 8/9] radv/gfx10: Fix NGG GS output mask handlings for LDS indexing.
From: Bas Nieuwenhuizen
In emit_vertex we optimize storage if the output mask does not
have all bits set. Do the same in the epilogue so the indices
actually match up.
Fixes dEQP-VK.geometry.input.basic_primitive.points because it
outputs PSIZE with an output mask of 1, which cause the generic
attribute for the color to be loaded from the wrong indices.
Reviewed-by: Samuel Pitoiset
---
src/amd/vulkan/radv_nir_to_llvm.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/src/amd/vulkan/radv_nir_to_llvm.c
b/src/amd/vulkan/radv_nir_to_llvm.c
index b5469677d2b..11498bc27aa 100644
--- a/src/amd/vulkan/radv_nir_to_llvm.c
+++ b/src/amd/vulkan/radv_nir_to_llvm.c
@@ -3627,14 +3627,18 @@ static void gfx10_ngg_gs_emit_epilogue_2(struct
radv_shader_context *ctx)
outputs[noutput].slot_index = i ==
VARYING_SLOT_CLIP_DIST1;
outputs[noutput].usage_mask =
ctx->shader_info->info.gs.output_usage_mask[i];
+ int length = util_last_bit(outputs[noutput].usage_mask);
- for (unsigned j = 0; j < 4; j++, out_idx++) {
+ for (unsigned j = 0; j < length; j++, out_idx++) {
gep_idx[2] = LLVMConstInt(ctx->ac.i32, out_idx,
false);
tmp = LLVMBuildGEP(builder, vertexptr, gep_idx,
3, "");
tmp = LLVMBuildLoad(builder, tmp, "");
outputs[noutput].values[j] =
ac_to_float(>ac, tmp);
}
+ for (unsigned j = length; j < 4; j++)
+ outputs[noutput].values[j] =
LLVMGetUndef(ctx->ac.f32);
+
noutput++;
}
--
2.22.0
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 2/9] radv/gfx10: fix VGT_SHADER_STAGES_EN for GS as NGG
The driver shouldn't set the copy shader bit.
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_pipeline.c | 21 +++--
1 file changed, 11 insertions(+), 10 deletions(-)
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 2ea984c8328..bb434f81325 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -3865,22 +3865,23 @@ radv_compute_vgt_shader_stages_en(const struct
radv_pipeline *pipeline)
S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
if (radv_pipeline_has_gs(pipeline))
- stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
- S_028B54_GS_EN(1) |
- S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
- else if (radv_pipeline_has_ngg(pipeline))
stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
- S_028B54_PRIMGEN_EN(1);
+ S_028B54_GS_EN(1);
+ else if (radv_pipeline_has_ngg(pipeline))
+ stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS);
else
stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
-
} else if (radv_pipeline_has_gs(pipeline)) {
stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
- S_028B54_GS_EN(1) |
- S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
+ S_028B54_GS_EN(1);
} else if (radv_pipeline_has_ngg(pipeline)) {
- stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
- S_028B54_PRIMGEN_EN(1);
+ stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL);
+ }
+
+ if (radv_pipeline_has_ngg(pipeline)) {
+ stages |= S_028B54_PRIMGEN_EN(1);
+ } else {
+ stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
}
if (pipeline->device->physical_device->rad_info.chip_class >= GFX9)
--
2.22.0
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 9/9] radv/gfx10: enable geometry shaders
Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_device.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c index bfd72caa693..273078239c4 100644 --- a/src/amd/vulkan/radv_device.c +++ b/src/amd/vulkan/radv_device.c @@ -762,7 +762,7 @@ void radv_GetPhysicalDeviceFeatures( .fullDrawIndexUint32 = true, .imageCubeArray = true, .independentBlend = true, - .geometryShader = pdevice->rad_info.chip_class < GFX10, + .geometryShader = true, .tessellationShader = true, .sampleRateShading= true, .dualSrcBlend = true, -- 2.22.0 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 4/9] radv/gfx10: Use correct ES shader for es_vgpr_comp_cnt for GS.
From: Bas Nieuwenhuizen
Reviewed-by: Samuel Pitoiset
---
src/amd/vulkan/radv_shader.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
index 79418b401fb..1987d439612 100644
--- a/src/amd/vulkan/radv_shader.c
+++ b/src/amd/vulkan/radv_shader.c
@@ -796,11 +796,14 @@ static void radv_postprocess_config(const struct
radv_physical_device *pdevice,
if (pdevice->rad_info.chip_class >= GFX10 &&
(stage == MESA_SHADER_VERTEX || stage == MESA_SHADER_TESS_EVAL ||
stage == MESA_SHADER_GEOMETRY)) {
unsigned gs_vgpr_comp_cnt, es_vgpr_comp_cnt;
+ gl_shader_stage es_stage = stage;
+ if (stage == MESA_SHADER_GEOMETRY)
+ es_stage = info->gs.es_type;
/* VGPR5-8: (VertexID, UserVGPR0, UserVGPR1, UserVGPR2 /
InstanceID) */
- if (stage == MESA_SHADER_VERTEX) {
+ if (es_stage == MESA_SHADER_VERTEX) {
es_vgpr_comp_cnt = info->info.vs.needs_instance_id ? 3
: 0;
- } else if (stage == MESA_SHADER_TESS_EVAL) {
+ } else if (es_stage == MESA_SHADER_TESS_EVAL) {
bool enable_prim_id = info->tes.export_prim_id ||
info->info.uses_prim_id;
es_vgpr_comp_cnt = enable_prim_id ? 3 : 2;
}
--
2.22.0
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 7/9] radv/gfx10: Simplify output mask handling for NGG GS.
From: Bas Nieuwenhuizen
We only ever get in this function for a NGG GS proper.
Reviewed-by: Samuel Pitoiset
---
src/amd/vulkan/radv_nir_to_llvm.c | 13 +
1 file changed, 1 insertion(+), 12 deletions(-)
diff --git a/src/amd/vulkan/radv_nir_to_llvm.c
b/src/amd/vulkan/radv_nir_to_llvm.c
index 490b16a1f25..b5469677d2b 100644
--- a/src/amd/vulkan/radv_nir_to_llvm.c
+++ b/src/amd/vulkan/radv_nir_to_llvm.c
@@ -3626,18 +3626,7 @@ static void gfx10_ngg_gs_emit_epilogue_2(struct
radv_shader_context *ctx)
outputs[noutput].slot_name = i;
outputs[noutput].slot_index = i ==
VARYING_SLOT_CLIP_DIST1;
- if (ctx->stage == MESA_SHADER_VERTEX &&
- !ctx->is_gs_copy_shader) {
- outputs[noutput].usage_mask =
-
ctx->shader_info->info.vs.output_usage_mask[i];
- } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
- outputs[noutput].usage_mask =
-
ctx->shader_info->info.tes.output_usage_mask[i];
- } else {
- assert(ctx->is_gs_copy_shader ||
ctx->options->key.vs_common_out.as_ngg);
- outputs[noutput].usage_mask =
-
ctx->shader_info->info.gs.output_usage_mask[i];
- }
+ outputs[noutput].usage_mask =
ctx->shader_info->info.gs.output_usage_mask[i];
for (unsigned j = 0; j < 4; j++, out_idx++) {
gep_idx[2] = LLVMConstInt(ctx->ac.i32, out_idx,
false);
--
2.22.0
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 5/9] radv/gfx10: implement support for GS as NGG
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_nir_to_llvm.c | 540 +-
src/amd/vulkan/radv_pipeline.c| 5 +-
src/amd/vulkan/radv_private.h | 24 ++
src/amd/vulkan/radv_shader.c | 5 +
4 files changed, 568 insertions(+), 6 deletions(-)
diff --git a/src/amd/vulkan/radv_nir_to_llvm.c
b/src/amd/vulkan/radv_nir_to_llvm.c
index 176e95537c1..dc37c937155 100644
--- a/src/amd/vulkan/radv_nir_to_llvm.c
+++ b/src/amd/vulkan/radv_nir_to_llvm.c
@@ -105,7 +105,12 @@ struct radv_shader_context {
bool is_gs_copy_shader;
LLVMValueRef gs_next_vertex[4];
+ LLVMValueRef gs_curprim_verts[4];
+ LLVMValueRef gs_generated_prims[4];
+ LLVMValueRef gs_ngg_emit;
+ LLVMValueRef gs_ngg_scratch;
unsigned gs_max_out_vertices;
+ unsigned gs_output_prim;
unsigned tes_primitive_mode;
@@ -116,6 +121,8 @@ struct radv_shader_context {
uint32_t tcs_num_patches;
uint32_t max_gsvs_emit_size;
uint32_t gsvs_vertex_size;
+
+ LLVMValueRef vertexptr; /* GFX10 only */
};
enum radeon_llvm_calling_convention {
@@ -1846,6 +1853,10 @@ static LLVMValueRef load_sample_mask_in(struct
ac_shader_abi *abi)
}
+static void gfx10_ngg_gs_emit_vertex(struct radv_shader_context *ctx,
+unsigned stream,
+LLVMValueRef *addrs);
+
static void
visit_emit_vertex(struct ac_shader_abi *abi, unsigned stream, LLVMValueRef
*addrs)
{
@@ -1854,6 +1865,11 @@ visit_emit_vertex(struct ac_shader_abi *abi, unsigned
stream, LLVMValueRef *addr
unsigned offset = 0;
struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
+ if (ctx->options->key.vs_common_out.as_ngg) {
+ gfx10_ngg_gs_emit_vertex(ctx, stream, addrs);
+ return;
+ }
+
/* Write vertex attribute values to GSVS ring */
gs_next_vertex = LLVMBuildLoad(ctx->ac.builder,
ctx->gs_next_vertex[stream],
@@ -1919,6 +1935,12 @@ static void
visit_end_primitive(struct ac_shader_abi *abi, unsigned stream)
{
struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
+
+ if (ctx->options->key.vs_common_out.as_ngg) {
+ LLVMBuildStore(ctx->ac.builder, ctx->ac.i32_0,
ctx->gs_curprim_verts[stream]);
+ return;
+ }
+
ac_build_sendmsg(>ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS |
(stream << 8), ctx->gs_wave_id);
}
@@ -2571,8 +2593,20 @@ radv_export_param(struct radv_shader_context *ctx,
unsigned index,
static LLVMValueRef
radv_load_output(struct radv_shader_context *ctx, unsigned index, unsigned
chan)
{
- LLVMValueRef output =
- ctx->abi.outputs[ac_llvm_reg_index_soa(index, chan)];
+ LLVMValueRef output;
+
+ if (ctx->vertexptr) {
+ LLVMValueRef gep_idx[3] = {
+ ctx->ac.i32_0, /* implicit C-style array */
+ ctx->ac.i32_0, /* second value of struct */
+ ctx->ac.i32_1, /* stream 1: source data index */
+ };
+
+ gep_idx[2] = LLVMConstInt(ctx->ac.i32,
ac_llvm_reg_index_soa(index, chan), false);
+ output = LLVMBuildGEP(ctx->ac.builder, ctx->vertexptr, gep_idx,
3, "");
+ } else {
+ output = ctx->abi.outputs[ac_llvm_reg_index_soa(index, chan)];
+ }
return LLVMBuildLoad(ctx->ac.builder, output, "");
}
@@ -2940,7 +2974,7 @@ handle_vs_outputs_post(struct radv_shader_context *ctx,
outputs[noutput].usage_mask =
ctx->shader_info->info.tes.output_usage_mask[i];
} else {
- assert(ctx->is_gs_copy_shader);
+ assert(ctx->is_gs_copy_shader ||
ctx->options->key.vs_common_out.as_ngg);
outputs[noutput].usage_mask =
ctx->shader_info->info.gs.output_usage_mask[i];
}
@@ -3090,6 +3124,20 @@ static LLVMValueRef get_wave_id_in_tg(struct
radv_shader_context *ctx)
return ac_unpack_param(>ac, ctx->merged_wave_info, 24, 4);
}
+static LLVMValueRef get_tgsize(struct radv_shader_context *ctx)
+{
+ return ac_unpack_param(>ac, ctx->merged_wave_info, 28, 4);
+}
+
+static LLVMValueRef get_thread_id_in_tg(struct radv_shader_context *ctx)
+{
+ LLVMBuilderRef builder = ctx->ac.builder;
+ LLVMValueRef tmp;
+ tmp = LLVMBuildMul(builder, get_wave_id_in_tg(ctx),
+ LLVMConstInt(ctx->ac.i32, 64, false), "");
+ return LLVMBuildAdd(builder, tmp, ac_get_thread_id(>ac), "");
+}
+
static LLVMValueRef ngg_get_vtx_cnt(struct radv_shader_context *ctx)
{
return ac_build_bfe(>ac, ctx->gs_tg_info,
@@ -3106,6 +3154,85 @@ static LLVMValueRef ngg_get_prim_cnt(struct
radv_shader_context *ctx)
[Mesa-dev] [PATCH 3/9] radv/gfx10: Do not allocate a gs_copy_shader on gfx10.
From: Bas Nieuwenhuizen
Will use ngg for any gs anyway.
Reviewed-by: Samuel Pitoiset
---
src/amd/vulkan/radv_cmd_buffer.c | 5 +++--
src/amd/vulkan/radv_pipeline.c | 5 +++--
2 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index b7ee0ff6422..91b9f9196b9 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -929,7 +929,8 @@ radv_emit_prefetch_L2(struct radv_cmd_buffer *cmd_buffer,
if (mask & RADV_PREFETCH_GS) {
radv_emit_shader_prefetch(cmd_buffer,
pipeline->shaders[MESA_SHADER_GEOMETRY]);
- radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);
+ if (pipeline->gs_copy_shader)
+ radv_emit_shader_prefetch(cmd_buffer,
pipeline->gs_copy_shader);
}
if (mask & RADV_PREFETCH_PS)
@@ -1123,7 +1124,7 @@ radv_emit_graphics_pipeline(struct radv_cmd_buffer
*cmd_buffer)
pipeline->shaders[i]->bo);
}
- if (radv_pipeline_has_gs(pipeline))
+ if (radv_pipeline_has_gs(pipeline) && pipeline->gs_copy_shader)
radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
pipeline->gs_copy_shader->bo);
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index bb434f81325..8417eab41db 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -2392,6 +2392,7 @@ void radv_create_shaders(struct radv_pipeline *pipeline,
struct radv_shader_binary *binaries[MESA_SHADER_STAGES] = {NULL};
struct radv_shader_variant_key keys[MESA_SHADER_STAGES] = {0};
unsigned char hash[20], gs_copy_hash[20];
+ bool use_ngg = device->physical_device->rad_info.chip_class >= GFX10;
radv_start_feedback(pipeline_feedback);
@@ -2412,7 +2413,7 @@ void radv_create_shaders(struct radv_pipeline *pipeline,
gs_copy_hash[0] ^= 1;
bool found_in_application_cache = true;
- if (modules[MESA_SHADER_GEOMETRY]) {
+ if (modules[MESA_SHADER_GEOMETRY] && !use_ngg) {
struct radv_shader_variant *variants[MESA_SHADER_STAGES] = {0};
radv_create_shader_variants_from_pipeline_cache(device, cache,
gs_copy_hash, variants,
_in_application_cache);
@@ -2563,7 +2564,7 @@ void radv_create_shaders(struct radv_pipeline *pipeline,
}
}
- if(modules[MESA_SHADER_GEOMETRY]) {
+ if(modules[MESA_SHADER_GEOMETRY] && !use_ngg) {
struct radv_shader_binary *gs_copy_binary = NULL;
if (!pipeline->gs_copy_shader) {
pipeline->gs_copy_shader = radv_create_gs_copy_shader(
--
2.22.0
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 6/9] radv/gfx10: Do GS prologue outside of gs_threads if.
From: Bas Nieuwenhuizen
Mirror radeonsi.
Reviewed-by: Samuel Pitoiset
---
src/amd/vulkan/radv_nir_to_llvm.c | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/src/amd/vulkan/radv_nir_to_llvm.c
b/src/amd/vulkan/radv_nir_to_llvm.c
index dc37c937155..490b16a1f25 100644
--- a/src/amd/vulkan/radv_nir_to_llvm.c
+++ b/src/amd/vulkan/radv_nir_to_llvm.c
@@ -4372,6 +4372,12 @@ LLVMModuleRef ac_translate_nir_to_llvm(struct
ac_llvm_compiler *ac_llvm,
LLVMBasicBlockRef merge_block;
if (shader_count >= 2 || is_ngg) {
+
+ if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY &&
+ ctx.options->key.vs_common_out.as_ngg) {
+ gfx10_ngg_gs_emit_prologue();
+ }
+
LLVMValueRef fn =
LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
LLVMBasicBlockRef then_block =
LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
merge_block =
LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
@@ -4383,11 +4389,6 @@ LLVMModuleRef ac_translate_nir_to_llvm(struct
ac_llvm_compiler *ac_llvm,
LLVMBuildCondBr(ctx.ac.builder, cond, then_block,
merge_block);
LLVMPositionBuilderAtEnd(ctx.ac.builder, then_block);
-
- if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY &&
- ctx.options->key.vs_common_out.as_ngg) {
- gfx10_ngg_gs_emit_prologue();
- }
}
if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT)
--
2.22.0
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev
