On 14.02.2018 09:54, Tapani Pälli wrote:
On 14.02.2018 09:38, Rogovin, Kevin wrote:
Hi,
The 3rd patch, "i965: use ASTC5x5 workaround in
intel_miptree_texture_aux_usage has issues:
1. Definitely: brw_draw lacks the call to
gen9_astc5x5_perform_wa() which generates the needed flush be
On 14.02.2018 09:38, Rogovin, Kevin wrote:
Hi,
The 3rd patch, "i965: use ASTC5x5 workaround in
intel_miptree_texture_aux_usage has issues:
1. Definitely: brw_draw lacks the call to gen9_astc5x5_perform_wa() which generates the needed flush between batchbuffers
Now it happens via i
Reviewed by: kevin.rogovin [at] intel.com
-Original Message-
From: Phillips, Scott D
Sent: Friday, February 9, 2018 3:11 AM
To: mesa-dev@lists.freedesktop.org; Rogovin, Kevin
Subject: [PATCH v3] intel/tools: new intel_sanitize_gpu tool
From: Kevin Rogovin
Adds a new debug tool to pad
Hi,
The 3rd patch, "i965: use ASTC5x5 workaround in
intel_miptree_texture_aux_usage has issues:
1. Definitely: brw_draw lacks the call to gen9_astc5x5_perform_wa() which
generates the needed flush between batchbuffers
2. Uneasy: I am nervous about hitting intel_miptree_texture_aux_us
On Tuesday, January 9, 2018 11:16:58 PM PST Scott D Phillips wrote:
> In all current uses, the linear surface is only allocated starting
> at (xt1, yt1) anyway, so this improves the calling ergonomics.
> ---
> src/mesa/drivers/dri/i965/intel_pixel_read.c | 2 +-
> src/mesa/drivers/dri/i965/inte
From: Dave Airlie
A bunch of CTS tests led me to write
tests/shaders/ssa/fs-while-loop-rotate-value.shader_test
which r600/sb always fell over on.
This patch fixes it, but I'll probably never be 100% sure why.
Anyways what appears to be happening is when gcm is scheduling
the copy_movs used for
On Monday, February 12, 2018 7:35:04 PM PST Jason Ekstrand wrote:
> ---
> src/intel/tools/gen_batch_decoder.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/src/intel/tools/gen_batch_decoder.c
> b/src/intel/tools/gen_batch_decoder.c
> index 78db83b..1a8794c 100644
> ---
On Monday, February 12, 2018 7:35:05 PM PST Jason Ekstrand wrote:
> ---
> src/intel/vulkan/genX_pipeline.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/src/intel/vulkan/genX_pipeline.c
> b/src/intel/vulkan/genX_pipeline.c
> index 45ebe31..4aee9ec 100644
> --- a/src/in
On Tuesday, February 13, 2018 2:57:07 PM PST Jason Ekstrand wrote:
> This fixes the build in clang
> ---
> src/mesa/drivers/dri/i965/brw_nir_uniforms.cpp | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_nir_uniforms.cpp
> b/src/mesa/drivers
On Tuesday, February 13, 2018 10:00:44 PM PST Timothy Arceri wrote:
> On 14/02/18 16:24, Jason Ekstrand wrote:
> > First off, you should add an index to the intrinsic if you're going to
> > do this and it should probably be set elsewhere. Otherwise, it becomes
> > this magic secret radeonsi thin
Fixes glsl-1.30/execution/isinf-and-isnan* piglit tests for
radeonsi and should fix SPIRV errors when LLVM optimises away
the workarounds in vtn_handle_alu() for handling ordered
comparisons.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104905
---
src/amd/common/ac_nir_to_llvm.c | 8 +++
This will enable the nir->llvm translation to work correctly.
---
src/compiler/nir/nir_opcodes.py | 4
1 file changed, 4 insertions(+)
diff --git a/src/compiler/nir/nir_opcodes.py b/src/compiler/nir/nir_opcodes.py
index 278562b2bd..61c004c6f8 100644
--- a/src/compiler/nir/nir_opcodes.py
+++
---
src/intel/compiler/brw_fs_nir.cpp | 10 +-
src/intel/compiler/brw_vec4_nir.cpp | 4
2 files changed, 13 insertions(+), 1 deletion(-)
diff --git a/src/intel/compiler/brw_fs_nir.cpp
b/src/intel/compiler/brw_fs_nir.cpp
index 0d77564930..cf3df75cd5 100644
--- a/src/intel/compiler
---
src/amd/common/ac_nir_to_llvm.c | 12
1 file changed, 12 insertions(+)
diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 8d1eed241f..a0c5680205 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -1803,6 +1803,1
---
src/compiler/spirv/vtn_alu.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/src/compiler/spirv/vtn_alu.c b/src/compiler/spirv/vtn_alu.c
index d0c9e31693..fd36c6537b 100644
--- a/src/compiler/spirv/vtn_alu.c
+++ b/src/compiler/spirv/vtn_alu.c
@@ -326,26 +326,26
On 14/02/18 16:24, Jason Ekstrand wrote:
First off, you should add an index to the intrinsic if you're going to
do this and it should probably be set elsewhere. Otherwise, it becomes
this magic secret radeonsi thing.
Ah yes that's how it's done, I thought there was a better way to do this
th
Reviewed-by: Tapani Pälli
On 14.02.2018 00:57, Jason Ekstrand wrote:
This fixes the build in clang
---
src/mesa/drivers/dri/i965/brw_nir_uniforms.cpp | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_nir_uniforms.cpp
b/src/mesa/drivers/dri/i
First off, you should add an index to the intrinsic if you're going to do
this and it should probably be set elsewhere. Otherwise, it becomes this
magic secret radeonsi thing.
Second, do you really want this on the intrinsic or would it be better as
part of shader_info? It's always been weird to
https://bugs.freedesktop.org/show_bug.cgi?id=104915
Tapani Pälli changed:
What|Removed |Added
Resolution|--- |FIXED
Status|NEW
---
src/gallium/drivers/radeonsi/si_shader_nir.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/src/gallium/drivers/radeonsi/si_shader_nir.c
b/src/gallium/drivers/radeonsi/si_shader_nir.c
index b46c7dca86..cb4f8e9255 100644
--- a/src/gallium/drivers/radeonsi/si_shader_nir.c
+++ b/src/g
radeonsi needs to gather this information.
---
src/compiler/nir/nir_lower_system_values.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/src/compiler/nir/nir_lower_system_values.c
b/src/compiler/nir/nir_lower_system_values.c
index 3594f4ae5c..f8d8463f7f 100644
--- a/src/compiler/nir
From: Dave Airlie
The gallium query types changed, so we need to remap from the
gallium ones to the virgl ones.
Fixes:
dEQP-GLES3.functional.transform_feedback.basic_types*
Fixes: 3f6b3d9db (gallium: add PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE)
Signed-off-by: Dave Airlie
---
src/gallium/
On Tue, Feb 13, 2018 at 5:34 PM, Nanley Chery wrote:
> On Mon, Feb 05, 2018 at 02:35:02PM -0800, Jason Ekstrand wrote:
> > ---
> > src/intel/vulkan/genX_cmd_buffer.c | 190 +-
> ---
> > 1 file changed, 68 insertions(+), 122 deletions(-)
> >
> > diff --git a/src/in
You're going to want to re-review this one when I send the v2. It changed
quite a bit.
On Tue, Feb 13, 2018 at 2:44 PM, Jason Ekstrand
wrote:
> On Tue, Feb 13, 2018 at 11:02 AM, Nanley Chery
> wrote:
>
>> On Mon, Feb 05, 2018 at 02:34:56PM -0800, Jason Ekstrand wrote:
>> > This moves the decis
On Tuesday, February 13, 2018 11:15:05 AM PST Anuj Phogat wrote:
> Signed-off-by: Anuj Phogat
> ---
> src/intel/Android.isl.mk | 20
> src/intel/Makefile.isl.am | 4
> src/intel/Makefile.sources | 4
> src/intel/isl/isl.c| 3 +++
> src/intel/isl/isl_pr
On Tuesday, February 13, 2018 11:15:03 AM PST Anuj Phogat wrote:
> Signed-off-by: Anuj Phogat
> ---
> src/intel/genxml/gen_bits_header.py | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/src/intel/genxml/gen_bits_header.py
> b/src/intel/genxml/gen_bits_header.py
> index 1b3504073b..965a
On Tuesday, February 13, 2018 11:15:08 AM PST Anuj Phogat wrote:
> Signed-off-by: Anuj Phogat
Reviewed-by: Kenneth Graunke
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mesa-dev mailing list
mesa-dev@lists.freedesktop.org
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On Tuesday, February 13, 2018 11:15:07 AM PST Anuj Phogat wrote:
> This field is removed in gen11+
>
> Signed-off-by: Anuj Phogat
> ---
> src/mesa/drivers/dri/i965/genX_state_upload.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/src/mesa/drivers/dri/i965/genX_state_upload.c
> b/s
On Tuesday, February 13, 2018 11:15:10 AM PST Anuj Phogat wrote:
> Gen11 MOCS settings are duplicate of Gen10 MOCS settings.
>
> Signed-off-by: Anuj Phogat
> ---
> src/mesa/drivers/dri/i965/brw_state.h| 6 ++
> src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 2 ++
> src/mesa/d
On Tuesday, February 13, 2018 11:15:11 AM PST Anuj Phogat wrote:
> Nothing is changed here from gen10 to gen11. So, just update
> the assert.
>
> Signed-off-by: Anuj Phogat
> ---
> src/mesa/drivers/dri/i965/brw_program.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/s
On Tuesday, February 13, 2018 11:15:02 AM PST Anuj Phogat wrote:
> Signed-off-by: Anuj Phogat
> ---
> src/intel/Android.genxml.mk | 5 +
> src/intel/Makefile.sources| 3 ++-
> src/intel/genxml/genX_pack.h | 2 ++
> src/intel/genxml/gen_macros.h | 3 +++
> 4 files changed, 12 insertions
On Mon, Feb 05, 2018 at 02:35:02PM -0800, Jason Ekstrand wrote:
> ---
> src/intel/vulkan/genX_cmd_buffer.c | 190
> +
> 1 file changed, 68 insertions(+), 122 deletions(-)
>
> diff --git a/src/intel/vulkan/genX_cmd_buffer.c
> b/src/intel/vulkan/genX_cmd_buffer
We were incorrectly using the input info for outputs.
---
src/gallium/drivers/radeonsi/si_shader.c | 13 +++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_shader.c
b/src/gallium/drivers/radeonsi/si_shader.c
index 825cb9dd0e..ec03f537d0 10
On Tue, Feb 13, 2018 at 4:47 PM, Nanley Chery wrote:
> On Mon, Feb 05, 2018 at 02:35:01PM -0800, Jason Ekstrand wrote:
> > ---
> > src/intel/vulkan/genX_cmd_buffer.c | 50 ++
>
> > 1 file changed, 29 insertions(+), 21 deletions(-)
> >
> > diff --git a/src/int
On Tue, Feb 13, 2018 at 4:35 PM, Nanley Chery wrote:
> On Mon, Feb 05, 2018 at 02:35:00PM -0800, Jason Ekstrand wrote:
> > This is quite a bit cleaner because we now sync the clear values at the
> > same time as we do the fast clear. For loading the clear values into
> > the surface state, we no
Build mesa 6908 completed
Commit f6718baabc by Roland Scheidegger on 2/13/2018 5:56 PM:
tgsi: Recognize RET in main for tgsi_transform\n\nShaders coming from dx10 state trackers have a RET before the END.\nAnd the epilog needs to be placed before the RET (other
On Mon, Feb 05, 2018 at 02:35:01PM -0800, Jason Ekstrand wrote:
> ---
> src/intel/vulkan/genX_cmd_buffer.c | 50
> ++
> 1 file changed, 29 insertions(+), 21 deletions(-)
>
> diff --git a/src/intel/vulkan/genX_cmd_buffer.c
> b/src/intel/vulkan/genX_cmd_buffer.
Build mesa 6907 failed
Commit 7461bd5b8f by Bas Nieuwenhuizen on 2/13/2018 10:25 PM:
ac: Use the renumbered const address space for LLVM 7.\n\nThe LLVM AMDGPU backend decided to renumber the constant address\nspace \n\nReviewed-by: Samuel Pitoiset
On Mon, Feb 05, 2018 at 02:35:00PM -0800, Jason Ekstrand wrote:
> This is quite a bit cleaner because we now sync the clear values at the
> same time as we do the fast clear. For loading the clear values into
> the surface state, we now do it once when we handle the LOAD_OP_LOAD
> instead of every
This adds support for the VK_GOOGLE_display timing extension, which
provides two things:
1) Detailed information about when frames are displayed, including
slack time between GPU execution and display frame.
2) Absolute time control over swapchain queue processing. This allows
the appli
This adds support for the KHR_display extension support to the vulkan
WSI layer. Driver support will be added separately.
Signed-off-by: Keith Packard
---
configure.ac|1 +
meson.build |4 +-
src/amd/vulkan/radv_wsi.c |3 +-
s
This extension is required to support EXT_display_control as it offers
a way to query whether the vblank counter is supported.
v2: Thanks to kisak
Fix spelling of VkSurfaceCapabilities2EXT in wsi_common_wayland.c,
it was using ext instead of EXT.
Fix spelling of VK_STRUCTURE_TYPE_SUR
This extension adds a single function to query the current GPU
timestamp, just like glGetInteger64v(GL_TIMESTAMP, ×tamp). This
function is needed to complete the implementation of
GOOGLE_display_timing, which needs to be able to coorelate GPU and CPU
timestamps.
Signed-off-by: Keith Packard
---
This adds support for the VK_GOOGLE_display timing extension.
Signed-off-by: Keith Packard
---
src/intel/vulkan/anv_extensions.py | 1 +
src/intel/vulkan/anv_wsi.c | 29 +
2 files changed, 30 insertions(+)
diff --git a/src/intel/vulkan/anv_extensions.py
b/s
This extension is required to support EXT_display_control as it offers
a way to query whether the vblank counter is supported.
Signed-off-by: Keith Packard
---
src/amd/vulkan/radv_extensions.py | 1 +
src/amd/vulkan/radv_wsi.c | 12
2 files changed, 13 insertions(+)
diff -
This adds support for the VK_GOOGLE_display timing extension.
Signed-off-by: Keith Packard
---
src/amd/vulkan/radv_extensions.py | 1 +
src/amd/vulkan/radv_wsi.c | 32
2 files changed, 33 insertions(+)
diff --git a/src/amd/vulkan/radv_extensions.py
b/s
This extension adds the ability to borrow an X RandR output for
temporary use directly by a Vulkan application to the radv driver.
Signed-off-by: Keith Packard
---
src/amd/vulkan/Makefile.am| 7 +++
src/amd/vulkan/meson.build| 7 +++
src/amd/vulkan/radv_extensions.py |
This extension provides fences and frame count information to direct
display contexts. It uses new kernel ioctls to provide 64-bits of
vblank sequence and nanosecond resolution.
v2: Remove DRM_CRTC_SEQUENCE_FIRST_PIXEL_OUT flag. This has
been removed from the proposed kernel API.
Add NULL
Add support for the EXT_direct_mode_display extension. This just
provides the vkReleaseDisplayEXT function.
Signed-off-by: Keith Packard
---
src/amd/vulkan/radv_extensions.py | 1 +
src/amd/vulkan/radv_wsi_display.c | 11 +++
2 files changed, 12 insertions(+)
diff --git a/src/amd/vulka
This extension adds a single function to query the current GPU
timestamp, just like glGetInteger64v(GL_TIMESTAMP, ×tamp). This
function is needed to complete the implementation of
GOOGLE_display_timing, which needs to be able to coorelate GPU and CPU
timestamps.
Signed-off-by: Keith Packard
---
This extension provides fences and frame count information to direct
display contexts. It uses new kernel ioctls to provide 64-bits of
vblank sequence and nanosecond resolution.
Signed-off-by: Keith Packard
---
src/amd/vulkan/radv_extensions.py | 1 +
src/amd/vulkan/radv_private.h | 11 ++
This extension adds the ability to borrow an X RandR output for
temporary use directly by a Vulkan application. For DRM, we use the
Linux resource leasing mechanism.
Signed-off-by: Keith Packard
---
configure.ac| 32 +++
meson.build | 17 ++
meso
This extension is required to support EXT_display_control as it offers
a way to query whether the vblank counter is supported.
v4: Add anv support
Signed-off-by: Keith Packard
---
src/intel/vulkan/anv_extensions.py | 1 +
src/intel/vulkan/anv_wsi.c | 12
2 files changed, 1
This extension adds a single function to query the current GPU
timestamp, just like glGetInteger64v(GL_TIMESTAMP, ×tamp). This
function is needed to complete the implementation of
GOOGLE_display_timing, which needs to be able to coorelate GPU and CPU
timestamps.
Signed-off-by: Keith Packard
---
Add support for the EXT_direct_mode_display extension. This just
provides the vkReleaseDisplayEXT function.
Signed-off-by: Keith Packard
---
src/vulkan/wsi/wsi_common_display.c | 17 +
src/vulkan/wsi/wsi_common_display.h | 5 +
2 files changed, 22 insertions(+)
diff --git a
Add support for the EXT_direct_mode_display extension. This just
provides the vkReleaseDisplayEXT function.
Signed-off-by: Keith Packard
---
src/intel/vulkan/anv_extensions.py | 1 +
src/intel/vulkan/anv_wsi_display.c | 11 +++
2 files changed, 12 insertions(+)
diff --git a/src/intel/v
This extension provides fences and frame count information to direct
display contexts. It uses new kernel ioctls to provide 64-bits of
vblank sequence and nanosecond resolution.
Signed-off-by: Keith Packard
---
src/intel/vulkan/anv_extensions.py | 1 +
src/intel/vulkan/anv_private.h | 4
Dave Airlie asked me to split these up so that the core and anv/radv
bits were all in separate patches.
There are no code changes here aside from fixing the KHR_display
version from 1 to 23. I also fixed the indentation in the changes to
the radv driver from spaces to tabs as per convention.
-kei
This adds support for the KHR_display extension to the anv Vulkan
driver. The driver now attempts to open the master DRM node when the
KHR_display extension is requested so that the common winsys code can
perform the necessary operations.
Signed-off-by: Keith Packard
---
src/intel/Makefile.sourc
This adds support for the KHR_display extension to the radv Vulkan
driver. The driver now attempts to open the master DRM node when the
KHR_display extension is requested so that the common winsys code can
perform the necessary operations.
Signed-off-by: Keith Packard
---
src/amd/vulkan/Makefile
This extension adds the ability to borrow an X RandR output for
temporary use directly by a Vulkan application to the anv driver.
Signed-off-by: Keith Packard
---
src/intel/Makefile.vulkan.am | 7 +++
src/intel/vulkan/anv_extensions.py | 1 +
src/intel/vulkan/anv_extensions_g
On Mon, Feb 05, 2018 at 02:34:58PM -0800, Jason Ekstrand wrote:
> These are the same as pending clear aspects only for the "load"
> operation.
> ---
> src/intel/vulkan/anv_private.h | 1 +
> src/intel/vulkan/genX_cmd_buffer.c | 22 --
> 2 files changed, 17 insertions(+), 6
On Tuesday, February 13, 2018 11:15:14 AM PST Anuj Phogat wrote:
> On gen11+ AUX_HIZ is not a supported value for surfaces being
> sampled by the 3D sampler.
>
> Signed-off-by: Anuj Phogat
> ---
> src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 5 +++--
> 1 file changed, 3 insertions(+), 2 delet
On Mon, Feb 05, 2018 at 02:34:59PM -0800, Jason Ekstrand wrote:
> This requires us to ditch the VkAttachmentReference struct in favor of
> an anv-specific struct. However, we can now easily identify from just
> the subpass attachment what kind of an attachment it is. This will make
> iteration ov
On Tue, Feb 13, 2018 at 03:23:42PM -0800, Jason Ekstrand wrote:
> On Tue, Feb 13, 2018 at 3:18 PM, Nanley Chery wrote:
>
> > On Mon, Feb 05, 2018 at 02:34:59PM -0800, Jason Ekstrand wrote:
> > > This requires us to ditch the VkAttachmentReference struct in favor of
> > > an anv-specific struct.
On Tuesday, February 13, 2018 11:15:16 AM PST Anuj Phogat wrote:
> From PIPE_CONTROL command description in gfxspecs:
>
> "Whenever a Binding Table Index (BTI) used by a Render Taget Message
> points to a different RENDER_SURFACE_STATE, SW must issue a Render
> Target Cache Flush by enabling thi
On Tuesday, February 13, 2018 11:15:15 AM PST Anuj Phogat wrote:
> Signed-off-by: Anuj Phogat
> ---
> src/mesa/drivers/dri/i965/brw_state_upload.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c
> b/src/mesa/drivers/dri/i965/
On Tuesday, February 13, 2018 11:15:12 AM PST Anuj Phogat wrote:
> Signed-off-by: Anuj Phogat
> ---
> src/mesa/drivers/dri/i965/brw_formatquery.c | 1 +
> src/mesa/drivers/dri/i965/intel_screen.c| 1 +
> 2 files changed, 2 insertions(+)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_formatqu
On Tuesday, February 13, 2018 11:15:13 AM PST Anuj Phogat wrote:
> SIMD4x2 dispatch mode has been removed in GEN11. We're not using
> it anyways in Mesa. Adding few asserts to make it explicit.
>
> Signed-off-by: Anuj Phogat
> ---
> src/intel/blorp/blorp_genX_exec.h | 4
> src/m
On Tuesday, February 13, 2018 11:15:09 AM PST Anuj Phogat wrote:
> Signed-off-by: Anuj Phogat
> ---
> src/intel/blorp/blorp_genX_exec.h | 9 +
> src/mesa/drivers/dri/i965/genX_state_upload.c | 9 +
> 2 files changed, 10 insertions(+), 8 deletions(-)
Reviewed-by: Kenne
On Tue, Feb 13, 2018 at 3:18 PM, Nanley Chery wrote:
> On Mon, Feb 05, 2018 at 02:34:59PM -0800, Jason Ekstrand wrote:
> > This requires us to ditch the VkAttachmentReference struct in favor of
> > an anv-specific struct. However, we can now easily identify from just
> > the subpass attachment w
Reviewed-by: Samuel Pitoiset
On 02/13/2018 11:41 PM, Bas Nieuwenhuizen wrote:
The LLVM AMDGPU backend decided to renumber the constant address
space
---
src/amd/common/ac_llvm_build.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/amd/common/ac_llvm_build.h b/
On Mon, Feb 05, 2018 at 02:34:59PM -0800, Jason Ekstrand wrote:
> This requires us to ditch the VkAttachmentReference struct in favor of
> an anv-specific struct. However, we can now easily identify from just
> the subpass attachment what kind of an attachment it is. This will make
> iteration ov
On Tuesday, February 13, 2018 11:15:06 AM PST Anuj Phogat wrote:
> StateCacheInvalidation is required on all gen7+ platforms. We
> don't need to update this check for every new gen h/w unless
> this requirement is changed. So, dropping the check for latest
> gen h/w.
>
> Signed-off-by: Anuj Phogat
On Tuesday, February 13, 2018 11:15:04 AM PST Anuj Phogat wrote:
> Signed-off-by: Anuj Phogat
> ---
> src/intel/isl/isl.c | 6 +-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
> index 59f512fc05..c9873d96df 100644
> --- a/src/inte
On Tuesday, February 13, 2018 1:51:54 PM PST Rafael Antognolli wrote:
> Gen10 seems pretty stable so far, remove "alpha support" message.
>
> Signed-off-by: Rafael Antognolli
> Cc: Jason Ekstrand
> Cc: "18.0" mesa-sta...@lists.freedesktop.org
> ---
> src/intel/vulkan/anv_device.c | 8 +++-
>
On Tue, Feb 13, 2018 at 11:29 AM, Nanley Chery
wrote:
> On Mon, Feb 05, 2018 at 02:34:57PM -0800, Jason Ekstrand wrote:
> > This unifies things a bit because we now handle depth and stencil at the
> > same time. It also ensures that clears happen for input attachments.
>
> As we discussed in ano
> On Feb 13, 2018, at 4:54 PM, Dylan Baker wrote:
>
> Quoting Andres Gomez (2018-02-13 14:42:57)
> [snip]
>>
>> -if with_amd_vk or with_gallium_radeonsi
>> +if with_amd_vk or with_gallium_radeonsi or with_gallium_swr
>> _llvm_version = '>= 4.0.0'
>> -elif with_gallium_opencl or with_gallium_s
This fixes the build in clang
---
src/mesa/drivers/dri/i965/brw_nir_uniforms.cpp | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_nir_uniforms.cpp
b/src/mesa/drivers/dri/i965/brw_nir_uniforms.cpp
index 10a4ff4..69da83a 100644
--- a/src/mesa/drive
I am not an expert on all the changes needed for travis and packaging, but the
swr changes look good.
Reviewed-by: George Kyriazis
mailto:george.kyria...@intel.com>>
On Feb 13, 2018, at 4:42 PM, Andres Gomez
mailto:ago...@igalia.com>> wrote:
Since radv and radeonsi removed support for LLVM 3.
Quoting Andres Gomez (2018-02-13 14:42:57)
[snip]
>
> -if with_amd_vk or with_gallium_radeonsi
> +if with_amd_vk or with_gallium_radeonsi or with_gallium_swr
>_llvm_version = '>= 4.0.0'
> -elif with_gallium_opencl or with_gallium_swr or with_gallium_r600
> +elif with_gallium_opencl or with_ga
On Tue, 2018-02-06 at 19:23 +, Kyriazis, George wrote:
> SWR is OK with moving to LLVM 4.0 and above.
>
> Just to clarify: This goes to master, which means mesa 18.0 is not
> affected, just 18.1 and later. Correct?
That is my understanding.
3bf1e036e8a, which is the one triggering this chan
Sent this patch to ML by mistake :(. Reviewers can ignore this one for now.
Matt can send it out later with rest of his compiler changes.
On Tue, Feb 13, 2018 at 2:41 PM, Anuj Phogat wrote:
> From: Matt Turner
>
> ---
> src/intel/compiler/test_eu_validate.cpp | 1 +
> 1 file changed, 1 insertio
Performance optimization, and fixes some clipping issues.
---
src/gallium/drivers/swr/rasterizer/core/clip.h | 4
1 file changed, 4 insertions(+)
diff --git a/src/gallium/drivers/swr/rasterizer/core/clip.h
b/src/gallium/drivers/swr/rasterizer/core/clip.h
index 1d336b6..5193672 100644
--- a/
Convert portions of the C sampler to the rasty SIMD lib.
---
src/gallium/drivers/swr/rasterizer/common/intrin.h | 3 +++
.../drivers/swr/rasterizer/common/simdlib_128_avx.inl| 16
2 files changed, 19 insertions(+)
diff --git a/src/gallium/drivers/swr/rasterizer/common/
fix gcc8 compiler error for KNL.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105029
---
src/gallium/drivers/swr/rasterizer/common/simdlib_512_avx512.inl | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/gallium/drivers/swr/rasterizer/common/simdlib_512_avx512.inl
On Tue, Feb 13, 2018 at 11:02 AM, Nanley Chery
wrote:
> On Mon, Feb 05, 2018 at 02:34:56PM -0800, Jason Ekstrand wrote:
> > This moves the decision out of begin_subpass and into BeginRenderPass
> > like the decision for color clears. We use a similar name for the
> > function for depth/stencil a
Since radv and radeonsi removed support for LLVM 3.9 the distcheck
target got broken because SWR distribution needed 3.9.x.
After checking with George Kyriazis, SWR is OK with moving to LLVM 4.0
and above, which will solve this problem.
Fixes: 3bf1e036e8a ("amd: remove support for LLVM 3.9")
Cc:
---
src/gallium/drivers/swr/rasterizer/jitter/builder_mem.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/gallium/drivers/swr/rasterizer/jitter/builder_mem.h
b/src/gallium/drivers/swr/rasterizer/jitter/builder_mem.h
index 14dc22d..f31cb4a 100644
--- a/src/gallium/drivers
Added support for another full translation path in fetch jitter.
---
src/gallium/drivers/swr/rasterizer/jitter/builder_mem.h | 1 +
src/gallium/drivers/swr/rasterizer/jitter/fetch_jit.cpp | 4
2 files changed, 5 insertions(+)
diff --git a/src/gallium/drivers/swr/rasterizer/jitter/builder_mem
"typename SIMD_T::TypeName" --> "TypeName"
---
.../drivers/swr/rasterizer/common/simdlib.hpp | 9 +
src/gallium/drivers/swr/rasterizer/core/binner.cpp | 338 ++---
src/gallium/drivers/swr/rasterizer/core/binner.h | 18 +-
src/gallium/drivers/swr/rasterizer/core/clip.h
GEP was given the wrong type, and asserting.
---
src/gallium/drivers/swr/rasterizer/jitter/builder_mem.cpp | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/gallium/drivers/swr/rasterizer/jitter/builder_mem.cpp
b/src/gallium/drivers/swr/rasterizer/jitter/builder_mem.cpp
in
Consolidate archrst draw events into single draw event with an attribute
that represents the type of draw
- Add handlers for new private proto versions of DrawInstancedEvent,
DrawIndexedInstancedEvent, DrawInstancedSplitEvent, and
DrawIndexedInstancedSplitEvent
- Convert the draw events to gen
in template gen_llvm.hpp
---
src/gallium/drivers/swr/rasterizer/codegen/templates/gen_llvm.hpp | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/gallium/drivers/swr/rasterizer/codegen/templates/gen_llvm.hpp
b/src/gallium/drivers/swr/rasterizer/codegen/templates/gen_llvm.hp
---
src/gallium/drivers/swr/rasterizer/jitter/builder_mem.cpp | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/src/gallium/drivers/swr/rasterizer/jitter/builder_mem.cpp
b/src/gallium/drivers/swr/rasterizer/jitter/builder_mem.cpp
index 491fb98..617cf33 100644
--- a/src/g
---
.../drivers/swr/rasterizer/jitter/JitManager.h | 38 +++---
1 file changed, 19 insertions(+), 19 deletions(-)
diff --git a/src/gallium/drivers/swr/rasterizer/jitter/JitManager.h
b/src/gallium/drivers/swr/rasterizer/jitter/JitManager.h
index ddd6864..3660249 100644
--- a/s
Together with correct detection of clipDistance NaNs when no cullDistance is set
---
src/gallium/drivers/swr/rasterizer/core/clip.h| 2 +-
src/gallium/drivers/swr/rasterizer/core/context.h | 26
src/gallium/drivers/swr/rasterizer/core/state.h | 81 +--
3 files c
Don't count on the compiler automagically converting an srli call to
srl if the shift count isn't an immediate.
---
src/gallium/drivers/swr/rasterizer/common/simdlib_128_avx.inl | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/swr/rasterizer/common/simdli
Fix invalid number of attributes passed into tesselation PA.
Needs to take into account any offsets from the shader.
nnocuous issue, but removes an assert firing in debug.
---
src/gallium/drivers/swr/rasterizer/core/frontend.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/s
---
src/gallium/drivers/swr/rasterizer/core/api.cpp | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/gallium/drivers/swr/rasterizer/core/api.cpp
b/src/gallium/drivers/swr/rasterizer/core/api.cpp
index f45da96..99d3cd5 100644
--- a/src/gallium/drivers/swr/rasterizer/core/a
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