From: Dave Airlie
This fixes bad interactions with the LDS special values.
---
src/gallium/drivers/r600/sb/sb_core.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/gallium/drivers/r600/sb/sb_core.cpp
b/src/gallium/drivers/r600/sb/sb_core.cpp
index cdc2862d36
From: Dave Airlie
It's rare to have a final alu clause on normal shaders (exports)
but tess shaders write to LDS as their output, so we see some
alu clauses, and the CF_END get put in the wrong place.
This makes sure to update last_cf correctly.
Signed-off-by: Dave Airlie
---
src/ga
From: Dave Airlie
This adds support for GDS ops to sb backend.
This seems to work for atomics and tess factor writes.
Signed-off-by: Dave Airlie
---
src/gallium/drivers/r600/r600_isa.h| 2 +-
src/gallium/drivers/r600/sb/sb_bc.h| 7
src/gallium/drivers/r600/sb
From: Dave Airlie
This stops them being optimised out.
---
src/gallium/drivers/r600/sb/sb_bc_parser.cpp | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/src/gallium/drivers/r600/sb/sb_bc_parser.cpp
b/src/gallium/drivers/r600/sb/sb_bc_parser.cpp
index ae92a767b4
From: Dave Airlie
For LDS read/write ordering we use the LDS_RW value, reads
will wait on previous writes.
For LDS read/read from LDS queue ordering we use the LDS_OQ
values, we define two for now, though initially we'll just
support OQA.
Also add the check for the lds oq values
Signed-o
From: Dave Airlie
We need to convert these to the hw special registers.
---
src/gallium/drivers/r600/sb/sb_bc_finalize.cpp | 12
1 file changed, 12 insertions(+)
diff --git a/src/gallium/drivers/r600/sb/sb_bc_finalize.cpp
b/src/gallium/drivers/r600/sb/sb_bc_finalize.cpp
index
This is an attempt to add tessellation support to the SB backend.
The main things needed are GDS access which is used for tess
factor storage (also used for atomic counters), and LDS access
which is needed to pass all the data between stages.
The first 19 patches are the stuff I'm happy with, the
From: Dave Airlie
Just saves a pointless a = a + 0;
Signed-off-by: Dave Airlie
---
src/gallium/drivers/r600/r600_shader.c | 14 --
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/src/gallium/drivers/r600/r600_shader.c
b/src/gallium/drivers/r600/r600_shader.c
index
On 10 January 2018 at 12:34, Bas Nieuwenhuizen wrote:
> Tested with a modified deferred demo and no regressions in a 1.0.2
> mustpass run.
For the series:
Reviewed-by: Dave Airlie
> ---
> src/amd/vulkan/radv_cmd_buffer.c | 51
> +++
&g
On 5 January 2018 at 01:14, Michal Srb wrote:
> From: =?UTF-8?q?Tom=C3=A1=C5=A1=20Chv=C3=A1tal?=
>
> Makes the egd_tables.py compatible with both python 2 and 3.
This appears to break the build here, I get a few () lines in the output.
I suspect print() needs to be print('')
Dave.
> ---
> sr
From: Dave Airlie
---
docs/features.txt | 2 +-
src/gallium/drivers/r600/r600_pipe.c | 2 +-
src/gallium/drivers/r600/r600_shader.c | 29 ++---
src/gallium/drivers/r600/r600_sq.h | 3 ++-
4 files changed, 30 insertions(+), 6 deletions
On 8 January 2018 at 17:12, Dave Airlie wrote:
> On 6 January 2018 at 03:41, Gert Wollny wrote:
>> Am Freitag, den 05.01.2018, 18:18 +0100 schrieb Gert Wollny:
>>>
>>> Well, I have tested some piglits now and the behaviour is quite
>>> wired:
>>>
>
On 6 January 2018 at 03:41, Gert Wollny wrote:
> Am Freitag, den 05.01.2018, 18:18 +0100 schrieb Gert Wollny:
>>
>> Well, I have tested some piglits now and the behaviour is quite
>> wired:
>>
>> When I run nop as the very first piglit after booting the machine it
>> works. After running other pig
On 8 January 2018 at 16:45, Timothy Arceri wrote:
> nir_to_llvm_context will always be NULL for radeonsi so we need
> work around this.
Reviewed-by: Dave Airlie
> ---
> src/amd/common/ac_nir_to_llvm.c | 17 -
> 1 file changed, 8 insertions(+), 9 deletions(-)
&
.
The current WSI already has some magic flags to pass things like the
no space for cmask flag.
For all 3:
Reviewed-by: Dave Airlie
Dave.
> ---
> src/amd/vulkan/Makefile.am | 7 +
> src/amd/vulkan/Makefile.sources | 3 +
> src/amd
On 29 December 2017 at 16:38, Dave Airlie wrote:
> On 11 December 2017 at 22:49, Gert Wollny wrote:
>> Am Freitag, den 08.12.2017, 16:30 +1000 schrieb Dave Airlie:
>>> [snip]
>>>
>>> So I haven't commited these yet, because I wanted to see if I could
>
On 11 December 2017 at 22:49, Gert Wollny wrote:
> Am Freitag, den 08.12.2017, 16:30 +1000 schrieb Dave Airlie:
>> [snip]
>>
>> So I haven't commited these yet, because I wanted to see if I could
>> get sb to work.
> Well, it was very much work in progress, I di
From: Dave Airlie
This should fix:
dEQP-VK.pipeline.sampler.view_type.*.format.b4g4r4a4_unorm_pack16.address_modes.all_mode_clamp_to_border_opaque_black
and a few others in that area.
Fixes: b11c4a5546 (radv: add texture descriptor/fmask/cmask support for GFX9)
Signed-off-by: Dave Airlie
From: Dave Airlie
amdvlk is probably more subtle than this but it never uses
the inv cb/db variants, we fail some CTS tests without this.
Fixes:
dEQP-VK.renderpass.dedicated_allocation.formats.d32_sfloat_s8_uint.input*.
Fixes: c2fbeb7ca05 (radv: add GFX9 cache flushing support.)
Signed-off-by
From: Dave Airlie
This ports a fix from amdvlk, to fix the sizing for mip levels
when block compressed images are viewed using uncompressed views.
Fixes:
dEQP-VK.image.texel_view_compatible.graphic.extended*bc*
Fixes: e38685cc62e 'Revert "radv: disable support for VEGA for now."
From: Dave Airlie
This fixes some of the broken:
dEQP-VK.synchronization.op.multi_queue.*64x64x8* tests.
Fixes: e38685cc62e 'Revert "radv: disable support for VEGA for now."'
Signed-off-by: Dave Airlie
---
src/amd/vulkan/radv_meta_bufimage.c | 73 ++
From: Dave Airlie
This fixes some of the broken:
dEQP-VK.synchronization.op.multi_queue.*64x64x8* tests.
Fixes: e38685cc62e 'Revert "radv: disable support for VEGA for now."'
Signed-off-by: Dave Airlie
---
src/amd/vulkan/radv_meta_bufimage.c | 75 ++
From: Dave Airlie
This fixes some of the broken:
dEQP-VK.synchronization.op.multi_queue.*64x64x8* tests.
Fixes: e38685cc62e 'Revert "radv: disable support for VEGA for now."'
Signed-off-by: Dave Airlie
---
src/amd/vulkan/radv_meta_bufimage.c | 62 ++
From: Dave Airlie
It's legal to a pipeline stat query on a compute queue,
but we'd emit the wrong packet here. This should fix it to emit
the correct packet.
Noticed while inspecting the mpv hang.
Signed-off-by: Dave Airlie
---
src/amd/vulkan/radv_query.c | 2 +-
1 file changed, 1
From: Dave Airlie
The event emission wasn't sending the correct packet for gfx8 compute
queues, which explains why it works on vega fine.
This fixes the mpv vulkan hang.
Fixes: ad61eac250 (radv: factor out eop event writing code. (v2))
Signed-off-by: Dave Airlie
---
src/amd/v
From: Dave Airlie
These seem mildly unstable on vega, crashing CTS in various fun ways,
and looks like leaking memory.
Disable for now, but leave the option to enable them.
Signed-off-by: Dave Airlie
---
src/amd/vulkan/radv_debug.h | 1 +
src/amd/vulkan/radv_device.c
From: Dave Airlie
This fixes:
dEQP-VK.image.texel_view_compatible.graphic.basic.attachment_read.bc*r16g16b16a16_sfloat
dEQP-VK.image.extended_usage_bit.attachment_write.r16_sfloat
I've no idea if it's correct though.
Signed-off-by: Dave Airlie
---
src/amd/vulkan/radv_pipeline.c
7;d still need the buffer as it's unfixable since the hw requires
> always 0 unfortunately.)
For the series:
Reviewed-by: Dave Airlie
from previous experiments the hw doesn't work at all using vc fetch or
otherwise.
Dave.
___
mesa-dev mai
From: Dave Airlie
We destroy the pools but don't free the container.
This fixes:
dEQP-VK.wsi.xlib.swapchain.simulate_oom*
Fixes: d50937f137 (vulkan/wsi: Implement prime in a completely generic way)
Signed-off-by: Dave Airlie
---
src/vulkan/wsi/wsi_common.c | 1 +
1 file changed, 1 inse
> Framebuffer is from 0,0, not (dst.x, dst.y).
>
> Fixes: 69136f4e633 "radv/meta: add resolve pass using fragment/vertex shaders"
Reviewed-by: Dave Airlie
Dave.
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From: Dave Airlie
For copies the texture unit needs to know the depth format so
it can read the htile data properly.
This fixes:
dEQP-VK.renderpass.suballocation.formats.d32_sfloat_s8_uint.load.clear
Signed-off-by: Dave Airlie
---
src/amd/vulkan/radv_meta_copy.c | 3 ++-
1 file changed, 2
From: Dave Airlie
This needs to correspond to the bit depth of the Z plane.
noticed in passing reading amdvlk.
Signed-off-by: Dave Airlie
---
src/amd/vulkan/radv_image.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan
On 27 December 2017 at 10:20, Bas Nieuwenhuizen
wrote:
> the samples_identical instruction returns 0 if they are differet, so
> we have to do the extra work if the result is 0, not if it is != 0.
>
I think I lost the logic trail on this code a few times.
Patches look good.
Reviewed
From: Dave Airlie
AMDVLK says that these don't work, so disable them.
Signed-off-by: Dave Airlie
---
src/gallium/drivers/radeonsi/si_clear.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/src/gallium/drivers/radeonsi/si_clear.c
b/src/gallium/drivers/rad
From: Dave Airlie
From AMDVLK fast clears don't work with cmask on gfx9, only with
dcc, so we don't need to allocate cmask for single sampled surfaces.
Signed-off-by: Dave Airlie
---
src/amd/vulkan/radv_image.c | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff -
From: Dave Airlie
This is ported from amdvlk.
Signed-off-by: Dave Airlie
---
src/amd/vulkan/radv_device.c| 10 ++
src/gallium/drivers/radeonsi/si_state.c | 9 +
2 files changed, 19 insertions(+)
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan
From: Dave Airlie
This is ported from amdvlk which sets the independent 64b blocks
only for image which will sample dcc.
I'm not sure how to port this to radeonsi.
Signed-off-by: Dave Airlie
---
src/amd/vulkan/radv_device.c | 11 ++-
1 file changed, 10 insertions(+), 1 del
From: Dave Airlie
These are just taken from amdvlk, we probably knew these already,
but may as well port them now.
Signed-off-by: Dave Airlie
---
src/amd/common/sid.h| 6 ++
src/amd/vulkan/radv_device.c| 6 +++---
src/gallium/drivers/radeonsi/si_state.c | 6
On 22 December 2017 at 12:14, Dave Airlie wrote:
> From: Dave Airlie
>
> If we are using tc compatible depth image as textures, it seems
> that we would need to make sure the depth/stencil clear registers
> are reloaded with the correct values before accessing the image.
Ignore
From: Dave Airlie
If we are using tc compatible depth image as textures, it seems
that we would need to make sure the depth/stencil clear registers
are reloaded with the correct values before accessing the image.
This was a failed attempt to fix
dEQP
On 21 December 2017 at 19:52, Alex Smith wrote:
> Nice - this does fix the issue I was seeing, thanks.
>
> Can at least patches 2 and 3 go to stable?
Yes once I get some review I'll tag those two for stable.
Dave.
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From: Dave Airlie
If we are doing a general->general transfer with HIZ enabled,
we want to hit the tile surface disable bits in radv_emit_fb_ds_state,
however we never get the current layout to know we are in general
and meta hardcoded the transfer layout which is always tile enabled.
T
From: Dave Airlie
This fixes the layout issue for the blit path as well.
This fixes:
dEQP-VK.api.copy_and_blit.core.blit_image.all_formats.depth_stencil.d32_sfloat_s8_uint_d32_sfloat_s8_uint*
v2: use compatible render passes.
Signed-off-by: Dave Airlie
---
src/amd/vulkan/radv_meta_blit.c
From: Dave Airlie
This fixes the layout issue for the blit path as well.
This fixes:
dEQP-VK.api.copy_and_blit.core.blit_image.all_formats.depth_stencil.d32_sfloat_s8_uint_d32_sfloat_s8_uint*
Signed-off-by: Dave Airlie
---
src/amd/vulkan/radv_meta_blit.c | 537
From: Dave Airlie
If we are doing a general->general transfer with HIZ enabled,
we want to hit the tile surface disable bits in radv_emit_fb_ds_state,
however we never get the current layout to know we are in general
and meta hardcoded the transfer layout which is always tile enabled.
T
From: Dave Airlie
If we are doing a general->general transfer with HIZ enabled,
we want to hit the tile surface disable bits in radv_emit_fb_ds_state,
however we never get the current layout to know we are in general
and meta hardcoded the transfer layout which is always tile enabled.
T
> wrote:
>> This reverts commit ff0f17da1446e7aa965e06c04a6ad5a55d95463d.>>
>> See the TODO.
I think I've sent the correct fix now.
Dave.
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From: Dave Airlie
This fixes vmfaults seen on vega with:
dEQP-VK.pipeline.multisample_interpolation.sample_interpolate_at_single_sample_.128_128_1.samples_1
These were caused by the don't allocate cmask but it was just accidental.
The actual problem was the shader was trying to get the s
From: Dave Airlie
On GFX9 we must access 3D textures with 3D samplers AFAICS.
This fixes:
dEQP-VK.api.image_clearing.core.clear_color_image.3d.single_layer
on GFX9 for me.
v1.1: fix tex->sampler_dim to dim
v2: send layer in from outside
v3: don't regress on pre-gfx9
Fixes: e38
From: Dave Airlie
This add support for a 3D image reading path to the blit 2d paths,
like I did for the clear paths.
Signed-off-by: Dave Airlie
---
src/amd/vulkan/radv_meta_blit2d.c | 110 +++---
src/amd/vulkan/radv_private.h | 10 ++--
2 files changed, 97
From: Dave Airlie
looking at traces I noticed we'd set slice_max too large sometimes.
This should fix it.
Signed-off-by: Dave Airlie
---
src/amd/vulkan/radv_device.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/src/amd/vulkan/radv_device.c b/sr
From: Dave Airlie
This just refactors the gfx9 blit2d pipeline creation
to be less lines of code.
Signed-off-by: Dave Airlie
---
src/amd/vulkan/radv_meta_blit2d.c | 111 --
1 file changed, 33 insertions(+), 78 deletions(-)
diff --git a/src/amd/vulkan
This series fixes about 340 CTS tests on Vega that involve 3D images.
The two main things are to use 3D samplers for copy paths sources that
are 3D images.
I've also found another bug, and refactors a bit of code at the end.
I've also test this on a tonga and tests don't seem to break.
Dave.
_
On 21 December 2017 at 03:46, Alex Smith wrote:
> Looks like blit2d needs this fix as well - been debugging an issue that's
> turned out to be due to a corrupted copy of a 3D texture with CmdCopyImage.
> I can do that tomorrow.
I already wrote that as well,
https://github.com/airlied/mesa/tree/r
From: Dave Airlie
On GFX9 we must access 3D textures with 3D samplers AFAICS.
This fixes:
dEQP-VK.api.image_clearing.core.clear_color_image.3d.single_layer
on GFX9 for me.
v2: fixes a bunch of other tests as well.
v1.1: fix tex->sampler_dim to dim
v2: send layer in from outside
Fi
From: Dave Airlie
On GFX9 we must access 3D textures with 3D samplers AFAICS.
This fixes:
dEQP-VK.api.image_clearing.core.clear_color_image.3d.single_layer
on GFX9 for me.
Fixes: e38685cc62e 'Revert "radv: disable support for VEGA for now."'
Signed-off-by: Dave Airlie
From: Dave Airlie
This wasn't calculating the correct value, this along with
a nir patch fixes a regression in:
dEQP-VK.tessellation.shader_input_output.barrier
Fixes: 043d14db30a (ac/nir: don't write tcs outputs to LDS that aren't read
back.)
Signed-off-by: Dave Airlie
---
From: Dave Airlie
If we don't remap and output this code would trample the outputs
read bits.
This fixes a regression in
dEQP-VK.tessellation.shader_input_output.barrier
Fixes: 1c9c42d16b4c (nir: add varying component packing helpers)
Signed-off-by: Dave Airlie
---
src/compile
From: Dave Airlie
anv merges the tess info correctly, but radv wasn't doing this.
This fixes hangs in
dEQP-VK.tessellation.winding.default_domain.hlsl_triangles_ccw
Fixes: 60fc0544e0 (radv/pipeline: handle tessellation shader compilation)
Signed-off-by: Dave Airlie
---
src/amd/v
On 17 December 2017 at 10:11, Bas Nieuwenhuizen
wrote:
> For the radv dependencies on syncobj signal/reset.
I've released 2.4.89 with those patches,
So, for the series,
Reviewed-by: Dave Airlie
Dave.
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On 18 December 2017 at 09:11, Bas Nieuwenhuizen
wrote:
> We did not set the layer correctly for the dst, as we would keep
> using the base layer. Same for the source image.
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102710
> CC:
Reviewed-by: Dave Airlie
&
On 15 November 2017 at 19:29, Gert Wollny wrote:
> Dear all,
>
> since on r600 the tesselation shaders don't go through the sb-optimizer I
> though it might help to improve performance by applying some optimizations
> to the created assembly. The patches are experimental but to a point where
> I t
From: Dave Airlie
This stops them being optimised out.
---
src/gallium/drivers/r600/sb/sb_bc_parser.cpp | 3 +++
1 file changed, 3 insertions(+)
diff --git a/src/gallium/drivers/r600/sb/sb_bc_parser.cpp
b/src/gallium/drivers/r600/sb/sb_bc_parser.cpp
index ae92a767b4c..8a4abd48306 100644
--- a
From: Dave Airlie
This adds support for GDS ops to sb backend.
It seems to work for atomic counters on cayman, probably
needs a lot more testing.
---
src/gallium/drivers/r600/r600_isa.h| 2 +-
src/gallium/drivers/r600/sb/sb_bc.h| 7 +
src/gallium/drivers/r600/sb
This is a first pass at adding GDS support to the r600/sb backend,
along with a small compute shader fix.
For compute shaders, LDS needs supporting as well.
Dave.
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On 30 November 2017 at 22:06, Gert Wollny wrote:
> Am Donnerstag, den 30.11.2017, 17:56 +1000 schrieb Dave Airlie:
>> On 30 November 2017 at 17:20, Gert Wollny
>> wrote:
>> > Am Donnerstag, den 30.11.2017, 09:30 +1000 schrieb Dave Airlie:
>> > > On 29
and because I guess the rounding mode behaviour is similar between
> GL and VK, we can use it. About performance, it improves Talos
> by +3/4% but I don't see any other impacts.
>
> No CTS regressions on Polaris (Vega in progress).
Seems like a good plan.
Reviewed-by: Dave Airlie
From: Dave Airlie
Don't try and use the image format for ssbo, just 32-bit uint.
Signed-off-by: Dave Airlie
---
src/gallium/drivers/r600/r600_shader.c | 16
1 file changed, 12 insertions(+), 4 deletions(-)
diff --git a/src/gallium/drivers/r600/r600_shader.c
b/src/ga
From: Dave Airlie
This fixes loading from different channels.
Signed-off-by: Dave Airlie
---
src/gallium/drivers/r600/r600_shader.c | 12 +++-
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/src/gallium/drivers/r600/r600_shader.c
b/src/gallium/drivers/r600/r600_shader.c
From: Dave Airlie
This works best for returning the correct values and sizes in
tests.
Signed-off-by: Dave Airlie
---
src/gallium/drivers/r600/evergreen_state.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/src/gallium/drivers/r600/evergreen_state.c
b/src/gallium
From: Dave Airlie
The atomic rat path has a bug in the ssbo path, refactor out the
address calcs from the load/store paths and reuse to fix the bug
in the buffer rat atomic path.
Signed-off-by: Dave Airlie
---
src/gallium/drivers/r600/r600_shader.c | 71 ++
1
From: Dave Airlie
This just refactors the same code out of the images/buffers paths.
Signed-off-by: Dave Airlie
---
src/gallium/drivers/r600/evergreen_state.c | 66 +-
1 file changed, 28 insertions(+), 38 deletions(-)
diff --git a/src/gallium/drivers/r600
From: Dave Airlie
This just changes how thread id loading is done, it makes
smaller shaders if we don't use thread id gprs.
Signed-off-by: Dave Airlie
---
src/gallium/drivers/r600/r600_shader.c | 27 ++-
1 file changed, 18 insertions(+), 9 deletions(-)
diff --
I've been running deqp-gles31 over the r600 ssbo/image code
it uses compute shaders, but I've found a few bugs in the in-tree
code, so just sending some fixes out for those first.
ssbo seems to pass all the tests, images have some heisenbug
where they pass sometimes and not others.
Dave.
___
From: Dave Airlie
On Cayman we don't use the append/consume counters (fglrx doesn't)
and they don't seem to work well with compute shaders.
This just uses GDS instead to do the atomic operations.
v1.1: remove unused line.
v2: use EOS on cayman, it appears to work.
Signed-off-
On 1 December 2017 at 20:49, Nicolai Hähnle wrote:
> On 01.12.2017 06:06, Dave Airlie wrote:
>>
>> From: Dave Airlie
>>
>> On Cayman we don't use the append/consume counters (fglrx doesn't)
>> and they don't seem to work well with compute sha
From: Dave Airlie
On Cayman we don't use the append/consume counters (fglrx doesn't)
and they don't seem to work well with compute shaders.
This just uses GDS instead to do the atomic operations.
Signed-off-by: Dave Airlie
---
src/gallium/drivers/r600/evergre
From: Dave Airlie
For cayman we want to use different code paths.
Signed-off-by: Dave Airlie
---
src/gallium/drivers/r600/evergreen_state.c | 80 +++---
1 file changed, 50 insertions(+), 30 deletions(-)
diff --git a/src/gallium/drivers/r600/evergreen_state.c
b/src
There appears to be some bad interaction with the append/consume counters
on cayman (and compute shaders at least). I traced fglrx and it appears
it directly uses GDS memory.
This adds cayman specific paths to directly use GDS memory for these
atomics.
Dave.
_
On 30 November 2017 at 17:20, Gert Wollny wrote:
> Am Donnerstag, den 30.11.2017, 09:30 +1000 schrieb Dave Airlie:
>> On 29 November 2017 at 22:46, Gert Wollny
>> wrote:
>> >
>> >
>> > I run the arb_compute_shader piglits on BARTS, the piglits
>>
On 29 November 2017 at 14:36, Dave Airlie wrote:
> This set of patches enables compute shaders on r600 and exposes GLSL 4.30
> support. They are pretty alpha level, but I'd like to land some of them
> (maybe disabled) so I can avoid the rebasing fun with the more intrusive
> ones
like the best place to start.
Reviewed-by: Dave Airlie
>
> Signed-off-by: Samuel Pitoiset
> ---
> src/amd/vulkan/radv_image.c | 10 ++
> 1 file changed, 10 insertions(+)
>
> diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
> index c241e369b9..
On 29 November 2017 at 22:46, Gert Wollny wrote:
> Am Mittwoch, den 29.11.2017, 14:36 +1000 schrieb Dave Airlie:
>> This set of patches enables compute shaders on r600 and exposes GLSL
>> 4.30 support. They are pretty alpha level, but I'd like to land some
>> of them
From: Dave Airlie
This add paths to handle TGSI compute shaders and shader selection.
It also avoids emitting certain things on tgsi paths,
CBs, vertex buffers, config reg init (not required).
---
src/gallium/drivers/r600/evergreen_compute.c | 125 -
.../drivers/r600
From: Dave Airlie
---
src/gallium/drivers/r600/evergreen_compute.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/src/gallium/drivers/r600/evergreen_compute.c
b/src/gallium/drivers/r600/evergreen_compute.c
index 7df1c55..b8e1c20 100644
--- a/src/gallium/drivers/r600
From: Dave Airlie
---
src/gallium/drivers/r600/evergreen_compute.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/src/gallium/drivers/r600/evergreen_compute.c
b/src/gallium/drivers/r600/evergreen_compute.c
index b8e1c20..c9e649e 100644
--- a/src/gallium/drivers
From: Dave Airlie
This appears to cause hangs with compute images. Unless
we can find more specifics, just don't do this for now.
Signed-off-by: Dave Airlie
---
src/gallium/drivers/r600/r600_texture.c | 8
1 file changed, 8 deletions(-)
diff --git a/src/gallium/drivers
From: Dave Airlie
---
src/gallium/drivers/r600/r600_pipe.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/r600/r600_pipe.c
b/src/gallium/drivers/r600/r600_pipe.c
index 01f9bf6..b013d69 100644
--- a/src/gallium/drivers/r600/r600_pipe.c
+++ b/src
From: Dave Airlie
This just adds support for decompressing compute resources.
Signed-off-by: Dave Airlie
---
src/gallium/drivers/r600/r600_pipe.h | 1 +
src/gallium/drivers/r600/r600_state_common.c | 31 ++--
2 files changed, 26 insertions(+), 6 deletions
From: Dave Airlie
This is needed for compute shaders.
v1.1: make work for vectors, fix missing lds ops.
Signed-off-by: Dave Airlie
---
src/gallium/drivers/r600/r600_shader.c | 165 +
1 file changed, 165 insertions(+)
diff --git a/src/gallium/drivers/r600
From: Dave Airlie
We just pass these in from outside in a constant buffer.
The shader side stores them once they are accessed once.
Signed-off-by: Dave Airlie
---
src/gallium/drivers/r600/evergreen_compute.c | 9 +++-
src/gallium/drivers/r600/r600_pipe.h | 3 ++
src/gallium/drivers
From: Dave Airlie
---
src/gallium/drivers/r600/r600_pipe.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/gallium/drivers/r600/r600_pipe.c
b/src/gallium/drivers/r600/r600_pipe.c
index b013d69..e285608 100644
--- a/src/gallium/drivers/r600/r600_pipe.c
+++ b/src/gallium
From: Dave Airlie
---
src/gallium/drivers/r600/evergreen_compute.c | 13 -
1 file changed, 13 deletions(-)
diff --git a/src/gallium/drivers/r600/evergreen_compute.c
b/src/gallium/drivers/r600/evergreen_compute.c
index 7831b43..ff51ea3 100644
--- a/src/gallium/drivers/r600
From: Dave Airlie
This just adds the compute paths to state handling for the
main objects
---
src/gallium/drivers/r600/evergreen_state.c | 79 ++--
src/gallium/drivers/r600/r600_hw_context.c | 2 +
src/gallium/drivers/r600/r600_pipe.h | 6 ++-
src/gallium
From: Dave Airlie
---
src/gallium/drivers/r600/r600_pipe_common.c | 4
1 file changed, 4 insertions(+)
diff --git a/src/gallium/drivers/r600/r600_pipe_common.c
b/src/gallium/drivers/r600/r600_pipe_common.c
index 23f7d74..b611783 100644
--- a/src/gallium/drivers/r600/r600_pipe_common.c
From: Dave Airlie
---
src/gallium/drivers/r600/r600_shader.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/src/gallium/drivers/r600/r600_shader.c
b/src/gallium/drivers/r600/r600_shader.c
index 83b70b0..b3c29b9 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src
From: Dave Airlie
This just makes it easier to bypass for TGSI later.
Signed-off-by: Dave Airlie
---
src/gallium/drivers/r600/evergreen_compute.c | 50
1 file changed, 28 insertions(+), 22 deletions(-)
diff --git a/src/gallium/drivers/r600/evergreen_compute.c
b
From: Dave Airlie
This just moves some code around to make it easier to add compute.
---
src/gallium/drivers/r600/r600_pipe.h | 10 ++
src/gallium/drivers/r600/r600_state_common.c | 24 +---
2 files changed, 27 insertions(+), 7 deletions(-)
diff --git a/src
From: Dave Airlie
---
src/gallium/drivers/r600/evergreen_compute.c | 28
1 file changed, 20 insertions(+), 8 deletions(-)
diff --git a/src/gallium/drivers/r600/evergreen_compute.c
b/src/gallium/drivers/r600/evergreen_compute.c
index b976b61..7df1c55 100644
--- a
From: Dave Airlie
This appears to bad, compute shaders hang without it.
---
src/gallium/drivers/r600/r600_shader.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/gallium/drivers/r600/r600_shader.c
b/src/gallium/drivers/r600/r600_shader.c
index 41af0f5..e72215f 100644
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