Thomas,
i did have a look at the devices PWL and PWLR. you mentioned.
PWL works ok (default as a voltage type). The PWLR (default as a
differential voltage type) demands a part type attribute must be a value,
but i think its just a protel bug.
The parameter list of the PWLR includes the %vd(pin1,
Hi,
I changed the footprint, 40mil pitch with 20mil pads.
VIAs between SMD pad are 16mil pad and 8mil hole, we
want use this because there will be more room for
routing and SOLDERMASK is bigger between SMD pad
and VIA (I have 4mil opening for SMD pads and VIAs
are tentd or 0mil opening; which
they were meatball 10/10 mostly 12/12 bds
there was a giant pour on the entire top
the clearance on the pour was 20 mils all the way around the pads (to
make it easy and not get shorts!)
they said with a big plane it is harder to etch
there must be at least a bit of truth to that
Hello all,
I'm finalizing my PCB for first proto. Its a 4-layer board w/o internal
planes but uses signal layer polygon fill on each layer for the GND, SGND,
+15, -15 planes. My question today is: What considerations need to be made
when selecting the polygon fill parameters, relative to the
Tim,
first my observations. I have always found that 45 degree polygons
are a lot slower than 90 degree polygons at repouring. Since yours is
completely filled I don't see where 45 degree is doing anything for you.
Second, rather than using a grid matching the track width, I normally use
what about the question of octagon vs arcs on the pours?
we use the arcs (without notable problems) for whatever that is worth
they look nice anyway
Dennis Saputelli
Brad Velander wrote:
Tim,
first my observations. I have always found that 45 degree polygons
are a lot slower than
Thanks Brad. I thought the 45 degree might match up with the octagonal
surrounds for the pads but if it isn't needed I'll change it. Thanks for
the info.
Sincerely,
Tim Hutcheson
Institute for Human and Machine Cognition
University of West Florida
40 South Alcaniz St.
Pensacola, FL 32501
Dennis, Tim,
I use the arcs as well, with no problems to date. I don't know if
there is any optimization to using arcs or octagons. Personal preference
rules here.
Sincerely,
Brad Velander.
Lead PCB Designer
Norsat International Inc.
Microwave Products
Tel (604) 292-9089 (direct line)
Rolf
Since you have PWL working, I tried it again.
The netlist generation worked without generating any errors, result for the
PWL was;
AU1 AT FLUX AU1PWL
.MODEL AU1PWL PWL(X_ARRAY=[0 10 20 30 40 50 60 70 80 90 100] Y_ARRAY=[0
0.005
+ 0.01 0.025 0.04 0.075 0.125 0.2 0.29 0.38 0.475]
Juha,
First, sorry about the delay in responding, but the different time zones
make it hard to keep up. Secondly, I an certainly no guru on the subject,
but can only offer you a few things to think about as you approach this
board, and hopefully if someone out there knows better than I, they
Is there an actual datasheet for the specific device you are using?
Can you provide a Mfg and PN, and possibly a link?
It would help alot in seeing what you need.
Thanks, JaMi
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Juha,
OK, I looked at the layout, and the part number device, EP1S30, and did a
search on the net, and came up with ALTERA STRATIX.
Yes, the LVDS is in fact controlled impedance, 100 ohm differential, or you
could probably route individual lines at 50 ohm. It does appear that some of
the
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