Re: [PEDA] Through hole IPC recommendations

2003-02-28 Thread Ian Capps
Carlos You also need to consider your thermal releifs in the inner planes as this can play havoc with your solderability. Ian - Original Message - From: "Carlos Claveria" <[EMAIL PROTECTED]> To: <[EMAIL PROTECTED]> Sent: Thursday, February 27, 2003 8:08 AM Subject: [PEDA] Through hole IPC

Re: [PEDA] Through hole IPC recommendations

2003-02-28 Thread Clive . Broome
I used HMP solder once and it seemed to have either no flux in it or the flux burnt off very fast due to the high temps. You could try using extra flux. The other problem is soldering to gold plating. The solder reacts to the gold and will cause embrittlement of the joint. Im not sure the solutio

[PEDA] Testing! See Lloyd it is still up. 8^>

2003-02-28 Thread Brad Velander
Sincerely, Brad Velander. Lead PCB Designer Norsat International Inc. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mai

Re: [PEDA] Cut and Paste bug from schematics to MS Word

2003-02-28 Thread Mark HARRISON
Hi Brad, Haven't taken the plunge with DXP yet. No real incentive until another project comes along (i.e. one with a nice big budget that can afford DXP :-) Maybe I'll try the trial/demo version one day - when I run out of Windows & Xilinx bugs to solve and have some free time available :-) I shou

Re: [PEDA] Cut and Paste bug from schematics to MS Word

2003-02-28 Thread Mark HARRISON
Suzy, Thanks for the hint on cut-off edges. I think I tried printing the suspect schematic to a postscript file some time back but seem to recall there were some problems with this method also. My memory is not 100% on this (it may have been that the HP printer couldn't handle embedded postscript

[PEDA] Job Hunting

2003-02-28 Thread Lloyd Good
Hi all, I know some of you will recognize the name and it's been a while. I am no longer at my old employer and am seeking something either in PCB design of which I have 16 years experience or now I have recently added Solidworks 3D CAD to my repertoire, which comes in handy for PCB integration in

[PEDA] Through hole IPC recommendations

2003-02-28 Thread Carlos Claveria
Hello everyone, I was wondering if anyone could help me with this question. I built a 8 layer pcb with through hole components. I used 0.032" hole diameter and 0.050" gold plating. I have to use HMP (high melting point) solder and found that is really hard to get a good solder flow. I was wonderin

Re: [PEDA] A Question About Netlist Compare and Partially Matched Nets. Protel 99SE SP6.

2003-02-28 Thread Abd ul-Rahman Lomax
At 09:07 PM 2/21/2003, Mike Reagan wrote: The four steps work without failure, every time. I do not trust a netlist load without clearing first because as we all know we don'ts know which cycle even or odd the load is on. Sure we do. Just look at the macros. If they all remove net nodes, ywe have

Re: [PEDA] diff for protel schematics

2003-02-28 Thread Abd ul-Rahman Lomax
At 12:56 AM 2/24/2003, Ian Wilson wrote: You can extract netlists and do a net compare (between two Sch netlists), this is possibly the closest you will get in the P99 environment. You can also do a diff on the Sch if saved in ASCII format but this will possibly produce garbage output as there