Re: [PEDA] keepoutlayer and planes ??
draw pimitives (lines) on the planes around the perimeter to exclude copper in those areas the keepout doesn't limit the plane copper you generally want more than a few mils back off from the boundary, we usually place a 50 mil line on the center of the outline on the plane layer we generally do not use the keepout for the outline, sometimes they coincide, sometimes you want the keepout a little smaller or just different to avoid redrawing all the plane primitives just copy them and paste on current layer (the other plane(s) the keepout generally, at least for us, has no significance to the board shop good luck Dennis Saputelli Robison Michael R CNIN wrote: hello, we're duplicating some legacy boards. in order to avoid flight testing i hand-routed the traces to match the old artwork. i believe that i just came close to making a SERIOUS mistake. i used the pcb wizard to generate the board but then hand-editted the various notches in it. the keepout was in the way and i was going to hand rout everything so i deleted it. there is a power and ground plane on this board and there are machined metal card guides that get mounted to the board. does this sound ugly? i'm thinking (i know that's rare ;-) that by deleting the keepoutlayer i've let the planes come right out to the edge of the board. is this correct? if so, i've created a potential short between power and ground when the card guides are attached to the board. i put the keepoutlayer back on there, but i'm nervous. when i add the power plane to the viewable layers, the only place it is evident is around the pads and vias, where a dark green edge appears to isolate them. pads that are supposed to be tied to power have a broken circle out away from them a bit. but the dark green vcc void hasn't appeared outside my keepoutlayer. i get the feeling that putting the keepoutlayer back in there has not cured my problem. my questions: 1. the dark green i'm seeing represents the negative, or holes, in the power plane, correct? 2. after simply drawing the keepoutlayer back in, i am not seeing the dark green power plane void outside the keepoutlayer. does this mean that i still have the power plane running right to the board edge? 3. without a keepoutlayer do the planes extend right to the board edge? 4. how do i recess the power and ground planes back in a few mils on this board? 5. can i visibly see the planes recessed back from the card edge in protel or do i need to generate gerbers and use camtastic to do that? thank you, miker -- ___ www.integratedcontrolsinc.comIntegrated Controls, Inc. tel: 415-647-04802851 21st Street fax: 415-647-3003San Francisco, CA 94110 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] keepoutlayer and planes ??
Robison Michael R CNIN wrote: my questions: 1. the dark green i'm seeing represents the negative, or holes, in the power plane, correct? Yes 2. after simply drawing the keepoutlayer back in, i am not seeing the dark green power plane void outside the keepoutlayer. does this mean that i still have the power plane running right to the board edge? Yes - the power planes extend to the edge of the universe :-) The keepout boundary has no effect on them. 3. without a keepoutlayer do the planes extend right to the board edge? Far beyond it. 4. how do i recess the power and ground planes back in a few mils on this board? Draw tracks on the plane layers, on or inside the board boundaries, to keep the copper of that plane away from the edges. 5. can i visibly see the planes recessed back from the card edge in protel or do i need to generate gerbers and use camtastic to do that? If you put tracks around the edges you will see them in Protel. -- Peter Bennett TRIUMF 4004 Wesbrook Mall, Vancouver, BC, Canada GPS and NMEA info and programs: http://vancouver-webpages.com/peter/index.html * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] keepoutlayer and planes ??
Even without the card guides, you could get a short from slivers of copper left when the boards are cut. I was lucky -- on my first board with planes, I didn't know about putting traces along the edges, but the board shop called asked if we'd like them to pull the planes back from the board edges! So having a good board shop can pay off... -Original Message- From: Robison Michael R CNIN [mailto:[EMAIL PROTECTED]] Sent: Thursday, November 08, 2001 12:30 PM snip ... I've let the planes come right out to the edge of the board. ... If so, i've created a potential short between power and ground when the card guides are attached to the board. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] keepoutlayer and planes ??
technically and to be pedantic you should say Place Line (not track) Dennis Saputelli Ian Wilson wrote: On 03:29 PM 8/11/2001 -0500, Robison Michael R CNIN said: hello, my questions: 1. the dark green i'm seeing represents the negative, or holes, in the power plane, correct? Correct 2. after simply drawing the keepoutlayer back in, i am not seeing the dark green power plane void outside the keepoutlayer. does this mean that i still have the power plane running right to the board edge? Keepout does not affect planes. 3. without a keepoutlayer do the planes extend right to the board edge? With or without the keepout - Yes, planes extend to the edge. 4. how do i recess the power and ground planes back in a few mils on this board? Use tracks on the plane layer. The simplest method is to use select all the board outline tracks and the use the Paste Special to paste onto the current layer, changing the layer to each of the plane layers and pasting. Then de-select all the tracks on the board outline layer, leaving only the tracks on the plane layers selected, and then globally change the selected track widths to double your backoff - so a 50 mil track gives a 25 mil backoff. You can go a bit higher but usually not necessary. 5. can i visibly see the planes recessed back from the card edge in protel or do i need to generate gerbers and use camtastic to do that? Yes see point 4) Ian Wilson -- ___ www.integratedcontrolsinc.comIntegrated Controls, Inc. tel: 415-647-04802851 21st Street fax: 415-647-3003San Francisco, CA 94110 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] keepoutlayer and planes ??
thanks to everyone that posted on this. i understand now. it would have been inconceivably horrible if we had built and sold off on defective boards. these parts go in navy planes. and they could have very possibly passed functional testing and then started failing left and right once the planes started vibrating them around. thank god i don't design suspension bridges. ;-) there's irony there, i guess... you spend so much time sweating the details and then you let some big gaping bug in the design slip right past you. thanks again, miker -Original Message- From: Dennis Saputelli [mailto:[EMAIL PROTECTED]] Sent: Thursday, November 08, 2001 5:00 PM To: Protel EDA Forum Subject: Re: [PEDA] keepoutlayer and planes ?? technically and to be pedantic you should say Place Line (not track) Dennis Saputelli Ian Wilson wrote: On 03:29 PM 8/11/2001 -0500, Robison Michael R CNIN said: hello, my questions: 1. the dark green i'm seeing represents the negative, or holes, in the power plane, correct? Correct 2. after simply drawing the keepoutlayer back in, i am not seeing the dark green power plane void outside the keepoutlayer. does this mean that i still have the power plane running right to the board edge? Keepout does not affect planes. 3. without a keepoutlayer do the planes extend right to the board edge? With or without the keepout - Yes, planes extend to the edge. 4. how do i recess the power and ground planes back in a few mils on this board? Use tracks on the plane layer. The simplest method is to use select all the board outline tracks and the use the Paste Special to paste onto the current layer, changing the layer to each of the plane layers and pasting. Then de-select all the tracks on the board outline layer, leaving only the tracks on the plane layers selected, and then globally change the selected track widths to double your backoff - so a 50 mil track gives a 25 mil backoff. You can go a bit higher but usually not necessary. 5. can i visibly see the planes recessed back from the card edge in protel or do i need to generate gerbers and use camtastic to do that? Yes see point 4) Ian Wilson -- ___ www.integratedcontrolsinc.comIntegrated Controls, Inc. tel: 415-647-04802851 21st Street fax: 415-647-3003San Francisco, CA 94110 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] keepoutlayer and planes ??
At 02:00 PM 11/8/01 -0800, Dennis Saputelli wrote: technically and to be pedantic you should say Place Line (not track) It is not merely pedantic. A very frequent question is I'm trying to place a wide track (perhaps for the power plane clearance) and I can't place it on an inner plane and besides even though I set the width at 50 mils, it keeps coming out 10 mils. What gives? Often it is a long-time Protel user, familiar with an earlier version, recently upgraded, who asks this. He is using the old command Place/Track (P-T) to place the line, not noticing that there is no more Place Track command. Instead there is Place/ interactive rouTing, same hotkeys, which follows width rules and which will only place track on copper layers, and Place Line, which has no such restrictions. It was, by the way, a kindness for Protel to keep P-T working for the most common line placement operation. I remember when Tango changed many of their hotkey assignments, ostensibly to make PCB match schematic, and it took me years to unlearn the old and learn the new. And the irony was that, in the end, PCB and Schematic still did not match, and so there was the additional problem that similar functions in PCB and Schematic had different sequences. One of the common PCB sequences, in particular, would send you into a fairly long and not interruptable routine if you hit it in Schematic. And then there was incompatibility between Schematic itself and the schematic library editor. I once brought this up with Jeannine, the Tango support manager, and she simply noted the guy who did that is no longer with the company [EMAIL PROTECTED] Abdulrahman Lomax Easthampton, Massachusetts USA * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] minor display refresh bug
P99SE SP6, PCB Editor With Top Solder Mask and Outline (I name Mechanical 1 Outline) enabled, as initially displayed, with Outline being the current layer, only actual primitives on the Solder Mask and Outline layers are displayed. The calculated solder mask pads are not displayed. If one clicks on the Top Solder Mask tab to make it the current layer, the pads are displayed. If one then hits View/Refresh, top surface pads disappear, only through-hole pads continue to be displayed. If one makes Outline the current layer and then changes back to Top Solder Mask, the surface pads reappear. I could find no way to display any surface mount solder mask pads with Top Solder Mask as the only enabled layer. In this case, only through-hole solder mask pads appear. [EMAIL PROTECTED] Abdulrahman Lomax Easthampton, Massachusetts USA * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] keepoutlayer and planes ??
Robison Michael R CNIN wrote: hello, we're duplicating some legacy boards. in order to avoid flight testing i hand-routed the traces to match the old artwork. i believe that i just came close to making a SERIOUS mistake. i used the pcb wizard to generate the board but then hand-editted the various notches in it. the keepout was in the way and i was going to hand rout everything so i deleted it. there is a power and ground plane on this board and there are machined metal card guides that get mounted to the board. does this sound ugly? i'm thinking (i know that's rare ;-) that by deleting the keepoutlayer i've let the planes come right out to the edge of the board. is this correct? if so, i've created a potential short between power and ground when the card guides are attached to the board. I don't think the keepout prevents the internal power planes from existing under the keepout. (I think it will prevent an outer signal layer pour in that area.) What you need to do is place rectangular fills all around the edges of the board to hold the power planes out of that area. This is what I've been doing for years. 2. after simply drawing the keepoutlayer back in, i am not seeing the dark green power plane void outside the keepoutlayer. does this mean that i still have the power plane running right to the board edge? Yes, I believe so. 3. without a keepoutlayer do the planes extend right to the board edge? 4. how do i recess the power and ground planes back in a few mils on this board? See above. 5. can i visibly see the planes recessed back from the card edge in protel or do i need to generate gerbers and use camtastic to do that? Not really. You will see your fills, if you have them in ful mode, or just the outline of them if fills are in draft mode. My technique is this : 1. Generate Gerbers 2. Create new blank PCB 3. gang import (not exact term, but close) the gerbers onto this new PCB (do NOT make my mistake of importing getbers on TOP of existing PCB file!) 4. Shft/S to go to single layer mode 5. Now, you can go through the board, layer by layer with the + and - keys, and hit shift/S if you lose track of where you are spatially in the board. You can even use the report/measure function to measure pad sizes and clearances in the power or other inner layers to verify that your padstack settings are working right. Note that having the real PCB file open at the same time sets the gerber apertures so the gerber import works right. If you don't do this, the apertures may be set from the last board viewed, and a gerber import will make a picture that looks very wrong. Jon * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] minor display refresh bug
At 06:56 PM 8/11/01 -0500, you wrote: P99SE SP6, PCB Editor With Top Solder Mask and Outline (I name Mechanical 1 Outline) enabled, as initially displayed, with Outline being the current layer, only actual primitives on the Solder Mask and Outline layers are displayed. The calculated solder mask pads are not displayed. If one clicks on the Top Solder Mask tab to make it the current layer, the pads are displayed. If one then hits View/Refresh, top surface pads disappear, only through-hole pads continue to be displayed. If one makes Outline the current layer and then changes back to Top Solder Mask, the surface pads reappear. I could find no way to display any surface mount solder mask pads with Top Solder Mask as the only enabled layer. In this case, only through-hole solder mask pads appear. I suspect that we have all seen this sort of behavior in various conditions, it is irritating. It is certainly worth bringing it up so it can be discussed and Altium may make it an official bug. I think that there is some relationship here with the fact that multi-layer is a layer rather than a collection of other layers (subtle difference) but it has significant ramifications during the various combinations and permutations of display configuration. I think I would like to be able to define named collections of layers that can be used during pad stack creation and display manipulation. With this technique, multi-layer as an explicit layer is no longer needed - it merely becomes a layer collection consisting of all copper layers. Any pros or cons for this idea. Ian Wilson * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] keepoutlayer and planes ??
At 06:02 PM 11/8/01 -0600, Jon Elson wrote: What you need to do is place rectangular fills all around the edges of the board to hold the power planes out of that area. This is what I've been doing for years. The practice of copying the outline track to the inner planes, as described by others, and then blowing it out with a global edit to, say, 50 mils, is simpler and, with a complex outline, faster. Mr Elson made some good points about how to do gerber import. One note I would add is that Protel, if possible, flashes fills, it does not fill them, so when they are reimported, they become pads. Yes, pads. This introduces certain complications, trying to view solder mask imports. It's better, I suggest, to view gerbers in CAMtastic or another Gerber viewer. But it can be convenient to view them in Protel, and the ability to import gerber is a real plus for many reasons. [EMAIL PROTECTED] Abdulrahman Lomax Easthampton, Massachusetts USA * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] minor display refresh bug
At 11:31 AM 11/9/01 +1100, Ian Wilson wrote: I think I would like to be able to define named collections of layers that can be used during pad stack creation and display manipulation. With this technique, multi-layer as an explicit layer is no longer needed - it merely becomes a layer collection consisting of all copper layers. Any pros or cons for this idea. The multilayer layer causes all kinds of problems. For example, vias live on multilayer, intrinsically. But blind and buried vias are most certainly not on every copper layer. As as result of how Protel treats multilayer and vias, one cannot get a true, simple, single-layer display showing only the blind and buried vias present on a particular layer. It's a mess. The only way to correctly view it -- as far as I know -- is to generate the gerber and then view it with a gerber viewer or import it back. If it is imported back, presumably after removing everything but those vias, I can turn off multilayer and see the pads that will then exist on the appropriate layers. But then it will be a pain to edit, as well as increasing the file size. Basically, multilayer should go. Instead, there should be a button that enables all copper layers. Or perhaps multilayer should stay, but not be necessary. In other words, pads and vias will display even when multilayer is turned off, if they exist on the enabled layers. I thought that Protel worked this way, but I could not get P99SE to do it. If I wasn't so busy, I'd go back and see what Protel 98 did with this. (In other words, if you had top layer enabled, you saw pads and vias in the top layer color instead of the multilayer color. As it is in P99SE, they aren't in the display at all, only *surface* top layer pads display. As far as P98 is concerned, maybe my memory is incorrect.) Technically, this too is a bug. If you have top layer enabled, you should be able to see everything on the top layer It only becomes a serious bug when one is trying to do complex blind and buried via work. As it happens, that's my job at the moment grrr The saving grace is that Protel will cheerfully route over those spuriously displayed vias. And the plots are correct. [EMAIL PROTECTED] Abdulrahman Lomax Easthampton, Massachusetts USA * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] keepoutlayer and planes ??
i bet they pulled them back as SOP Dennis Saputelli Nicholas Cobb wrote: Someone please correct me if I am wrong, but I thought that the power plane clearance rule in the manufacturing section also included clearance from the keepout layer around the edge of the board. So far, I have never drawn any copper on the internal planes to keep them away from the edge of the board, and they have all turned out with clearance. This may be from the board house changing this, but I figured I would have heard something. Nick Cobb - Original Message - From: Abd ul-Rahman Lomax [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Thursday, November 08, 2001 7:34 PM Subject: Re: [PEDA] keepoutlayer and planes ?? At 06:02 PM 11/8/01 -0600, Jon Elson wrote: What you need to do is place rectangular fills all around the edges of the board to hold the power planes out of that area. This is what I've been doing for years. The practice of copying the outline track to the inner planes, as described by others, and then blowing it out with a global edit to, say, 50 mils, is simpler and, with a complex outline, faster. Mr Elson made some good points about how to do gerber import. One note I would add is that Protel, if possible, flashes fills, it does not fill them, so when they are reimported, they become pads. Yes, pads. This introduces certain complications, trying to view solder mask imports. It's better, I suggest, to view gerbers in CAMtastic or another Gerber viewer. But it can be convenient to view them in Protel, and the ability to import gerber is a real plus for many reasons. [EMAIL PROTECTED] Abdulrahman Lomax Easthampton, Massachusetts USA -- ___ www.integratedcontrolsinc.comIntegrated Controls, Inc. tel: 415-647-04802851 21st Street fax: 415-647-3003San Francisco, CA 94110 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] keepoutlayer and planes ??
At 07:59 PM 8/11/01 -0600, you wrote: Someone please correct me if I am wrong, Consider yourself corrected :-) Ian Wilson but I thought that the power plane clearance rule in the manufacturing section also included clearance from the keepout layer around the edge of the board. So far, I have never drawn any copper on the internal planes to keep them away from the edge of the board, and they have all turned out with clearance. This may be from the board house changing this, but I figured I would have heard something. Nick Cobb * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] minor display refresh bug
P99SE SP6, PCB Editor With Top Solder Mask and Outline (I name Mechanical 1 Outline) enabled, as initially displayed, with Outline being the current layer, only actual primitives on the Solder Mask and Outline layers are displayed. The calculated solder mask pads are not displayed. snip Abd ul-Rahman Lomax I suspect that we have all seen this sort of behavior in various conditions, it is irritating. It is certainly worth bringing it up so it can be discussed and Altium may make it an official bug. This has been a long standing aspect of Protel. My interpretation of what is happening is that pads on the external copper layers (and the MultiLayer layer) are imaged on the Solder Mask and Paste Mask layers, and as such, the software released to date does not always properly display what is really present on the Solder Mask and Paste Mask layers. (If the MultiLayer layer is *not* displayed, even images of pads on that layer are not always properly displayed on the Solder Mask layers.) I think that there is some relationship here with the fact that multi-layer is a layer rather than a collection of other layers (subtle difference) but it has significant ramifications during the various combinations and permutations of display configuration. I think I would like to be able to define named collections of layers that can be used during pad stack creation and display manipulation. With this technique, multi-layer as an explicit layer is no longer needed - it merely becomes a layer collection consisting of all copper layers. Any pros or cons for this idea. Ian Wilson There are arguments for and against providing the Multilayer layer. One argument for retaining it, or at least for pad and via objects (if not for arc, fill, track, and string objects), is that the *same* pad or via exists on *different* copper layers, and that aspect matches real world vias and through-hole pads. OTOH, given that a hierarchical structure exists in PCB files (e.g. component, polygon, coordinate and dimension objects), this could be extended so that pad and via objects themselves have a hierarchical structure. As such, users could define default settings for each layer, while also having the ability to customise (i.e. over-ride) the settings for each individual layer as required (including Solder Mask layers, Paste Mask layers, and even Power Plane layers). However, I also consider that efforts to change or enhance pad and via objects would open a very large can of worms. Amongst the issues to consider (but certainly not the only issues concerned) are whether properties associated with the Solder Mask layers, Paste Mask layers, and Power Plane layers should be set by Design Rules, or by dialog boxes, or by either of those options. (I have spoken on that matter previously; at present, listings of Design Rules do not report settings which have been customised by usage of dialog boxes.) Abd ul-Rahman Lomax has also recently mentioned that blind and buried vias are sometimes inappropriately displayed. I concur that this could be regarded as a bug, but apart from that, I personally don't regard the MultiLayer layer as being bad in nature. It is a special layer, like the Drill Draw, Drill Guide and Keep Out layers, but PCB applications differ from general purpose CAD applications (such as Autocad) in that there is a good case for special layers to be provided. I think that pad and via objects could be enhanced. However, we should be very careful about what we ask for... Regards, Geoff Harland. - E-Mail Disclaimer The Information in this e-mail is confidential and may be legally privileged. It is intended solely for the addressee. Access to this e-mail by anyone else is unauthorised. If you are not the intended recipient, any disclosure, copying, distribution or any action taken or omitted to be taken in reliance on it, is prohibited and may be unlawful. Any opinions or advice contained in this e-mail are confidential and not for public display. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] minor display refresh bug
At 01:50 PM 11/9/01 +1100, Geoff Harland wrote: However, I also consider that efforts to change or enhance pad and via objects would open a very large can of worms. Amongst the issues to consider (but certainly not the only issues concerned) are whether properties associated with the Solder Mask layers, Paste Mask layers, and Power Plane layers should be set by Design Rules, or by dialog boxes, or by either of those options. (I have spoken on that matter previously; at present, listings of Design Rules do not report settings which have been customised by usage of dialog boxes.) I'd think that a bug because a user might rely on the design rule believing that it is of universal application. But I have not researched this. In talking about the potential elimination of the Multilayer layer, however, no change is contemplated, per se, in how the calculated layers (solder mask, paste mask, inner planes, drill drawing) are handled. The actual utility of the Multilayer layer is quite limited. Almost never would one want to draw a track on that layer. It appears in plots of all copper layers, yet it does not DRC, as I recall. Right now, there are two uses: through pads and vias. A multilayer pad is one which appears on all copper layers. This, right away, is problematic, since the layer appearance of pads is customizable; it is the *hole* which definitely appears on all layers, *if* it is a through hole. Pads, however, may be placed on any layer individually. Protel gets drill-drawing indigestion if such single-layer pads have holes, as I recall. Vias, at present, can only be placed on the multilayer layer. Since vias can be blind or buried, the true display of a copper layer could be different depending on the layer. So a via is not really multilayer. Once upon a time it was, and Protel's implementation was reasonable, if not the best. (Basically, the difference between pads and vias has become academic.) There are certain functions of the multilayer layer, I suspect, that are used by various designers. It would be useful to enumerate those uses, so that we could suggest how to provide the same or better functionality while fixing the problems created by the multilayer concept. The *original* multilayer concept was that of an object that appeared the *same* on all copper layers. Thus a multilayer object could be displayed simply as it was, if and only if the multilayer layer was enabled, no problem. But that went out the door, first with surface mount, and then with blind and buried vias. Abd ul-Rahman Lomax has also recently mentioned that blind and buried vias are sometimes inappropriately displayed. Actually, they are *always* inappropriately displayed. Either you have multilayer turned off, in which case no vias are displayed at all, or you have it turned on, in which case vias are displayed unconditionally, whether or not they exist on the enabled layers. This is really a major shortcoming at the point, actually one of the worst of which I know. I concur that this could be regarded as a bug, but apart from that, I personally don't regard the MultiLayer layer as being bad in nature. It is a special layer, like the Drill Draw, Drill Guide and Keep Out layers, but PCB applications differ from general purpose CAD applications (such as Autocad) in that there is a good case for special layers to be provided. I have not heard, yet, any good argument for the maintenance of this layer as a layer. It is a concept more than it is a layer. A button that, in Display setup, turns on all copper layers would be useful. But a via is a via, it does not need a special layer! [EMAIL PROTECTED] Abdulrahman Lomax Easthampton, Massachusetts USA * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
