;[EMAIL PROTECTED]To: Protel EDA Forum <[EMAIL
PROTECTED]>
.com>cc:
Subject: Re: [PEDA] Protel Signal
Integrity -
une 11, 2003 7:52 PM
Subject: Re: [PEDA] Protel Signal Integrity - self help
>
> You are quite right, it is possible to create tiny loops under pads
> inadvertantly. This explains some of the problems. I carefully looked for
> this yesterday and found two instances. This still leaves a
AIL
PROTECTED]>
cc:
10-Jun-2003 08:06Subject: Re: [PEDA] Protel Signal
Integrity - sel
> I have carefully inspected the routes and no sign of loops anywhere. The
> analyzer seems to have particular problems with "T" networks. I have
cured
> one instance of this by removing the route, deleting the net, creating a
The loops could be under pads. I had this problem on a board and coul
ED]>
.com>cc:
Subject: Re: [PEDA] Protel Signal
Integrity
ED]To: "Protel EDA Forum" <[EMAIL
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.com>cc:
Subject: Re:
;Protel EDA Forum" <[EMAIL PROTECTED]>
Sent: Monday, June 09, 2003 8:22 PM
Subject: [PEDA] Protel Signal Integrity
>
> I have been trying to get a report out using the SI tool to provide info
> for an SDRAM interface. I have IBIS models and some results look useful.
> All the
I have been trying to get a report out using the SI tool to provide info
for an SDRAM interface. I have IBIS models and some results look useful.
All the same I am going nuts trying to sort out some less than well
documented aspects of the process. An SI report (Menu >Reports>SI) tells me
that I d
