Re: [PEDA] Connectivity Nightmares
Basic Schematics 101: ~ ~ ~ Rule 37: NEVER apply more than one Signal Name to the same Signal. PERIOD. Rule 38: NEVER apply the same Signal Name to more than one Signal. PERIOD. ~ ~ ~ Rule 274: No "ifs", "ands", or "buts" about any of the preceding 273 Rules. PERIOD. Rule 275: Never think that these Rules do not apply to you. PERIOD. Rule 276: Never forget these Rules. PERIOD. PERIOD The other 271 Rules - Don't even ask - If you have been in the industry for several years now and still don't know them by now, you are in deep yogurt and nothing will help you - If you are new to the industry, you will learn them in due time - Patience. - Original Message - From: <[EMAIL PROTECTED]> To: "Protel EDA Forum" <[EMAIL PROTECTED]> Sent: Wednesday, November 27, 2002 6:36 PM Subject: [PEDA] Connectivity Nightmares > Hi all: > > I usually use a hierarchical structure for my schematic documents, with a > main document with all the connectors on it, then below that a block > diagram, and then the actual circuitry on one or more levels below that. > > I'm currently doing a reasonable-sized board, with lots of digital lines, > and have amalgamated those lines into busses for the most part, however when > I try to synchronise my PCB, I get lots of errors due to the net labels I've > chosen not being mapped across separate sheets. I have tried to connect the > busses through the ports on the sheet symbol/port connectivity, but > apparently it doesn't work. Is the only solution here to change to net > labels/ports global (with a corresponding edit of all the sheets in the > schematic - 25 or so pages), or is there a way to get rid of these errors > using the current methodology? I've tried checking the add sheet suffixes to > local nets box, but this results in no connectivity, which is clearly not > what I want. > > Cheers, > Matthew van de Werken > Electronics Engineer > CSIRO Exploration & Mining - Gravity Group > 1 Technology Court - Pullenvale - Qld - 4069 > ph: (07) 3327 4685 fax: (07) 3327 4455 > email: [EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Connectivity Nightmares
I always assumed It had to be checked for multi sheet hierarchical designs, so that the synchroniser would count all the sheets as one big netlist, and you know what they say about assumptions (they're the mother of all f@*kups). I was wrong. What it really does is outlined on p132 of the Designers Handbook, "Model 5 - Using Sheet Parts to Create Hierarchy" Imagine you have a two pin daughter PCB you can place in a circuit, or alternatively you can install the components present on the daughter PCB directly onto the main PCB. Use a *component* to specify a sheet path to the daughter circuit, and when synchronising: 1) if you want to use the whole circuit on one PCB check the "Descend into sheet parts" box and all the component footprints present in the daughter PCB (component referenced sheet) will be used. or 2) if you want to use the daughter PCB module, uncheck the "Descend into sheet parts" box and a two pin footprint (for the daughter module) will be used instead. Clear as mud? > -Original Message- > From: Dennis Saputelli [mailto:[EMAIL PROTECTED]] > Sent: Thursday, 28 November 2002 15:17 > To: Protel EDA Forum > Subject: Re: [PEDA] Connectivity Nightmares > > > why? > what is the relevance of this? > i've never really understood that > > Dennis Saputelli > > > Thomas wrote: > > > > Do you have "Descend into sheet parts" ticked when running > the synchroniser? > > > > > -Original Message- > > > From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED]] > > > Sent: Thursday, 28 November 2002 14:21 > > > To: Protel EDA Forum > > > Subject: Re: [PEDA] Connectivity Nightmares > > > > > > > > > > > > > > At 12:36 PM 28/11/02 +1000, you wrote: > > > > >Hi all: > > > > > > > > > >I usually use a hierarchical structure for my schematic > > > > documents, with a > > > > >main document with all the connectors on it, then below > > > that a block > > > > >diagram, and then the actual circuitry on one or more levels > > > > below that. > > > > > > > > > >I'm currently doing a reasonable-sized board, with lots of > > > > digital lines, > > > > >and have amalgamated those lines into busses for the most part, > > > > > > > > Are these busses made up from dissimilar nets - that is stuff > > > > like nRD, > > > > nWR, nCSRAM all being merged in to a bus called something like > > > > CONTROLS? If so this won't work. Protel can only cope with > > > > busses of the > > > > "standard" form eg D[7..0] and nets D7 down to D0. > > > > > > A mixture of both; however I'm having just as much trouble on > > > the data bus > > > (TR_D00..TR_D15) as I am on the control busses... > > > > > > > > > > > > Cheers, > > > MvdW > > > > > > > > > > > > -- > __ > _ > www.integratedcontrolsinc.comIntegrated Controls, Inc. >tel: 415-647-04802851 21st Street > fax: 415-647-3003San Francisco, CA 94110 > * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Connectivity Nightmares
why? what is the relevance of this? i've never really understood that Dennis Saputelli Thomas wrote: > > Do you have "Descend into sheet parts" ticked when running the synchroniser? > > > -Original Message- > > From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED]] > > Sent: Thursday, 28 November 2002 14:21 > > To: Protel EDA Forum > > Subject: Re: [PEDA] Connectivity Nightmares > > > > > > > > > > At 12:36 PM 28/11/02 +1000, you wrote: > > > >Hi all: > > > > > > > >I usually use a hierarchical structure for my schematic > > > documents, with a > > > >main document with all the connectors on it, then below > > that a block > > > >diagram, and then the actual circuitry on one or more levels > > > below that. > > > > > > > >I'm currently doing a reasonable-sized board, with lots of > > > digital lines, > > > >and have amalgamated those lines into busses for the most part, > > > > > > Are these busses made up from dissimilar nets - that is stuff > > > like nRD, > > > nWR, nCSRAM all being merged in to a bus called something like > > > CONTROLS? If so this won't work. Protel can only cope with > > > busses of the > > > "standard" form eg D[7..0] and nets D7 down to D0. > > > > A mixture of both; however I'm having just as much trouble on > > the data bus > > (TR_D00..TR_D15) as I am on the control busses... > > > > > > > > Cheers, > > MvdW > > > > > > > -- ___ www.integratedcontrolsinc.comIntegrated Controls, Inc. tel: 415-647-04802851 21st Street fax: 415-647-3003San Francisco, CA 94110 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Connectivity Nightmares
I do now, but I don't think I did when I first ran it. I've pretty much solved the problem (except for the duplicate net errors I have to delete each time) by removing all nets from the pcb, then re-synchronising (of course, adding connected copper to nets). Cheers, Matthew van de Werken Electronics Engineer CSIRO Exploration & Mining - Gravity Group 1 Technology Court - Pullenvale - Qld - 4069 ph: (07) 3327 4685 fax: (07) 3327 4455 email: [EMAIL PROTECTED] > -Original Message- > From: Thomas [mailto:[EMAIL PROTECTED]] > Sent: Thursday, 28 November 2002 1:43 PM > To: 'Protel EDA Forum' > Subject: Re: [PEDA] Connectivity Nightmares > > > Do you have "Descend into sheet parts" ticked when running > the synchroniser? > > > -Original Message- > > From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED]] > > Sent: Thursday, 28 November 2002 14:21 > > To: Protel EDA Forum > > Subject: Re: [PEDA] Connectivity Nightmares > > > > > > > > > > At 12:36 PM 28/11/02 +1000, you wrote: > > > >Hi all: > > > > > > > >I usually use a hierarchical structure for my schematic > > > documents, with a > > > >main document with all the connectors on it, then below > > that a block > > > >diagram, and then the actual circuitry on one or more levels > > > below that. > > > > > > > >I'm currently doing a reasonable-sized board, with lots of > > > digital lines, > > > >and have amalgamated those lines into busses for the most part, > > > > > > Are these busses made up from dissimilar nets - that is stuff > > > like nRD, > > > nWR, nCSRAM all being merged in to a bus called something like > > > CONTROLS? If so this won't work. Protel can only cope with > > > busses of the > > > "standard" form eg D[7..0] and nets D7 down to D0. > > > > A mixture of both; however I'm having just as much trouble on > > the data bus > > (TR_D00..TR_D15) as I am on the control busses... > > > > > > > > Cheers, > > MvdW > > > > > > > > > > Ian Wilson > > > > > > * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Connectivity Nightmares
> Are these busses made up from dissimilar nets - that is stuff like nRD, > nWR, nCSRAM all being merged in to a bus called something like > CONTROLS? If so this won't work. Protel can only cope with busses of the > "standard" form eg D[7..0] and nets D7 down to D0. > > Ian Wilson As an aside, has DXP done anything to correct this problem? Cheers Don * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Connectivity Nightmares
Do you have "Descend into sheet parts" ticked when running the synchroniser? > -Original Message- > From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED]] > Sent: Thursday, 28 November 2002 14:21 > To: Protel EDA Forum > Subject: Re: [PEDA] Connectivity Nightmares > > > > > > At 12:36 PM 28/11/02 +1000, you wrote: > > >Hi all: > > > > > >I usually use a hierarchical structure for my schematic > > documents, with a > > >main document with all the connectors on it, then below > that a block > > >diagram, and then the actual circuitry on one or more levels > > below that. > > > > > >I'm currently doing a reasonable-sized board, with lots of > > digital lines, > > >and have amalgamated those lines into busses for the most part, > > > > Are these busses made up from dissimilar nets - that is stuff > > like nRD, > > nWR, nCSRAM all being merged in to a bus called something like > > CONTROLS? If so this won't work. Protel can only cope with > > busses of the > > "standard" form eg D[7..0] and nets D7 down to D0. > > A mixture of both; however I'm having just as much trouble on > the data bus > (TR_D00..TR_D15) as I am on the control busses... > > > > Cheers, > MvdW > > > > > > Ian Wilson > > > * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Connectivity Nightmares
> > At 12:36 PM 28/11/02 +1000, you wrote: > >Hi all: > > > >I usually use a hierarchical structure for my schematic > documents, with a > >main document with all the connectors on it, then below that a block > >diagram, and then the actual circuitry on one or more levels > below that. > > > >I'm currently doing a reasonable-sized board, with lots of > digital lines, > >and have amalgamated those lines into busses for the most part, > > Are these busses made up from dissimilar nets - that is stuff > like nRD, > nWR, nCSRAM all being merged in to a bus called something like > CONTROLS? If so this won't work. Protel can only cope with > busses of the > "standard" form eg D[7..0] and nets D7 down to D0. A mixture of both; however I'm having just as much trouble on the data bus (TR_D00..TR_D15) as I am on the control busses... Cheers, MvdW > > Ian Wilson > * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Connectivity Nightmares
Forgive me if you already know this: If any buss connects to a port make sure the busses have net labels. For example an 8 way buss with lines D0 to D7 connected to a port needs a net label "[D0..D7]" without the quotes placed on it for connectivity also the port must have the same name (that is [D0..D7]). See Schematic Help topic "Bus (Schematic electrical design object)" There is also an example on p99 of the manual. > -Original Message- > From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED]] > Sent: Thursday, 28 November 2002 13:37 > To: Protel EDA Forum > Subject: [PEDA] Connectivity Nightmares > > > Hi all: > > I usually use a hierarchical structure for my schematic > documents, with a > main document with all the connectors on it, then below that a block > diagram, and then the actual circuitry on one or more levels > below that. > > I'm currently doing a reasonable-sized board, with lots of > digital lines, > and have amalgamated those lines into busses for the most > part, however when > I try to synchronise my PCB, I get lots of errors due to the > net labels I've > chosen not being mapped across separate sheets. I have tried > to connect the > busses through the ports on the sheet symbol/port connectivity, but > apparently it doesn't work. Is the only solution here to change to net > labels/ports global (with a corresponding edit of all the > sheets in the > schematic - 25 or so pages), or is there a way to get rid of > these errors > using the current methodology? I've tried checking the add > sheet suffixes to > local nets box, but this results in no connectivity, which is > clearly not > what I want. > > Cheers, > Matthew van de Werken > Electronics Engineer > CSIRO Exploration & Mining - Gravity Group > 1 Technology Court - Pullenvale - Qld - 4069 > ph: (07) 3327 4685 fax: (07) 3327 4455 > email: [EMAIL PROTECTED] > * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Connectivity Nightmares
At 12:36 PM 28/11/02 +1000, you wrote: Hi all: I usually use a hierarchical structure for my schematic documents, with a main document with all the connectors on it, then below that a block diagram, and then the actual circuitry on one or more levels below that. I'm currently doing a reasonable-sized board, with lots of digital lines, and have amalgamated those lines into busses for the most part, Are these busses made up from dissimilar nets - that is stuff like nRD, nWR, nCSRAM all being merged in to a bus called something like CONTROLS? If so this won't work. Protel can only cope with busses of the "standard" form eg D[7..0] and nets D7 down to D0. Ian Wilson * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Connectivity Nightmares
Another data point: When I just create a netlist, there are duplicate nets with the same name formed - the solution here is obviously to generate only one net with that name, and append the new nodes to the existing net. Is there an easy way of doing this, since I'll have to do it numerous times as I get the pinout right? Cheers, Matthew van de Werken Electronics Engineer CSIRO Exploration & Mining - Gravity Group 1 Technology Court - Pullenvale - Qld - 4069 ph: (07) 3327 4685 fax: (07) 3327 4455 email: [EMAIL PROTECTED] > -Original Message- > From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED]] > Sent: Thursday, 28 November 2002 12:37 PM > To: Protel EDA Forum > Subject: [PEDA] Connectivity Nightmares > > > Hi all: > > I usually use a hierarchical structure for my schematic > documents, with a > main document with all the connectors on it, then below that a block > diagram, and then the actual circuitry on one or more levels > below that. > > I'm currently doing a reasonable-sized board, with lots of > digital lines, > and have amalgamated those lines into busses for the most > part, however when > I try to synchronise my PCB, I get lots of errors due to the > net labels I've > chosen not being mapped across separate sheets. I have tried > to connect the > busses through the ports on the sheet symbol/port connectivity, but > apparently it doesn't work. Is the only solution here to change to net > labels/ports global (with a corresponding edit of all the > sheets in the > schematic - 25 or so pages), or is there a way to get rid of > these errors > using the current methodology? I've tried checking the add > sheet suffixes to > local nets box, but this results in no connectivity, which is > clearly not > what I want. > > Cheers, > Matthew van de Werken > Electronics Engineer > CSIRO Exploration & Mining - Gravity Group > 1 Technology Court - Pullenvale - Qld - 4069 > ph: (07) 3327 4685 fax: (07) 3327 4455 > email: [EMAIL PROTECTED] > * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
