Re: [PEDA] Test point tenting on side opposite TP
> Joel, > Clicking Testpoint just marks it as a testpoint for output, but does not > even > automatically untent the via. So it would allow you to have soldermask on a > test point. > Hum, they might complain about that in the test department. >Seems the only solution/work around is create separate components for the > top and bottom testpoints and then modify them as needed. Protels treatment > of testpoints leaves something to be desired. > Perhaps the next version will give us the control we need. It would be nice > to have clearance checking for testpoint to testpoint spacing. And also > soldermask control for each side of the board, since you only need access > from one side, not both. > Carl I was wondering why a (testpoint) component had to be designed for each side of the PCB, as components can be moved from one side of the PCB to the other. But having said that, the Testpoint properties of pads are *not* updated whenever a pad is moved to the other side of a PCB, and regardless of whether a pad is part of a component or otherwise. Is there anyone who thinks that this behaviour is desirable? I.e. that pads' Testpoint properties should *not* be updated whenever a pad is moved to the other side of a PCB. (Maybe the user should be polled as to whether *none* of the pads and vias being "flipped" have their Testpoint properties updated, or *all* of these, or whether the user will be polled for *each* of these.) Vias are also problematic in this regard. (Although it is less likely for vias to be incorporated within footprints, this is still possible though.) And a related issue is what should happen to each via's LowLayer and HighLayer properties when vias are moved from one side of the PCB to the other. At present, these don't change, but a case could be made that the outside layer of all "blind" vias should toggle (even though this could result in vias using layer pairs which have not been defined by the user). Comments from other users on this one? I do not disagree with the concept of enhanced "padstacks" support (supporting, among other things, through-hole pads and vias having a soldermask opening on one side of the PCB but not on the other), and I have advocated this to some extent in the past. But I am also of the view that this is "can of worms" territory, because of issues as to whether the desired outcome should be achieved by using Design Rules, or dialog box entries, or by *either* of those methods. In some ways, the ideal would be to support either method, but a proper implementation of that approach would require dialog box entries to "auto-create" corresponding Design Rules, so that settings for pads and vias can be determined/checked either by viewing Design Rules or by viewing dialog box contents. But Design Rules could be problematic when the pads and vias these are applied to are not fully "identifiable"; if only *some* vias are to be masked on one side only (for instance), how are these to be identifed (via Design Rule entities)? Again, comments from others on this matter would be welcomed. (I have previously suggested that perhaps vias could support a name/designator property, so that Design Rules could be applied to vias on a selective basis, the selection criteria being of course based on the name assigned to each via.) Regards, Geoff Harland. - E-Mail Disclaimer The Information in this e-mail is confidential and may be legally privileged. It is intended solely for the addressee. Access to this e-mail by anyone else is unauthorised. If you are not the intended recipient, any disclosure, copying, distribution or any action taken or omitted to be taken in reliance on it, is prohibited and may be unlawful. Any opinions or advice contained in this e-mail are confidential and not for public display. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Test point tenting on side opposite TP
Joel, Clicking Testpoint just marks it as a testpoint for output, but does not even automatically untent the via. So it would allow you to have soldermask on a test point. Hum, they might complain about that in the test department. Seems the only solution/work around is create separate components for the top and bottom testpoints and then modify them as needed. Protels treatment of testpoints leaves something to be desired. Perhaps the next version will give us the control we need. It would be nice to have clearance checking for testpoint to testpoint spacing. And also soldermask control for each side of the board, since you only need access from one side, not both. Carl -Original Message- From: Joel Hammer [mailto:[EMAIL PROTECTED]] Sent: Friday, July 27, 2001 10:27 AM To: 'Protel EDA Forum' Subject: Re: [PEDA] Test point tenting on side opposite TP carl, have you clicked "top" or "bottom" test point in the pad/properties dialog box? (double click on pad in component editor) i've not had any problems in using that for a single-sided tp and not a th via. hope this helps. Joel L. Hammer PCB Layout/Cad Specialist E2 Enterprises Inc. 636.949.9101 Ext. 26 www.e2enterprises.com > -Original Message- > From: Schattke, Carl [mailto:[EMAIL PROTECTED]] > Sent: Friday, July 27, 2001 11:36 AM > To: Protel EDA Forum > Subject: [PEDA] Test point tenting on side opposite TP > > > Hello, >Has anyone figured out a work around so test points will > only be exposed > on > the tested side and tented on the untested side (like under > fine pitch SMT > components)? >Editing the Gerber's is the only way I know to do this now. :( > I would prefer something that be reproducible after revisions > are made. >Any news about a new version coming? > > Sincerely, > Carl Schattke, C.I.D. > Intel Corporation, ACT > Sr. Hardware Engineer ( PCB Design) > 122 Saratoga Ave. Suite 100 > Santa Clara, CA 95052 > Office 408-556-3122 > Fax 408-261-5869 > 24 Hr. Ph. 888-204-3704 > Email: [EMAIL PROTECTED] > > > * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Test point tenting on side opposite TP
carl, have you clicked "top" or "bottom" test point in the pad/properties dialog box? (double click on pad in component editor) i've not had any problems in using that for a single-sided tp and not a th via. hope this helps. Joel L. Hammer PCB Layout/Cad Specialist E2 Enterprises Inc. 636.949.9101 Ext. 26 www.e2enterprises.com > -Original Message- > From: Schattke, Carl [mailto:[EMAIL PROTECTED]] > Sent: Friday, July 27, 2001 11:36 AM > To: Protel EDA Forum > Subject: [PEDA] Test point tenting on side opposite TP > > > Hello, >Has anyone figured out a work around so test points will > only be exposed > on > the tested side and tented on the untested side (like under > fine pitch SMT > components)? >Editing the Gerber's is the only way I know to do this now. :( > I would prefer something that be reproducible after revisions > are made. >Any news about a new version coming? > > Sincerely, > Carl Schattke, C.I.D. > Intel Corporation, ACT > Sr. Hardware Engineer ( PCB Design) > 122 Saratoga Ave. Suite 100 > Santa Clara, CA 95052 > Office 408-556-3122 > Fax 408-261-5869 > 24 Hr. Ph. 888-204-3704 > Email: [EMAIL PROTECTED] > > > * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Test point tenting on side opposite TP
On 03:39 PM 27/07/2001 -0700, Abd ul-Rahman Lomax said: >Then make a solder mask expansion design rule to tent the pad for each >class as desired. Top and bottom masks can be subject to different design >rules by adding layer scope as the second term in the rule selection criteria. Restricting with layer scope will work for surface pads only. It is not possible to apply different mask expansions depending upon the layer, using design rules for multi-layer pads. I have written on this subject quite a number for times in the past and believe it is a significant oversight in the behavior of the program. There is no method in Protel of automatically tenting the top but not the bottom (or visa-versa) of a multi-layer pad/via using design rules. I also do testpoints as single pin components. They are 1mm round with a 5 mil think arc radius 47.5 mil on a mech layer to allow easy determination of our desired 100 mil TP clearance (we also set up design rules to check for this). The Protel TP finder does not allow you to specify minimum TP clearance so is not useful. As others have said the advantages of using a TP component are: 1) the TP is shown on the sch, which is a huge boon 2) full control of layer and tenting 3) testpoints can usually be located off vias (which one board stuffer has informed us is their preference where possible as it reduces the incidence of via barrels damaged by test probes). Ian Wilson * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Test point tenting on side opposite TP
At 12:29 PM 7/27/01 -0700, Schattke, Carl wrote: >I have test points on both sides due to the high density of the product. > I am using vias for test points in some locations, so if I give them a >negative expansion >then I will be covering my testpoints with mask. > Making parts for each testpoint may be my only way. With several hundred >points it is >more than a minor chore, but it would give me consistent results. But even >through hole parts don't let us manipulate the top and bottom masks >separately. > We really need Protel to give us access to the soldermask pads on the top >and bottom. I haven't done this, but here is how I would look to do it. If using components for test points, make a component class for top access and a component class for bottom access. You may be able to use the class generator to make a class of all selected components. Then make a solder mask expansion design rule to tent the pad for each class as desired. Top and bottom masks can be subject to different design rules by adding layer scope as the second term in the rule selection criteria. You could also use separate footprints for the top and bottom parts. Tent them all, but on the top-test-point footprint place a "pad" on the top solder mask layer of the footprint of the appropriate size, and analogously on the bottom. [EMAIL PROTECTED] Abdulrahman Lomax P.O. Box 690 El Verano, CA 95433 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Test point tenting on side opposite TP
I have two different testpoint components in my library, one for topside, one for bottom. This way you can just select them by pattern and edit the mask expansion. Reed At 12:29 PM 7/27/01 -0700, you wrote: >Reed, > Your solution would work if all the test points are on one side. >I have test points on both sides due to the high density of the product. > I am using vias for test points in some locations, so if I give them a >negative expansion >then I will be covering my testpoints with mask. > Making parts for each testpoint may be my only way. With several hundred >points it is >more than a minor chore, but it would give me consistent results. But even >through hole parts don't let us manipulate the top and bottom masks >separately. > We really need Protel to give us access to the soldermask pads on the top >and bottom. >Carl > > >-Original Message- >From: Reed Woltering [mailto:[EMAIL PROTECTED]] >Sent: Friday, July 27, 2001 11:34 AM >To: Protel EDA Forum >Subject: Re: [PEDA] Test point tenting on side opposite TP > > >The way I do this is to simply plot the soldermask for the side with the >testpoints >normally, and then select the testpoints, and edit the soldermask expansion >for >them to be negative, (ex: 30 mil TP gets -15mil expansion) and plot the >opposite >side to bury them in the mask. > >Reed Woltering >Cad Manager >Ariel Corporation > >At 09:35 AM 7/27/01 -0700, you wrote: > >Hello, > >Has anyone figured out a work around so test points will only be >exposed > >on > >the tested side and tented on the untested side (like under fine pitch SMT > >components)? > >Editing the Gerber's is the only way I know to do this now. :( > >I would prefer something that be reproducible after revisions are made. > >Any news about a new version coming? > > > >Sincerely, > >Carl Schattke, C.I.D. > >Intel Corporation, ACT > >Sr. Hardware Engineer ( PCB Design) > >122 Saratoga Ave. Suite 100 > >Santa Clara, CA 95052 > >Office 408-556-3122 > >Fax 408-261-5869 > >24 Hr. Ph. 888-204-3704 > >Email: [EMAIL PROTECTED] > > > > * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Test point tenting on side opposite TP
Reed, Your solution would work if all the test points are on one side. I have test points on both sides due to the high density of the product. I am using vias for test points in some locations, so if I give them a negative expansion then I will be covering my testpoints with mask. Making parts for each testpoint may be my only way. With several hundred points it is more than a minor chore, but it would give me consistent results. But even through hole parts don't let us manipulate the top and bottom masks separately. We really need Protel to give us access to the soldermask pads on the top and bottom. Carl -Original Message- From: Reed Woltering [mailto:[EMAIL PROTECTED]] Sent: Friday, July 27, 2001 11:34 AM To: Protel EDA Forum Subject: Re: [PEDA] Test point tenting on side opposite TP The way I do this is to simply plot the soldermask for the side with the testpoints normally, and then select the testpoints, and edit the soldermask expansion for them to be negative, (ex: 30 mil TP gets -15mil expansion) and plot the opposite side to bury them in the mask. Reed Woltering Cad Manager Ariel Corporation At 09:35 AM 7/27/01 -0700, you wrote: >Hello, >Has anyone figured out a work around so test points will only be exposed >on >the tested side and tented on the untested side (like under fine pitch SMT >components)? >Editing the Gerber's is the only way I know to do this now. :( >I would prefer something that be reproducible after revisions are made. >Any news about a new version coming? > >Sincerely, >Carl Schattke, C.I.D. >Intel Corporation, ACT >Sr. Hardware Engineer ( PCB Design) >122 Saratoga Ave. Suite 100 >Santa Clara, CA 95052 >Office 408-556-3122 >Fax 408-261-5869 >24 Hr. Ph. 888-204-3704 >Email: [EMAIL PROTECTED] > > * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Test point tenting on side opposite TP
The way I do this is to simply plot the soldermask for the side with the testpoints normally, and then select the testpoints, and edit the soldermask expansion for them to be negative, (ex: 30 mil TP gets -15mil expansion) and plot the opposite side to bury them in the mask. Reed Woltering Cad Manager Ariel Corporation At 09:35 AM 7/27/01 -0700, you wrote: >Hello, >Has anyone figured out a work around so test points will only be exposed >on >the tested side and tented on the untested side (like under fine pitch SMT >components)? >Editing the Gerber's is the only way I know to do this now. :( >I would prefer something that be reproducible after revisions are made. >Any news about a new version coming? > >Sincerely, >Carl Schattke, C.I.D. >Intel Corporation, ACT >Sr. Hardware Engineer ( PCB Design) >122 Saratoga Ave. Suite 100 >Santa Clara, CA 95052 >Office 408-556-3122 >Fax 408-261-5869 >24 Hr. Ph. 888-204-3704 >Email: [EMAIL PROTECTED] > > * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Test point tenting on side opposite TP
Carl , What I have done in the past: I have our engineer layout his design with a TESTPOINT symbol on each net. This can be done on each sheet or can be attached as the last page(s) of the schematic. I create a surface mount pad according to my test requirements. The pad will also include a keepout circle drawn on one the mechanical layers so that I can observe the min testpoint to testpoint spacing. I design and route my board first without the TESTPOINTS. Then I load the netlist and now the testpoints points. I move one testpoint at time an locate them on existing vias. and pads only on the side that will be tested. This method has proved flawless for me because I can inspect every testpoint as I am placing them for clearances, and it insures that every testpoint is accessible and can be identified. When you are done generate a Pick and place report , extract the TP data and presto you have every location for testing. And hopefully you meet your test requirements. Feel free to email if you have any questions Mike Reagan EDSI Frederick MD [EMAIL PROTECTED] - Original Message - From: Schattke, Carl <[EMAIL PROTECTED]> To: Protel EDA Forum <[EMAIL PROTECTED]> Sent: Friday, July 27, 2001 12:35 PM Subject: [PEDA] Test point tenting on side opposite TP > Hello, >Has anyone figured out a work around so test points will only be exposed > on > the tested side and tented on the untested side (like under fine pitch SMT > components)? >Editing the Gerber's is the only way I know to do this now. :( > I would prefer something that be reproducible after revisions are made. >Any news about a new version coming? > > Sincerely, > Carl Schattke, C.I.D. > Intel Corporation, ACT > Sr. Hardware Engineer ( PCB Design) > 122 Saratoga Ave. Suite 100 > Santa Clara, CA 95052 > Office 408-556-3122 > Fax 408-261-5869 > 24 Hr. Ph. 888-204-3704 > Email: [EMAIL PROTECTED] > > > * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
