> Joel,
>   Clicking Testpoint just marks it as a testpoint for output, but does not
> even
> automatically untent the via.  So it would allow you to have soldermask on
a
> test point.
> Hum, they might complain about that in the test department.
>    Seems the only solution/work around is create separate components for
the
> top and bottom testpoints and then modify them as needed.  Protels
treatment
> of testpoints leaves something to be desired.
> Perhaps the next version will give us the control we need.  It would be
nice
> to have clearance checking for testpoint to testpoint spacing.  And also
> soldermask control for each side of the board, since you only need access
> from one side, not both.
> Carl

I was wondering why a (testpoint) component had to be designed for each side
of the PCB, as components can be moved from one side of the PCB to the
other. But having said that, the Testpoint properties of pads are *not*
updated whenever a pad is moved to the other side of a PCB, and regardless
of whether a pad is part of a component or otherwise.

Is there anyone who thinks that this behaviour is desirable? I.e. that pads'
Testpoint properties should *not* be updated whenever a pad is moved to the
other side of a PCB. (Maybe the user should be polled as to whether *none*
of the pads and vias being "flipped" have their Testpoint properties
updated, or *all* of these, or whether the user will be polled for *each* of
these.)

Vias are also problematic in this regard. (Although it is less likely for
vias to be incorporated within footprints, this is still possible though.)
And a related issue is what should happen to each via's LowLayer and
HighLayer properties when vias are moved from one side of the PCB to the
other. At present, these don't change, but a case could be made that the
outside layer of all "blind" vias should toggle (even though this could
result in vias using layer pairs which have not been defined by the user).
Comments from other users on this one?

I do not disagree with the concept of enhanced "padstacks" support
(supporting, among other things, through-hole pads and vias having a
soldermask opening on one side of the PCB but not on the other), and I have
advocated this to some extent in the past. But I am also of the view that
this is "can of worms" territory, because of issues as to whether the
desired outcome should be achieved by using Design Rules, or dialog box
entries, or by *either* of those methods. In some ways, the ideal would be
to support either method, but a proper implementation of that approach would
require dialog box entries to "auto-create" corresponding Design Rules, so
that settings for pads and vias can be determined/checked either by viewing
Design Rules or by viewing dialog box contents. But Design Rules could be
problematic when the pads and vias these are applied to are not fully
"identifiable"; if only *some* vias are to be masked on one side only (for
instance), how are these to be identifed (via Design Rule entities)?

Again, comments from others on this matter would be welcomed. (I have
previously suggested that perhaps vias could support a name/designator
property, so that Design Rules could be applied to vias on a selective
basis, the selection criteria being of course based on the name assigned to
each via.)

Regards,
Geoff Harland.
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