ed the KS10 to do computer based IV - a first for DEC.
/Bob Supnik
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Yes, the PDP11 Architecture Handbook was a post-facto effort. The J11
was finished; DEC did not intend to do another PDP11 processor. (I wrote
a spec for one, primarily as an exercise in trying to do a different
microcode structure than the PLA/ROM of the LSI11/F11/J11, but I lost
it.) The
e original.
An interesting project for the do-it-yourselfers on this list.
/Bob Supnik
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Very cool. Is there any way to download the entire set of files at once,
as an archive?
On 6/27/2020 12:00 PM, simh-requ...@trailing-edge.com wrote:
Message: 1
Date: Fri, 26 Jun 2020 17:48:09 +
From: Lars Brinkhoff
To:simh@trailing-edge.com
Subject: [Simh] DG Nova announcement from
...@trailing-edge.com wrote:
Message: 3
Date: Mon, 25 May 2020 09:59:09 -0400
From: Timothe Litt
To:simh@trailing-edge.com
Subject: Re: [Simh] A lost 18b peripheral
Message-ID:
Content-Type: text/plain; charset="utf-8"
On 25-May-20 09:29, Bob Supnik wrote:
Looking through the XVM/MUMPS15 list
Looking through the XVM/MUMPS15 listing, I saw that the timesharing
terminals were attached via a DC01 communications multiplexer. There's
no reference to such a device anywhere in the 18b literature on Bitsavers.
Because the PDP15 is a contemporary of the PDP8/I and the KI10, I
thought it
Before MUMPS-11, there was MUMPS-15. It is the only one of the PDP-15's
DEC operating systems that is still missing. TA PDF assembly listing of
XVM/MUMPS-15 (or perhaps only part of it) exists, but it is scribbled
over in places, as though it were a developer's "in progress" listing.
There's
One of the problems with simulating the non-VLSI VAXen, other than the
780, is that the microcode is not available. Back at DEC, I had the 730
microcode in a huge notebook (it was 16KW), but I discarded it when I
moved out of Hudson and downsized my document collection. We really need
the
And the solution is... a stock RT-11 distribution only has RL drives.
; SYSTEM GENERATION OPTION
.IIF NDF DL$UN, DL$UN == 2;NUMBER OF UNITS SUPPORTED
.IIF GT DL$UN-4, DL$UN == 4;CAN'T HAVE MORE THAN 4 UNITS
.IIF LE DL$UN, DL$UN == 1;CAN'T HAVE NO UNITS
The simulator is doing the right thing. Here's the core of the
formatting routine:
6$: MOV #-1,RKWC(R2) ;SET WORD COUNT TO 1
MOV #RKDATA,RKBA(R2) ;SET BUFFER ADDRESS
MOV #WRTFMT+GO,RKCS(R2) ;ISSUE WRITE FORMAT
7$: BIT
Okay. If I'm going to trace this RK11 FORMAT bug and RL02 init bug, I
need sources (with comments) for some version of RT11 that supports
those devices, like V5.3 or later. Both are probably in DUP, but I'd
need to trace driver code too.
Over the years, I've managed to stockpile sources for
1. I can confirm that RT11 V5.3 INIT does not work properly with an RL02
in 3.10.
My next step is to trace back changes, because I think it used to work.
2. There's no card reader for the SDS 940 because
a) I hate card readers (from having used them way back when)
b) I thought there wouldn't
To my surprise, format is actually mechanized in the RK11 simulator.
Whether it's mechanized correctly is another story, of course.
There are only two tests for the format bit.
1. If FORMAT is set when GO is set, and the command is anything other
than READ or WRITE, then PGE (programming
If the MMU is enabled, the instructions use PSW to compute
the source/destination operand physical address (if memory) or the stack
pointer to use (if SP). If the MMU is off, PSW only matters
if the source/destination operand is SP.
/Bob
On 9/22/2019 12:00 PM, simh-requ...@trailing-edge.com
. DMA devices can see (on the Unibus or the
original Qbus) 18 bits of memory addresses or (on the Q22 bus or a
Unibus system with an IO map) 22 bits of memory addresses.
/Bob Supnik
On 9/21/2019 8:24 PM, simh-requ...@trailing-edge.com wrote:
Message: 2
Date: Sat, 21 Sep 2019 19:49:39 -0400
From
Well, no. It's a PDP-8/A as initially released and documented in the
late 1976 PDP-8/A manuals and schematics. That machine was limited to
32KW. So was the initial, 1976 version of the FPP8-A.
The KT8-A was released in mid 1978. It expanded memory capability to
128KW and added a number of
As was pointed out, the existing PDP-8 CPU is basically a PDP-8/E or
-8/A. It doesn't have the model-specific capabilities of the current
PDP-11 CPU simulator.
Making the PDP-8 "model specific" is a bit more difficult than just
putting in model tests at various points in the CPU. The
Great job, Rich, and congratulations.
Maybe we'll have 4S72 (or whatever it was called), the first version of
TOPS-10 I ever used...
/Bob
On 7/10/2019 12:00 PM, simh-requ...@trailing-edge.com wrote:
Message: 2
Date: Wed, 10 Jul 2019 07:29:14 -0400
From: Richard Cornwell
The PLA scheme (another invention from the fertile mind of Bill Roberts,
architect of the LSI11 and UDA50 proto and founder of Emulex) was
basically a microcode and gate conservation scheme. It provided enormous
compression for the decode phase of the PDP11 and then got exploited to
a
-edge.com
Subject: Re: [Simh] Which PDP-11 to choose
Message-ID:<7wblydbv9t@junk.nocrew.org>
Content-Type: text/plain
Bob Supnik wrote:
The J-11 based simulators (11/73 and up) are the only ones that were
verified against actual machine microcode.
Speaking of which. Someone claime
If I may interject a serious note...
The J-11 based simulators (11/73 and up) are the only ones that were
verified against actual machine microcode. The 11/73 system was the only
one verified against its board and system specification. The others are
all derivatives.
I always debug with the
As I suspected, RP class drives (except the RP07) have 4 words of
header, and RM class drives have 2. This is confirmed by the RSTS/E disk
initialization code. RSTS/E can't format an RP07, so I can't verify how
those functions ought to work. RSTS/E seems to think it has 2 words of
header,
I don't think it's that straightforward. The write header and data
command must include the proper Massbus word count for header and data.
The Unibus side of the RH11 is doing 18b transfers, and so is the disk
side, so the word count ought to be 260 for an RP and 258 for an RM.
If the
Implementing a more complete form of read/write/write check header is
not as straightforward as I thought, because the RP and RM drives use
different header formats.
The RP expects 4 16 bit words, of which the first two are used, and the
second are "for software". Word 0 is cylinder plus
You're quite right. Rolm is not Rohm & Haas. The Rolm MIMIC simulator
was in the same box of ADR listings as a tensile tester package
developed for Rohm & Hass, and I got the names confused.
On 6/26/2019 12:00 PM, simh-requ...@trailing-edge.com wrote:
Message: 4
Date: Wed, 26 Jun 2019
too...
/Bob
On 6/25/2019 8:49 PM, Henry Bent wrote:
On Tue, 25 Jun 2019 at 20:41, Bob Supnik <mailto:b...@supnik.org>> wrote:
Rolm & Haas made a militarized Nova-compatible minicomputer called
the
1602 - a follow on to their 1601 Ruggednova system. It ha
Rolm & Haas made a militarized Nova-compatible minicomputer called the
1602 - a follow on to their 1601 Ruggednova system. It had an extended
instruction set. I know this because I found the listings for the PDP10
based 1602 simulator in my attic tonight. I've never seen any other
I like Johnny's suggestion.
1. On write header, "eat" the two header words and then write normal data.
2. On read header, synthesize the two standard header words and then
read the pack data.
3. On write check header, skip the first two (header) words and then do
a normal write check.
This
or 9" RA9X series, which used the RA8X radial
interconnect. ST504 was eventually replaced by SCSI (and later its
clusterable proprietary variant, DSSI).
/Bob
On 6/25/2019 7:22 PM, Robert Armstrong wrote:
Bob Supnik [b...@supnik.org] wrote:
Ah, yes, the Interconnect Task Force. 1980,
ning wrote:
On Jun 25, 2019, at 11:43 AM, Bob Supnik wrote:
True. My first assignment at DEC was managing the "New Disk Subsystem" (NDS)
advanced development project, which led eventually to both the HSC50 and the UDA50. Among
the goals of the project were
1. To move ECC correction
True. My first assignment at DEC was managing the "New Disk Subsystem"
(NDS) advanced development project, which led eventually to both the
HSC50 and the UDA50. Among the goals of the project were
1. To move ECC correction off the host and into the disk subsystem, so
that much more powerful
The four ports is not arbitrary. SimH simulates actual hardware. DEC
never built a backplane MSCP controller with more than four ports.
If you want to extend the current RQ simulator to include third party
boards (either SMD-based emulators or SCSI-based emulators), feel free
to add an
The simh.trailing-edge.com web site is for my personal branch, 3.10; it
says so, right at the top of the home page.
I have updated the link for FAQ to point to the PDF file and added a
disclaimer at the top of the help page that this is for 3.10.
/Bob Supnik
On 5/10/2019 11:37 AM, simh-requ
If you're talking about the NVAX chip and its derivative systems,
including the 6600 and 7000, the answer is, no, it doesn't support a 34b
physical address space. NVAX has a 32b physical address space. Despite a
25b page frame number (PFNs) in the PTE, the translation buffer has only
23b for
t for Matt's 8200
RXCD code. Anyone attempting implementation of further models (or VAX
vectors) should be aware of this new capability.
/Bob Supnik
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The 8200 (V11) doesn't have a console processor; the console is
implemented in microcode (as in the F11/J11) and some macrocode (as in
MicroVAX II). That's one of the reasons the V11's microstore was 15KW,
plus a 1 KW patch store, and MicroVAX II's was 1.6KW, with no patch
store. (The other
Jim,
Congratulations - a great piece of work bringing some distant hardware
and software back from the Land of the Lost.
/Bob Supnik
On 12/19/2018 12:00 PM, simh-requ...@trailing-edge.com wrote:
Message: 1
Date: Tue, 18 Dec 2018 21:33:59 -0700
From: "J Bevier"
To:
Subject: [Sim
ntent-Type: text/plain; charset=utf-8; format=flowed
Bob Supnik schreef op 15-12-2018 om 23:44:
[snip]
So I'd like to see what the behavior is the clock file
attached.
Or you can post a pointer to the disk image you're using, and I'll try
it on 3.10. I saw the ELN kits on 9track.net, but I
My question is... how does the TODR get reset from the value read by the
ROM to the ELN value with no intervening write? Did it wrap around?
Seems unlikely; it shouldn't wrap around before next year.
I suspect it's the "OS agnostic mode" that was added in 4.X. According
to the writeup,
.
for the block
addresses, which is not necessarily based on geometry.
/Bob Supnik
On 9/25/2018 12:00 PM, simh-requ...@trailing-edge.com wrote:
Message: 3
Date: Tue, 25 Sep 2018 09:53:04 -0400
From: Paul Koning
To: Folkert van Heusden
Cc:simh@trailing-edge.com
Subject: Re: [Simh] disk file format
SimH mirrors the behavior of the J11.
The J11 uses a pair of indirect register references labeled 'rsrc' and
'rsrc+1', but as the microcode definitions make clear, rsrc+1 is
actually rsrc OR 1. So if an odd source register is specified, the
dividend is two copies of the same register.
/Bob
-0400
From: Bob Supnik
To: Christopher Trumbour
I do not have F-11 specs; it was designed before my time in the Semi Group.
You could try the Computer History Museum in Mountain View, CA, which
has an extensive archive of DEC material.
/Bob
On 8/30/2018 10:05 PM, Christopher Trumbour
Hauser's SoftFloat to be of more interest, as it is
very general and implements every possible useless goodie of the
standard as is existed in the 20th century. It does not have the fifth
rounding mode that was added more recently, but the chips of that era
wouldn't have it either.
Bob Supnik
any point in adding it.
- If you want to improve the fidelity of the simulation a bit, the "4M"
memory size setting could be adjusted to 3840 vs 4088, for U vs Q, in
the cpu_set_size routine.
/Bob Supnik
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It's not a quirk, it's a design feature.
The PDP11 simulator didn't start out as a generalized, all-singing,
all-dancing emulation of all possible PDP11 models; it started as a J11
and PDP-11/73 simulator - one processor type, one system, Qbus only. In
the same way, the VAX didn't start out
Looking at the DEC ChipKit documentation, it seems fairly clear that a
device implemented with the DC003/5/6/10/21 series of chips never drives
BBS7. BBS7 is an input to the address matching logic implemented in the
DC005, but that's it.
On the other hand, the DEC Standard for the LSI11 bus
Apparently, the GT40 does this. So... problems.
1. The original simulator I wrote didn't support DMA to IO space. Code
for this was added in V4, but the code conformed to the internal
simulator convention that all addresses are 22b wide. This is certainly
not the case for Unibus DMA devices;
Baka me. Included the useless init file instead of the pirex.bin file.
Fixed.
Redownload xvmdos_uc15.zip.
/Bob
On 7/18/2018 8:07 PM, simh-requ...@trailing-edge.com wrote:
Message: 5
Date: Wed, 18 Jul 2018 19:49:15 -0400
From: Christian Gauger-Cosgrove
To: SIMH
Subject: [Simh] XVM/DOS Kits
The UC15 is an 11/05 with part of its address space mapped into PDP15
memory, and a small amount private. It allows bidirectional writes.
There is also a control link, basically two parallel interfaces tied
together.
The key difference with the Rubin 10-11 is that the PDP15 does not
access
, 2018, at 2:16 PM, Bob Supnik <b...@supnik.org> wrote:
At long last, I've finished testing the PDP15/UC15 combination, and it works well enough
to run a full XVM/DOS-15 sysgen. I've sent an "RC1" package to Mark fP. or
trial integration.
The configuration consists of two sep
3.10 is ready to go, I'll post it on the SimH web site, along with
a design paper about the UC15 configuration, and additional instructions
for running XVM/DOS-15 in a UC15 configuration.
/Bob Supnik
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htt
SimH's intended purpose was to run historical software in furtherance of
computer education. It was not intended as a perfectly accurate
emulation of every detail of every architecture. There are compromises
in the design to simplify implementation.
One of those, dating back to its
The original DZ emulator was originally written by a contributor. He
chose a model whereby lines were not explicitly represented by units. In
fact, even multiple controllers were not explicitly represented. This
model was followed in some other emulators, such as the DHU/V11 and the
NOVA QTY.
pe reader comes from the device simulator not having
any code to write to the associated file. If you want to block DEPOSIT,
then what you suggest is the correct course of action.
/Bob
On 3/25/2018 8:08 PM, Paul Koning wrote:
On Mar 25, 2018, at 7:23 PM, Bob Supnik <b...@supnik.org> wrote:
Mark Pizzolato pointed out that UNIT_RO is cleared unconditionally at
DETACH. This makes static declaration of a unit as UNIT_RO impossible.
He has proposed a change to distinguish a "static" read-only unit
(UNIT_RO set but not UNIT_ROABLE) from the usual "dynamic" read-only,
set by ATTACH -R
Zork (Dungeon) for VAX/VMS is available here:
http://simh.trailing-edge.com/games/dungeon.zip
The sources to Adventure (VAX/VMS version) are also online, as is the MDL
source for Zork. I have the PDP-11 version of Adventure as well.
/Bob
On 2/11/2018 1:22 PM, simh-requ...@trailing-edge.com
SPEAK got banged up a lot during the conversion to the PDP-11, because
of the difference in word width, but the relevant fragment is:
5 TYPE 2,(LINES(I),I=1,L)
2 FORMAT(' ',36A2)
This is still 1977-78, but the PDP-11 Fortran compilers (both F4 and
F77) adhered to the 'standard' for
Yes, in separate processes. They use shared memory sections to
communicate - one as main memory, one as control state.
/Bob
On 1/18/2018 12:26 PM, Lars Brinkhoff wrote:
Hello,
Thanks, that's good to know. It's encouraging that something is
underway.
Are the machines running inside the same
Lars,
SimH knows nothing of the internal structure of simulators, so I'm
skeptical of a SimH-level solution. However, a simulator-specific
interface can be built.
As an example, I am finishing up the UC15, which is exactly what you
describe - a PDP11 that is connected to the memory of a
,
/Bob SUpnik
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a look at what's happening.
/Bob Supnik
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Found a good block diagram in the Training Print Set. There was a unique
T11-based CPU that talked to the Cbus on one side and a Qbus on the
other. Local storage was an RL02.
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-0400
From: Guy Fedorkow <guy.fedor...@gmail.com>
To: Bob Supnik <b...@supnik.org>
hi Bob,
I'm continuing to explore the Whirlwind world, one tiny step at a time.
I thought I'd look around for retargetable cross-assemblers and
disassemblers that might work with the machine's
The expansion capability of the VT100 was used for all kinds of
interesting purposes.
The T11 (the one-chip micro intended to replace the LSI11 and F11 in
embedded applications) didn't generate a lot of buzz inside DEC, so the
team sponsored a "design contest" to spur usage. I'd never done
From page 6-6 of DEC STD 032 (the VAX architecture spec): "Execution of
MTPR src, #PR$_ASTLVL with src<31:0> GEQU 5 results in UNDEFINED
behavior. The preferred implementation is to cause a reserved operand
fault." MicroVAX II, CVAX, and Rigel all conform to the preferred
behavior, as does the
You can get a pre-built Windows 32b 3.9 executable without Ethernet (and
therefore, without needing WinPCap) here:
http://simh.trailing-edge.com/sources/simhv39-0-exe.zip. It should run
fine under W10. See if it will boot NetBSD 5.1.
/Bob Supnik
On 4/18/2017 3:53 PM, simh-requ...@trailing
There's an almost total lack of 8200 (aka V-11 or Scorpio) documentation
on the web. I have chip pictures
(http://simh.trailing-edge.com/semi/v11.html), and I think the chip
specs (which won't help much) are in my archive at the Computer History
Museum. Here are some things to be aware of:
Well, I didn't have to ask for it, because I had it... ;) Without it,
though, I could not have gotten the minute differences between the J-11
and the other PDP-11s correct.
In general, I am no longer a fan of "approximate" simulations. If you
just use the spec and ignore the implementation,
The HSC family offered a superset of capabilities compared to the
UDA50/QDA50. In particular,
- tape as well as disk support (TMSCP as well as MSCP);
- controller-based disk to tape backups and tape to disk restores;
- controller-based disk to disk duplication;
- controller-based volume
Sorry, replied to the wrong email.
On 2/22/2017 12:00 PM, simh-requ...@trailing-edge.com wrote:
Send Simh mailing list submissions to
simh@trailing-edge.com
To subscribe or unsubscribe via the World Wide Web, visit
http://mailman.trailing-edge.com/mailman/listinfo/simh
or, via
If you do want to use different timing, then global variable sim_step is
available with the current step count (0 means not stepping) at entry to
sim_instr. sim_step isn't deliberately global; it just works out that
way. Further, it is NOT maintained as the step count is counted down.
a pointer.
Thanks,
/Bob Supnik
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ETOS was not a DEC product. I don't know what its terms and conditions are.
DEC made all its PDP8 and PDP15 software into freeware at some point,
after the last systems had been out of production for years and years,
but I have no idea where there is any supporting paperwork.
On 1/14/2017
Simulators should never fix "bugs". The question at issue is how deeply
to mimic them, in order to assure maximum compatibility with software.
Over the years, I've concluded that straying too far from the hardware
is dangerous. I'm not suggesting that every register-transfer-level
interaction
I'm not sure there are any "non-quirky" standard operating conditions,
unless they were unpredictable from system to system. For example, the
implementation of interrupts on the RH series Massbus adapters is truly
broken, but it has to be simulated accurately, or the workaround in the
Unix
Josh Dersch at the Living Computer Museum found a snippet of real
DECtape code (that runs on a real 11/40) which fails on the simulator.
After looking at the snippet, and at the TC11 schematics, I realized
that the TC11 simulator had a basic design problem. The TC11 is not, in
fact, a
It is. Great detective work. Thanks.
/Bob Supnik
On 11/5/2016 5:15 AM, simh-requ...@trailing-edge.com wrote:
Message: 1
Date: Fri, 4 Nov 2016 20:52:33 -0700
From: Pascal Parent<pascg...@gmail.com>
To:simh@trailing-edge.com
Subject: Re: [Simh] TOPS-20 4.1 Cobol 12c Sample test failure
M
Mark,
Dave Bryan and I are trying to work out the kinks in the 'erase'
function on the 940, which is needed to make the tape file system work.
Dave has implemented precise in-place erase for records, but we'll need
a precise erase for file marks too. And then the whole thing has to be
I know of at least the following additional assembly language operating
systems that have sources, mostly on Bitsavers:
1. OS/8 - PDP-8 assembly language
2. XVM/DOS-15 - PDP-15 assembly language
3. CAPS-11 - PDP-11 assembly language
4. TSS/8 - PDP-8 assembly language
5. ADSS-9/15 - PDP-9/15
It works on the current 3.X build under Windows.
Have you verified that it works on 4.0 on an x86?
On 10/17/2016 12:00 PM, simh-requ...@trailing-edge.com wrote:
Re: 1401 and arm processors (Mark Pizzolato)
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Another issue with the 750, 730, and 8600 is that they are not as exact
at the 780 and CVAX simulators, because certain critical documents
(microcode, some subsystem specifications, some schematics) are not
available. For example, the 750's simulated Massbus and Unibus adapters
started out as
Per the earlier discussion, I have modified the PDP8's additional
terminal capability to support 16 lines. I'm testing it now and will
upload it when it has been wrung out.
In an earlier post, I provided a list of device numbers. The last (16th
device) was incorrect. The table should be:
The PDP-5 is, in fact, not all that compatible, because it used memory
location 0 as the PC, pushing the interrupt locations to 1/2, instead of
0/1. So any program requiring interrupts will not work on a -5 vs an -8.
The PDP-5 had an IO halt/restart facility, modeled on the PDP-1 and
dropped
More limitations: the PDP8 interrupts are laid out in a single 32b word.
There isn't room to have an additional 12*2 = 24 interrupts; the word is
almost full.
If anyone wants to try this, I suggest looking at the PDP15
implementation, which supports 16 (or more) lines. It already has the
Yeah, sorry. It is a single line. The simulator treats all of them as a
single device.
The limit of 4 lines comes from the (current) limit of 8 device
addresses per device (in pdp8_defs.h). Further, the simulator assumes
that the device addresses within a device are contiguous, and the
You can override the default value of delete with
SET CONSOLE DEL=interpret ASCII code value as DELETE
The value is radix 16 on hex machines, and radix 8 on everything else.
/Bob
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DEC didn't make much investment in error detection for its paper tape
equipment. In the 18b family, the PDP-9 was the first 18-bit system to
feature a "reader empty" flag. The PDP-8 never had one. (The PDP-11 had
one from the get go.)
That begs the question of what these early PDP's did when
There are any number of strange-length divide algorithms in SimH. Here
is the PDP-10 code for dividing a 70b unsigned integer by a 35b
(unsigned) integer.
// dvd[0:1] = 70b dividend, high order first (35b in each word)
// dvr = 35b divisor
// rs[0:1] = quotient remainder
// all variables
A really valuable tutorial. It's also the first proof that the LGP30
simulator sort-of works; I'm relieved.
Shoehorning the LGP30's operating procedures into SimH's default syntax
was difficult. It might have been better to use the 'simulator-defined
command' capability to create a set of
Please see the SimH web site
(http://simh.trailing-edge.com/software.html) for examples of kits to
run on SimH simulators. This works better for simple, stand-alone
applications that for full operating systems with layered products
installed, some of which (like VMS) require licenses and media
harset=utf-8
On 5/26/16 5:29 PM, Al Kossow wrote:
>
>
>On 5/26/16 1:46 PM, Bob Supnik wrote:
>>I didn't know of any surviving software
>
>look on bitsavers for docs and software, unless I forgot to upload it.
>
I just looked, and I haven't put up the floppy images
There
to do. I didn't know of any surviving software, either (except
now DoD's), so there was never any real motivation to work on an
emulator. Perhaps DoD would like to sponsor one . ;)
/Bob Supnik
**
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There is a proposed card reader library (not mine) in the GitHub
repository, which you could try.
On the 1401, the handling is as follows:
1. The card reader buffer is 2*CBUFSIZE + 1, where CBUFSIZE is an
internal SimH constant for buffer size. The buffer is zeroed before a read.
2. The card
of Unix "v0" (PDP-7 Unix). But there's always
more to do.
/Bob Supnik
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Upstate Medical Center in Syracuse had a number of PDP-15s, including
XVMs. Some are still be in the hands of a private collector. However,
that person is unwilling to share materials, particularly software kits,
from his collection.
If the RP disks follow normal SimH practice, then they are
With the restoration of PDP7 Unix coming along nicely, how about a PDP7
hardware emulator and front panel so that everyone can have their own
"unix v0"? Dave Conroy did a PDP4 emulator in an FPGA
(http://fpgaretrocomputing.org/pdp4x/) that includes the EAE, so there's
a good starting point.
It took some research, but I've regained access to the SimH website.
When I return in mid-May from a trip, I'll be updating the website's
papers and software kits, which have been frozen for a year.
As is the case now, GitHub remains the official source for SimH sources,
whether on the older
files into IBSYS job decks and turn IBSYS output magtapes into text
files, as well as a generalized command procedure for running jobs.
If the file transfer issue is not addressed to your satisfaction in a
particular simulated environment, then take it up with the developer or
maintainer of that
Amen!
If you're trying to transfer files to or from a simulator, then think
about how it was done /on the real machine/. There's almost always a
solution, for any given simulator/OS pair.
For systems from the 50s and 60s, it's punched cards, which are usually
simulated as ASCII text files.
Sigh... just looked through ka630_* modules.
Anyway, the byte access/word addressing is in the spec. So the code is
allowing writes to bytes that don't exist. Further, it is trying to deal
with lengths other than byte or word, and the access and control paths
don't exist in the hardware.
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