CVS commit: src/sys/arch/x86/include
Module Name:src
Committed By: msaitoh
Date: Sat Jul 10 17:08:37 UTC 2021
Modified Files:
src/sys/arch/x86/include: specialreg.h
Log Message:
Add some definitions from Intel SDM:
- CPUID leaf 7:0 %ecx bit 13 TME_EN (Total Memory Encryption)
- CPUID leaf 7:0 %edx bit 18 PCONFIG (Platform CONFIGuration)
To generate a diff of this commit:
cvs rdiff -u -r1.176 -r1.177 src/sys/arch/x86/include/specialreg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/include/specialreg.h
diff -u src/sys/arch/x86/include/specialreg.h:1.176 src/sys/arch/x86/include/specialreg.h:1.177
--- src/sys/arch/x86/include/specialreg.h:1.176 Tue Nov 24 00:46:28 2020
+++ src/sys/arch/x86/include/specialreg.h Sat Jul 10 17:08:37 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: specialreg.h,v 1.176 2020/11/24 00:46:28 msaitoh Exp $ */
+/* $NetBSD: specialreg.h,v 1.177 2021/07/10 17:08:37 msaitoh Exp $ */
/*
* Copyright (c) 2014-2020 The NetBSD Foundation, Inc.
@@ -458,6 +458,7 @@
#define CPUID_SEF_VPCLMULQDQ __BIT(10)
#define CPUID_SEF_AVX512_VNNI __BIT(11) /* Vector neural Network Instruction */
#define CPUID_SEF_AVX512_BITALG __BIT(12)
+#define CPUID_SEF_TME_EN __BIT(13) /* Total Memory Encryption */
#define CPUID_SEF_AVX512_VPOPCNTDQ __BIT(14)
#define CPUID_SEF_LA57 __BIT(16) /* 57bit linear addr & 5LVL paging */
#define CPUID_SEF_MAWAU __BITS(21, 17) /* MAWAU for BND{LD,ST}X */
@@ -473,7 +474,7 @@
"b\0PREFETCHWT1\0" "b\1AVX512_VBMI\0" "b\2UMIP\0" "b\3PKU\0" \
"b\4OSPKE\0" "b\5WAITPKG\0" "b\6AVX512_VBMI2\0" "b\7CET_SS\0" \
"b\10GFNI\0" "b\11VAES\0" "b\12VPCLMULQDQ\0" "b\13AVX512_VNNI\0"\
- "b\14AVX512_BITALG\0" "b\16AVX512_VPOPCNTDQ\0" \
+ "b\14AVX512_BITALG\0" "b\15TME_EN\0" "b\16AVX512_VPOPCNTDQ\0" \
"b\20LA57\0" \
"f\21\5MAWAU\0" "b\26RDPID\0" "b\27KL\0" \
"b\31CLDEMOTE\0" "b\33MOVDIRI\0" \
@@ -490,6 +491,7 @@
#define CPUID_SEF_SERIALIZE __BIT(14) /* SERIALIZE instruction */
#define CPUID_SEF_HYBRID __BIT(15) /* Hybrid part */
#define CPUID_SEF_TSXLDTRK __BIT(16) /* TSX suspend load addr tracking */
+#define CPUID_SEF_PCONFIG __BIT(18) /* Platform CONFIGuration */
#define CPUID_SEF_CET_IBT __BIT(20) /* CET Indirect Branch Tracking */
#define CPUID_SEF_IBRS __BIT(26) /* IBRS / IBPB Speculation Control */
#define CPUID_SEF_STIBP __BIT(27) /* STIBP Speculation Control */
@@ -503,7 +505,7 @@
"\5" "FSREP_MOV" \
"\11VP2INTERSECT" "\12SRBDS_CTRL" "\13MD_CLEAR" \
"\16TSX_FORCE_ABORT" "\17SERIALIZE" "\20HYBRID" \
- "\21" "TSXLDTRK" \
+ "\21" "TSXLDTRK" "\23" "PCONFIG" \
"\25" "CET_IBT" \
"\33" "IBRS" "\34" "STIBP" \
"\35" "L1D_FLUSH" "\36" "ARCH_CAP" "\37CORE_CAP" "\40" "SSBD"
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: christos Date: Fri Apr 30 15:37:06 UTC 2021 Added Files: src/sys/arch/x86/include: gdt.h Log Message: merge the i386 and amd64 gdt.h files. To generate a diff of this commit: cvs rdiff -u -r0 -r1.1 src/sys/arch/x86/include/gdt.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Added files: Index: src/sys/arch/x86/include/gdt.h diff -u /dev/null src/sys/arch/x86/include/gdt.h:1.1 --- /dev/null Fri Apr 30 11:37:06 2021 +++ src/sys/arch/x86/include/gdt.h Fri Apr 30 11:37:05 2021 @@ -0,0 +1,67 @@ +/* $NetBSD: gdt.h,v 1.1 2021/04/30 15:37:05 christos Exp $ */ + +/*- + * Copyright (c) 1996, 1997 The NetBSD Foundation, Inc. + * All rights reserved. + * + * This code is derived from software contributed to The NetBSD Foundation + * by John T. Kohl and Charles M. Hannum. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + *notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + *notice, this list of conditions and the following disclaimer in the + *documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _X86_GDT_H_ +#define _X86_GDT_H_ + +#if !defined(_LOCORE) + +struct cpu_info; +void gdt_init(void); +void gdt_init_cpu(struct cpu_info *); +void gdt_alloc_cpu(struct cpu_info *); + +#ifdef _LP64 +struct x86_64_tss; +int tss_alloc(struct x86_64_tss *); +#else +struct i386tss; +int tss_alloc(const struct i386tss *); +#endif + +void tss_free(int); +int ldt_alloc(void *, size_t); +void ldt_free(int); + +#endif /* LOCORE */ + + +#ifndef MAXGDTSIZ +# define MAXGDTSIZ 65536 /* XXX: see */ +#endif + +#ifndef MAX_USERLDT_SIZE +# define MAX_USERLDT_SIZE 65536 /* XXX: see */ +#endif + +#define MAX_USERLDT_SLOTS (int)(MAX_USERLDT_SIZE / sizeof(union descriptor)) + +#endif /* _X86_GDT_H_ */
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: nonaka Date: Thu Mar 18 01:50:12 UTC 2021 Modified Files: src/sys/arch/x86/include: intrdefs.h Log Message: LIR_HV priority should be lower than softint. To generate a diff of this commit: cvs rdiff -u -r1.24 -r1.25 src/sys/arch/x86/include/intrdefs.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/x86/include/intrdefs.h diff -u src/sys/arch/x86/include/intrdefs.h:1.24 src/sys/arch/x86/include/intrdefs.h:1.25 --- src/sys/arch/x86/include/intrdefs.h:1.24 Sat Apr 25 15:26:18 2020 +++ src/sys/arch/x86/include/intrdefs.h Thu Mar 18 01:50:12 2021 @@ -1,4 +1,4 @@ -/* $NetBSD: intrdefs.h,v 1.24 2020/04/25 15:26:18 bouyer Exp $ */ +/* $NetBSD: intrdefs.h,v 1.25 2021/03/18 01:50:12 nonaka Exp $ */ #ifndef _X86_INTRDEFS_H_ #define _X86_INTRDEFS_H_ @@ -27,7 +27,6 @@ */ #define LIR_IPI 31 #define LIR_TIMER 30 -#define LIR_HV 29 /* * XXX These should be lowest numbered, but right now would @@ -35,11 +34,12 @@ * means that soft interrupt take priority over hardware * interrupts when lowering the priority level! */ -#define SIR_SERIAL 28 -#define SIR_NET 27 -#define SIR_BIO 26 -#define SIR_CLOCK 25 -#define SIR_PREEMPT 24 +#define SIR_SERIAL 29 +#define SIR_NET 28 +#define SIR_BIO 27 +#define SIR_CLOCK 26 +#define SIR_PREEMPT 25 +#define LIR_HV 24 #define SIR_XENIPL_HIGH 23 #define SIR_XENIPL_SCHED 22 #define SIR_XENIPL_VM 21
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: kre Date: Thu Jan 21 09:50:37 UTC 2021 Modified Files: src/sys/arch/x86/include: bus_defs.h Log Message: PRIx (etc) definitions should not include the % Will fix anything this ends up breaking later. To generate a diff of this commit: cvs rdiff -u -r1.5 -r1.6 src/sys/arch/x86/include/bus_defs.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/x86/include/bus_defs.h diff -u src/sys/arch/x86/include/bus_defs.h:1.5 src/sys/arch/x86/include/bus_defs.h:1.6 --- src/sys/arch/x86/include/bus_defs.h:1.5 Thu Nov 14 16:23:52 2019 +++ src/sys/arch/x86/include/bus_defs.h Thu Jan 21 09:50:37 2021 @@ -1,4 +1,4 @@ -/* $NetBSD: bus_defs.h,v 1.5 2019/11/14 16:23:52 maxv Exp $ */ +/* $NetBSD: bus_defs.h,v 1.6 2021/01/21 09:50:37 kre Exp $ */ /*- * Copyright (c) 1996, 1997, 1998, 2001 The NetBSD Foundation, Inc. @@ -86,8 +86,8 @@ typedef paddr_t bus_addr_t; typedef size_t bus_size_t; #define PRIxBUSADDR PRIxPADDR -#define PRIxBUSSIZE "%zx" -#define PRIuBUSSIZE "%zu" +#define PRIxBUSSIZE "zx" +#define PRIuBUSSIZE "zu" struct bus_space_tag; typedef struct bus_space_tag *bus_space_tag_t;
CVS commit: src/sys/arch/x86/include
Module Name:src
Committed By: msaitoh
Date: Tue Nov 24 00:46:28 UTC 2020
Modified Files:
src/sys/arch/x86/include: specialreg.h
Log Message:
Add some definitions from the latest Intel SDM:
- Add CPUID leaf 7 %edx bit 23 "KL" (Key Locker).
- Add CPUID leaf 7 subleaf 1 %eax bit 5 "AVX512_BF16".
To generate a diff of this commit:
cvs rdiff -u -r1.175 -r1.176 src/sys/arch/x86/include/specialreg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/include/specialreg.h
diff -u src/sys/arch/x86/include/specialreg.h:1.175 src/sys/arch/x86/include/specialreg.h:1.176
--- src/sys/arch/x86/include/specialreg.h:1.175 Mon Sep 7 13:19:20 2020
+++ src/sys/arch/x86/include/specialreg.h Tue Nov 24 00:46:28 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: specialreg.h,v 1.175 2020/09/07 13:19:20 jakllsch Exp $ */
+/* $NetBSD: specialreg.h,v 1.176 2020/11/24 00:46:28 msaitoh Exp $ */
/*
* Copyright (c) 2014-2020 The NetBSD Foundation, Inc.
@@ -395,9 +395,12 @@
* %ebx: Feature bits.
* %ecx: Feature bits.
* %edx: Feature bits.
+ *
+ * %ecx == 1: Structure Extendede Feature Enumeration Sub-leaf
+ * %eax: See below.
*/
-/* %ebx */
+/* %ecx = 0, %ebx */
#define CPUID_SEF_FSGSBASE __BIT(0) /* {RD,WR}{FS,GS}BASE */
#define CPUID_SEF_TSC_ADJUST __BIT(1) /* IA32_TSC_ADJUST MSR support */
#define CPUID_SEF_SGX __BIT(2) /* Software Guard Extensions */
@@ -441,7 +444,7 @@
"\31" "CLWB" "\32" "PT" "\33" "AVX512PF" "\34" "AVX512ER" \
"\35" "AVX512CD""\36" "SHA" "\37" "AVX512BW" "\40" "AVX512VL"
-/* %ecx */
+/* %ecx = 0, %ecx */
#define CPUID_SEF_PREFETCHWT1 __BIT(0) /* PREFETCHWT1 instruction */
#define CPUID_SEF_AVX512_VBMI __BIT(1) /* AVX-512 Vector Byte Manipulation */
#define CPUID_SEF_UMIP __BIT(2) /* User-Mode Instruction prevention */
@@ -459,6 +462,7 @@
#define CPUID_SEF_LA57 __BIT(16) /* 57bit linear addr & 5LVL paging */
#define CPUID_SEF_MAWAU __BITS(21, 17) /* MAWAU for BND{LD,ST}X */
#define CPUID_SEF_RDPID __BIT(22) /* RDPID and IA32_TSC_AUX */
+#define CPUID_SEF_KL __BIT(23) /* Key Locker */
#define CPUID_SEF_CLDEMOTE __BIT(25) /* Cache line demote */
#define CPUID_SEF_MOVDIRI __BIT(27) /* MOVDIRI instruction */
#define CPUID_SEF_MOVDIR64B __BIT(28) /* MOVDIR64B instruction */
@@ -471,12 +475,11 @@
"b\10GFNI\0" "b\11VAES\0" "b\12VPCLMULQDQ\0" "b\13AVX512_VNNI\0"\
"b\14AVX512_BITALG\0" "b\16AVX512_VPOPCNTDQ\0" \
"b\20LA57\0" \
- "f\21\5MAWAU\0" \
- "b\26RDPID\0" \
+ "f\21\5MAWAU\0" "b\26RDPID\0" "b\27KL\0" \
"b\31CLDEMOTE\0" "b\33MOVDIRI\0" \
"b\34MOVDIR64B\0" "b\36SGXLC\0" "b\37PKS\0"
-/* %edx */
+/* %ecx = 0, %edx */
#define CPUID_SEF_AVX512_4VNNIW __BIT(2)
#define CPUID_SEF_AVX512_4FMAPS __BIT(3)
#define CPUID_SEF_FSREP_MOV __BIT(4) /* Fast Short REP MOV */
@@ -505,6 +508,10 @@
"\33" "IBRS" "\34" "STIBP" \
"\35" "L1D_FLUSH" "\36" "ARCH_CAP" "\37CORE_CAP" "\40" "SSBD"
+/* %ecx = 1, %eax */
+#define CPUID_SEF_AVX512_BF16 __BIT(5)
+#define CPUID_SEF1_FLAGS_A "\20" \
+"\6" "AVX512_BF16"
/*
* Intel CPUID Architectural Performance Monitoring Fn000a
*
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: bouyer Date: Sun Nov 15 13:59:42 UTC 2020 Modified Files: src/sys/arch/x86/include: machdep.h Log Message: remove unused x86_cpu_initclock_func() To generate a diff of this commit: cvs rdiff -u -r1.10 -r1.11 src/sys/arch/x86/include/machdep.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/x86/include/machdep.h diff -u src/sys/arch/x86/include/machdep.h:1.10 src/sys/arch/x86/include/machdep.h:1.11 --- src/sys/arch/x86/include/machdep.h:1.10 Sat Apr 25 15:26:18 2020 +++ src/sys/arch/x86/include/machdep.h Sun Nov 15 13:59:42 2020 @@ -1,4 +1,4 @@ -/* $NetBSD: machdep.h,v 1.10 2020/04/25 15:26:18 bouyer Exp $ */ +/* $NetBSD: machdep.h,v 1.11 2020/11/15 13:59:42 bouyer Exp $ */ /* * Copyright (c) 2000, 2007 The NetBSD Foundation, Inc. * All rights reserved. @@ -53,7 +53,6 @@ void x86_cpu_idle_set(void (*)(void), co extern u_long x86_rtclock_tval; extern void (*x86_initclock_func)(void); -extern void (*x86_cpu_initclock_func)(void); void x86_dummy_initclock(void);
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: jakllsch Date: Mon Sep 7 13:19:20 UTC 2020 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: Fix printb string for LA57 To generate a diff of this commit: cvs rdiff -u -r1.174 -r1.175 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/x86/include/specialreg.h diff -u src/sys/arch/x86/include/specialreg.h:1.174 src/sys/arch/x86/include/specialreg.h:1.175 --- src/sys/arch/x86/include/specialreg.h:1.174 Mon Sep 7 03:03:09 2020 +++ src/sys/arch/x86/include/specialreg.h Mon Sep 7 13:19:20 2020 @@ -1,4 +1,4 @@ -/* $NetBSD: specialreg.h,v 1.174 2020/09/07 03:03:09 msaitoh Exp $ */ +/* $NetBSD: specialreg.h,v 1.175 2020/09/07 13:19:20 jakllsch Exp $ */ /* * Copyright (c) 2014-2020 The NetBSD Foundation, Inc. @@ -470,7 +470,7 @@ "b\4OSPKE\0" "b\5WAITPKG\0" "b\6AVX512_VBMI2\0" "b\7CET_SS\0" \ "b\10GFNI\0" "b\11VAES\0" "b\12VPCLMULQDQ\0" "b\13AVX512_VNNI\0"\ "b\14AVX512_BITALG\0" "b\16AVX512_VPOPCNTDQ\0" \ - "b\20\LA57\0" \ + "b\20LA57\0" \ "f\21\5MAWAU\0" \ "b\26RDPID\0" \ "b\31CLDEMOTE\0" "b\33MOVDIRI\0" \
CVS commit: src/sys/arch/x86/include
Module Name:src
Committed By: msaitoh
Date: Mon Sep 7 03:03:09 UTC 2020
Modified Files:
src/sys/arch/x86/include: specialreg.h
Log Message:
Add CPUID(EAX=07H, ECX=0) ECX bit 16 LA57 from maxv.
To generate a diff of this commit:
cvs rdiff -u -r1.173 -r1.174 src/sys/arch/x86/include/specialreg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/include/specialreg.h
diff -u src/sys/arch/x86/include/specialreg.h:1.173 src/sys/arch/x86/include/specialreg.h:1.174
--- src/sys/arch/x86/include/specialreg.h:1.173 Sat Sep 5 07:45:44 2020
+++ src/sys/arch/x86/include/specialreg.h Mon Sep 7 03:03:09 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: specialreg.h,v 1.173 2020/09/05 07:45:44 maxv Exp $ */
+/* $NetBSD: specialreg.h,v 1.174 2020/09/07 03:03:09 msaitoh Exp $ */
/*
* Copyright (c) 2014-2020 The NetBSD Foundation, Inc.
@@ -456,6 +456,7 @@
#define CPUID_SEF_AVX512_VNNI __BIT(11) /* Vector neural Network Instruction */
#define CPUID_SEF_AVX512_BITALG __BIT(12)
#define CPUID_SEF_AVX512_VPOPCNTDQ __BIT(14)
+#define CPUID_SEF_LA57 __BIT(16) /* 57bit linear addr & 5LVL paging */
#define CPUID_SEF_MAWAU __BITS(21, 17) /* MAWAU for BND{LD,ST}X */
#define CPUID_SEF_RDPID __BIT(22) /* RDPID and IA32_TSC_AUX */
#define CPUID_SEF_CLDEMOTE __BIT(25) /* Cache line demote */
@@ -469,6 +470,7 @@
"b\4OSPKE\0" "b\5WAITPKG\0" "b\6AVX512_VBMI2\0" "b\7CET_SS\0" \
"b\10GFNI\0" "b\11VAES\0" "b\12VPCLMULQDQ\0" "b\13AVX512_VNNI\0"\
"b\14AVX512_BITALG\0" "b\16AVX512_VPOPCNTDQ\0" \
+ "b\20\LA57\0" \
"f\21\5MAWAU\0" \
"b\26RDPID\0" \
"b\31CLDEMOTE\0" "b\33MOVDIRI\0" \
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: maxv Date: Fri Sep 4 17:05:09 UTC 2020 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: Add a few more CPUID flags. To generate a diff of this commit: cvs rdiff -u -r1.171 -r1.172 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/x86/include/specialreg.h diff -u src/sys/arch/x86/include/specialreg.h:1.171 src/sys/arch/x86/include/specialreg.h:1.172 --- src/sys/arch/x86/include/specialreg.h:1.171 Wed Aug 5 15:40:46 2020 +++ src/sys/arch/x86/include/specialreg.h Fri Sep 4 17:05:09 2020 @@ -1,4 +1,4 @@ -/* $NetBSD: specialreg.h,v 1.171 2020/08/05 15:40:46 maxv Exp $ */ +/* $NetBSD: specialreg.h,v 1.172 2020/09/04 17:05:09 maxv Exp $ */ /* * Copyright (c) 2014-2020 The NetBSD Foundation, Inc. @@ -759,6 +759,11 @@ #define CPUID_CAPEX_VIRT_SSBD __BIT(25) /* Virt Spec Control SSBD */ #define CPUID_CAPEX_SSB_NO __BIT(26) /* SSBD not required */ +/* %ecx */ +#define CPUID_CAPEX_PerfTscSize __BITS(17,16) +#define CPUID_CAPEX_ApicIdSize __BITS(15,12) +#define CPUID_CAPEX_NC __BITS(7,0) + #define CPUID_CAPEX_FLAGS "\20" \ "\1CLZERO" "\2IRPERF" "\3XSAVEERPTR" \ "\5RDPRU" "\7B6" \ @@ -767,6 +772,9 @@ "\21IBRS_ALWAYSON" "\22STIBP_ALWAYSON" "\23PREFER_IBRS" "\24B19" \ "\31SSBD" "\32VIRT_SSBD" "\33SSB_NO" +/* AMD Fn8000_000a %eax (SVM Revision) */ +#define CPUID_AMD_SVM_REV __BITS(7,0) + /* AMD Fn8000_000a %edx features (SVM features) */ #define CPUID_AMD_SVM_NP 0x0001 #define CPUID_AMD_SVM_LbrVirt 0x0002
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: maxv Date: Wed Aug 5 15:40:46 UTC 2020 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: Add new fields here and there. To generate a diff of this commit: cvs rdiff -u -r1.170 -r1.171 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/x86/include/specialreg.h diff -u src/sys/arch/x86/include/specialreg.h:1.170 src/sys/arch/x86/include/specialreg.h:1.171 --- src/sys/arch/x86/include/specialreg.h:1.170 Mon Jul 20 05:50:55 2020 +++ src/sys/arch/x86/include/specialreg.h Wed Aug 5 15:40:46 2020 @@ -1,4 +1,4 @@ -/* $NetBSD: specialreg.h,v 1.170 2020/07/20 05:50:55 maxv Exp $ */ +/* $NetBSD: specialreg.h,v 1.171 2020/08/05 15:40:46 maxv Exp $ */ /* * Copyright (c) 2014-2020 The NetBSD Foundation, Inc. @@ -109,6 +109,7 @@ #define CR4_OSFXSR 0x0200 /* enable fxsave/fxrestor and SSE */ #define CR4_OSXMMEXCPT 0x0400 /* enable unmasked SSE exceptions */ #define CR4_UMIP 0x0800 /* user-mode instruction prevention */ +#define CR4_LA57 0x1000 /* 57-bit linear addresses */ #define CR4_VMXE 0x2000 /* enable VMX operations */ #define CR4_SMXE 0x4000 /* enable SMX operations */ #define CR4_FSGSBASE 0x0001 /* enable *FSBASE and *GSBASE instructions */ @@ -116,7 +117,9 @@ #define CR4_OSXSAVE 0x0004 /* enable xsave and xrestore */ #define CR4_SMEP 0x0010 /* enable SMEP support */ #define CR4_SMAP 0x0020 /* enable SMAP support */ -#define CR4_PKE 0x0040 /* protection key enable */ +#define CR4_PKE 0x0040 /* enable Protection Keys for user pages */ +#define CR4_CET 0x0080 /* enable CET */ +#define CR4_PKS 0x0100 /* enable Protection Keys for kern pages */ /* * Extended Control Register XCR0 @@ -131,13 +134,17 @@ #define XCR0_Hi16_ZMM 0x0080 /* AVX-512 512 bits upper registers */ #define XCR0_PT 0x0100 /* Processor Trace state */ #define XCR0_PKRU 0x0200 /* Protection Key state */ +#define XCR0_CET_U 0x0800 /* User CET state */ +#define XCR0_CET_S 0x1000 /* Kern CET state */ #define XCR0_HDC 0x2000 /* Hardware Duty Cycle state */ +#define XCR0_HWP 0x0001 /* Hardware P-states */ #define XCR0_FLAGS1 "\20" \ "\1" "x87" "\2" "SSE" "\3" "AVX" \ "\4" "BNDREGS" "\5" "BNDCSR" "\6" "Opmask" \ "\7" "ZMM_Hi256" "\10" "Hi16_ZMM" "\11" "PT" \ - "\12" "PKRU" "\16" "HDC" + "\12" "PKRU" "\14" "CET_U" "\15" "CET_S" \ + "\16" "HDC" "\21" "HWP" /* * Known FPU bits, only these get enabled. The save area is sized for all the @@ -147,7 +154,7 @@ XCR0_Opmask | XCR0_ZMM_Hi256 | XCR0_Hi16_ZMM) /* - * XSAVE component indices. + * XSAVE component indices, internal to NetBSD. */ #define XSAVE_X87 0 #define XSAVE_SSE 1 @@ -157,9 +164,6 @@ #define XSAVE_Opmask 5 #define XSAVE_ZMM_Hi256 6 #define XSAVE_Hi16_ZMM 7 -#define XSAVE_PT 8 -#define XSAVE_PKRU 9 -#define XSAVE_HDC 10 /* * Highest XSAVE component enabled by XCR0_FPU. @@ -448,7 +452,7 @@ #define CPUID_SEF_OSPKE __BIT(4) /* OS has set CR4.PKE to ena. protec. keys */ #define CPUID_SEF_WAITPKG __BIT(5) /* TPAUSE,UMONITOR,UMWAIT */ #define CPUID_SEF_AVX512_VBMI2 __BIT(6) /* AVX-512 Vector Byte Manipulation 2 */ -#define CPUID_SEF_CET_SS __BIT(7) /* CET shadow stack */ +#define CPUID_SEF_CET_SS __BIT(7) /* CET Shadow Stack */ #define CPUID_SEF_GFNI __BIT(8) #define CPUID_SEF_VAES __BIT(9) #define CPUID_SEF_VPCLMULQDQ __BIT(10) @@ -461,7 +465,7 @@ #define CPUID_SEF_MOVDIRI __BIT(27) /* MOVDIRI instruction */ #define CPUID_SEF_MOVDIR64B __BIT(28) /* MOVDIR64B instruction */ #define CPUID_SEF_SGXLC __BIT(30) /* SGX Launch Configuration */ -#define CPUID_SEF_PKS __BIT(31) /* Protection Keys */ +#define CPUID_SEF_PKS __BIT(31) /* Protection Keys for Kern-mode pages */ #define CPUID_SEF_FLAGS1 "\177\20" \ "b\0PREFETCHWT1\0" "b\1AVX512_VBMI\0" "b\2UMIP\0" "b\3PKU\0" \ @@ -481,7 +485,7 @@ #define CPUID_SEF_SRBDS_CTRL __BIT(9) /* IA32_MCU_OPT_CTRL */ #define CPUID_SEF_MD_CLEAR __BIT(10) #define CPUID_SEF_TSX_FORCE_ABORT __BIT(13) /* MSR_TSX_FORCE_ABORT bit 0 */ -#define CPUID_SEF_SERIALIZE __BIT(14) +#define CPUID_SEF_SERIALIZE __BIT(14) /* SERIALIZE instruction */ #define CPUID_SEF_HYBRID __BIT(15) /* Hybrid part */ #define CPUID_SEF_TSXLDTRK __BIT(16) /* TSX suspend load addr tracking */ #define CPUID_SEF_CET_IBT __BIT(20) /* CET Indirect Branch Tracking */
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: maxv Date: Mon Jul 20 05:50:56 UTC 2020 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: Revert previous, to unbreak the build (NVMM declares the macro too). There are hundreds of MSRs, we're not going to list them all, especially when the majority are unused. To generate a diff of this commit: cvs rdiff -u -r1.169 -r1.170 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/x86/include/specialreg.h diff -u src/sys/arch/x86/include/specialreg.h:1.169 src/sys/arch/x86/include/specialreg.h:1.170 --- src/sys/arch/x86/include/specialreg.h:1.169 Sun Jul 19 16:17:00 2020 +++ src/sys/arch/x86/include/specialreg.h Mon Jul 20 05:50:55 2020 @@ -1,4 +1,4 @@ -/* $NetBSD: specialreg.h,v 1.169 2020/07/19 16:17:00 jdolecek Exp $ */ +/* $NetBSD: specialreg.h,v 1.170 2020/07/20 05:50:55 maxv Exp $ */ /* * Copyright (c) 2014-2020 The NetBSD Foundation, Inc. @@ -865,9 +865,6 @@ #define APICBASE_PHYSADDR 0xf000 /* physical address */ #define MSR_EBL_CR_POWERON 0x02a #define MSR_EBC_FREQUENCY_ID 0x02c /* PIV only */ -#define MSR_IA32_FEATURE_CONTROL 0x03a -#define IA32_FEATURE_CONTROL_ENABLE_VMXON_INSIDE_SMX 0x0002 -#define IA32_FEATURE_CONTROL_ENABLE_VMXON_OUTSIDE_SMX 0x0004 #define MSR_IA32_SPEC_CTRL 0x048 #define IA32_SPEC_CTRL_IBRS 0x01 #define IA32_SPEC_CTRL_STIBP 0x02
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: jdolecek Date: Sun Jul 19 16:17:00 UTC 2020 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: add definition for MSR_IA32_FEATURE_CONTROL, just for information To generate a diff of this commit: cvs rdiff -u -r1.168 -r1.169 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/x86/include/specialreg.h diff -u src/sys/arch/x86/include/specialreg.h:1.168 src/sys/arch/x86/include/specialreg.h:1.169 --- src/sys/arch/x86/include/specialreg.h:1.168 Thu Jun 18 16:27:24 2020 +++ src/sys/arch/x86/include/specialreg.h Sun Jul 19 16:17:00 2020 @@ -1,4 +1,4 @@ -/* $NetBSD: specialreg.h,v 1.168 2020/06/18 16:27:24 maxv Exp $ */ +/* $NetBSD: specialreg.h,v 1.169 2020/07/19 16:17:00 jdolecek Exp $ */ /* * Copyright (c) 2014-2020 The NetBSD Foundation, Inc. @@ -865,6 +865,9 @@ #define APICBASE_PHYSADDR 0xf000 /* physical address */ #define MSR_EBL_CR_POWERON 0x02a #define MSR_EBC_FREQUENCY_ID 0x02c /* PIV only */ +#define MSR_IA32_FEATURE_CONTROL 0x03a +#define IA32_FEATURE_CONTROL_ENABLE_VMXON_INSIDE_SMX 0x0002 +#define IA32_FEATURE_CONTROL_ENABLE_VMXON_OUTSIDE_SMX 0x0004 #define MSR_IA32_SPEC_CTRL 0x048 #define IA32_SPEC_CTRL_IBRS 0x01 #define IA32_SPEC_CTRL_STIBP 0x02
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: maxv Date: Thu Jun 18 16:27:24 UTC 2020 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: style and fix typo To generate a diff of this commit: cvs rdiff -u -r1.167 -r1.168 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/x86/include/specialreg.h diff -u src/sys/arch/x86/include/specialreg.h:1.167 src/sys/arch/x86/include/specialreg.h:1.168 --- src/sys/arch/x86/include/specialreg.h:1.167 Wed Jun 10 03:39:03 2020 +++ src/sys/arch/x86/include/specialreg.h Thu Jun 18 16:27:24 2020 @@ -1,7 +1,7 @@ -/* $NetBSD: specialreg.h,v 1.167 2020/06/10 03:39:03 msaitoh Exp $ */ +/* $NetBSD: specialreg.h,v 1.168 2020/06/18 16:27:24 maxv Exp $ */ /* - * Copyright (c) 2014-2019 The NetBSD Foundation, Inc. + * Copyright (c) 2014-2020 The NetBSD Foundation, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -294,10 +294,10 @@ ? 0 : (CPUID_TO_EXTMODEL(cpuid) << 4))) /* CPUID Fn0001 %ebx */ -#define CPUID_BRAND_INDEX __BITS(7,0) -#define CPUID_CLFLUSH_SIZE __BITS(15,8) -#define CPUID_HTT_CORES __BITS(23,16) -#define CPUID_LOCAL_APIC_ID __BITS(31,24) +#define CPUID_BRAND_INDEX __BITS(7,0) +#define CPUID_CLFLUSH_SIZE __BITS(15,8) +#define CPUID_HTT_CORES __BITS(23,16) +#define CPUID_LOCAL_APIC_ID __BITS(31,24) /* * Intel Deterministic Cache Parameter Leaf @@ -389,7 +389,7 @@ /* * Intel/AMD Structured Extended Feature leaf Fn_0007 - * %eax == 0: Subleaf 0 + * %ecx == 0: Subleaf 0 * %eax: The Maximum input value for supported subleaf. * %ebx: Feature bits. * %ecx: Feature bits.
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: msaitoh Date: Wed Jun 10 03:39:03 UTC 2020 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: Add SRBDS_CTRL bit. To generate a diff of this commit: cvs rdiff -u -r1.166 -r1.167 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/x86/include/specialreg.h diff -u src/sys/arch/x86/include/specialreg.h:1.166 src/sys/arch/x86/include/specialreg.h:1.167 --- src/sys/arch/x86/include/specialreg.h:1.166 Mon Jun 1 08:32:39 2020 +++ src/sys/arch/x86/include/specialreg.h Wed Jun 10 03:39:03 2020 @@ -1,4 +1,4 @@ -/* $NetBSD: specialreg.h,v 1.166 2020/06/01 08:32:39 msaitoh Exp $ */ +/* $NetBSD: specialreg.h,v 1.167 2020/06/10 03:39:03 msaitoh Exp $ */ /* * Copyright (c) 2014-2019 The NetBSD Foundation, Inc. @@ -478,6 +478,7 @@ #define CPUID_SEF_AVX512_4FMAPS __BIT(3) #define CPUID_SEF_FSREP_MOV __BIT(4) /* Fast Short REP MOV */ #define CPUID_SEF_AVX512_VP2INTERSECT __BIT(8) +#define CPUID_SEF_SRBDS_CTRL __BIT(9) /* IA32_MCU_OPT_CTRL */ #define CPUID_SEF_MD_CLEAR __BIT(10) #define CPUID_SEF_TSX_FORCE_ABORT __BIT(13) /* MSR_TSX_FORCE_ABORT bit 0 */ #define CPUID_SEF_SERIALIZE __BIT(14) @@ -494,7 +495,7 @@ #define CPUID_SEF_FLAGS2 "\20" \ "\3" "AVX512_4VNNIW" "\4" "AVX512_4FMAPS" \ "\5" "FSREP_MOV" \ - "\11" "VP2INTERSECT" "\13" "MD_CLEAR" \ + "\11VP2INTERSECT" "\12SRBDS_CTRL" "\13MD_CLEAR" \ "\16TSX_FORCE_ABORT" "\17SERIALIZE" "\20HYBRID" \ "\21" "TSXLDTRK" \ "\25" "CET_IBT" \
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: msaitoh Date: Mon Jun 1 08:32:39 UTC 2020 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: Add some definitions from the latest Intel SDM plus small fix: - Add CPUID leaf 6 %eax bit 19 for HW_FEEDBACK* and IA32_PACKAGE_TERM* MSRs. - Add CPUID leaf 7 %ecx bit 31 for Protection Keys. - Add definition of Load only TLB and Store only TLB. - Add IF_PSCHANGE_MC_NO bit of IA32_ARCH_CAPABILITIES - Fix HWP_IGNIDL. To generate a diff of this commit: cvs rdiff -u -r1.165 -r1.166 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/x86/include/specialreg.h diff -u src/sys/arch/x86/include/specialreg.h:1.165 src/sys/arch/x86/include/specialreg.h:1.166 --- src/sys/arch/x86/include/specialreg.h:1.165 Thu May 28 07:59:38 2020 +++ src/sys/arch/x86/include/specialreg.h Mon Jun 1 08:32:39 2020 @@ -1,4 +1,4 @@ -/* $NetBSD: specialreg.h,v 1.165 2020/05/28 07:59:38 msaitoh Exp $ */ +/* $NetBSD: specialreg.h,v 1.166 2020/06/01 08:32:39 msaitoh Exp $ */ /* * Copyright (c) 2014-2019 The NetBSD Foundation, Inc. @@ -367,6 +367,7 @@ #define CPUID_DSPM_HWP_PECI __BIT(16) /* HWP PECI override */ #define CPUID_DSPM_HWP_FLEX __BIT(17) /* Flexible HWP */ #define CPUID_DSPM_HWP_FAST __BIT(18) /* Fast access for IA32_HWP_REQUEST */ +#define CPUID_DSPM_HW_FEEDBACK __BIT(19) /* HW_FEEDBACK*, IA32_PACKAGE_TERM* */ #define CPUID_DSPM_HWP_IGNIDL __BIT(20) /* Ignore Idle Logical Processor HWP */ #define CPUID_DSPM_FLAGS "\20" \ @@ -374,8 +375,8 @@ "\5" "PLN" "\6" "ECMD" "\7" "PTM" "\10" "HWP" \ "\11" "HWP_NOTIFY" "\12" "HWP_ACTWIN" "\13" "HWP_EPP" "\14" "HWP_PLR" \ "\16" "HDC" "\17" "TBM3" "\20" "HWP_CAP" \ - "\21" "HWP_PECI" "\22" "HWP_FLEX" "\23" "HWP_FAST" \ - "25" "HWP_IGNIDL" + "\21" "HWP_PECI" "\22" "HWP_FLEX" "\23" "HWP_FAST" "\24HW_FEEDBACK" \ + "\25" "HWP_IGNIDL" /* * Intel/AMD Digital Thermal Sensor and @@ -460,6 +461,7 @@ #define CPUID_SEF_MOVDIRI __BIT(27) /* MOVDIRI instruction */ #define CPUID_SEF_MOVDIR64B __BIT(28) /* MOVDIR64B instruction */ #define CPUID_SEF_SGXLC __BIT(30) /* SGX Launch Configuration */ +#define CPUID_SEF_PKS __BIT(31) /* Protection Keys */ #define CPUID_SEF_FLAGS1 "\177\20" \ "b\0PREFETCHWT1\0" "b\1AVX512_VBMI\0" "b\2UMIP\0" "b\3PKU\0" \ @@ -469,7 +471,7 @@ "f\21\5MAWAU\0" \ "b\26RDPID\0" \ "b\31CLDEMOTE\0" "b\33MOVDIRI\0" \ - "b\34MOVDIR64B\0" "b\36SGXLC\0" + "b\34MOVDIR64B\0" "b\36SGXLC\0" "b\37PKS\0" /* %edx */ #define CPUID_SEF_AVX512_4VNNIW __BIT(2) @@ -608,6 +610,8 @@ #define CPUID_DATP_TCTYPE_D 1 /* Data TLB */ #define CPUID_DATP_TCTYPE_I 2 /* Instruction TLB */ #define CPUID_DATP_TCTYPE_U 3 /* Unified TLB */ +#define CPUID_DATP_TCTYPE_L 4 /* Load only TLB */ +#define CPUID_DATP_TCTYPE_S 5 /* Store only TLB */ #define CPUID_DATP_TCLEVEL __BITS(7, 5) /* TLB level (start at 1) */ #define CPUID_DATP_FULLASSOC __BIT(8) /* Full associative */ #define CPUID_DATP_SHAREING __BITS(25, 14) /* shareing */ @@ -882,6 +886,7 @@ #define IA32_ARCH_SKIP_L1DFL_VMENTRY 0x08 #define IA32_ARCH_SSB_NO 0x10 #define IA32_ARCH_MDS_NO 0x20 +#define IA32_ARCH_IF_PSCHANGE_MC_NO 0x40 #define IA32_ARCH_TSX_CTRL 0x80 #define IA32_ARCH_TAA_NO 0x100 #define MSR_IA32_FLUSH_CMD 0x10b
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: msaitoh Date: Thu May 28 07:59:38 UTC 2020 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: Add AMD MSR_DE_CFG's bit 1 as DE_CFG_LFENCE_SERIALIZE. This bit makes lfence instruction serializing. To generate a diff of this commit: cvs rdiff -u -r1.164 -r1.165 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/x86/include/specialreg.h diff -u src/sys/arch/x86/include/specialreg.h:1.164 src/sys/arch/x86/include/specialreg.h:1.165 --- src/sys/arch/x86/include/specialreg.h:1.164 Fri May 1 04:07:24 2020 +++ src/sys/arch/x86/include/specialreg.h Thu May 28 07:59:38 2020 @@ -1,4 +1,4 @@ -/* $NetBSD: specialreg.h,v 1.164 2020/05/01 04:07:24 msaitoh Exp $ */ +/* $NetBSD: specialreg.h,v 1.165 2020/05/28 07:59:38 msaitoh Exp $ */ /* * Copyright (c) 2014-2019 The NetBSD Foundation, Inc. @@ -1121,6 +1121,7 @@ #define MSR_DE_CFG 0xc0011029 #define DE_CFG_ERRATA_721 0x0001 +#define DE_CFG_LFENCE_SERIALIZE __BIT(1) #define DE_CFG_ERRATA_1021 __BIT(13) #define MSR_BU_CFG2 0xc001102a
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: msaitoh Date: Fri May 1 04:07:24 UTC 2020 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: - Add AMD INVLPGB/TLBSYNC hypervisor enable in VMCB and TLBSYNC intercept bit. - Modify comment. To generate a diff of this commit: cvs rdiff -u -r1.163 -r1.164 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/x86/include/specialreg.h diff -u src/sys/arch/x86/include/specialreg.h:1.163 src/sys/arch/x86/include/specialreg.h:1.164 --- src/sys/arch/x86/include/specialreg.h:1.163 Sat Apr 25 15:26:18 2020 +++ src/sys/arch/x86/include/specialreg.h Fri May 1 04:07:24 2020 @@ -1,4 +1,4 @@ -/* $NetBSD: specialreg.h,v 1.163 2020/04/25 15:26:18 bouyer Exp $ */ +/* $NetBSD: specialreg.h,v 1.164 2020/05/01 04:07:24 msaitoh Exp $ */ /* * Copyright (c) 2014-2019 The NetBSD Foundation, Inc. @@ -730,6 +730,7 @@ * %eax: Long Mode Size Identifiers * %ebx: Extended Feature Identifiers * %ecx: Size Identifiers + * %edx: RDPRU Register Identifier Range */ /* %ebx */ @@ -773,6 +774,7 @@ #define CPUID_AMD_SVM_vGIF 0x0001 /* Virtualized GIF */ #define CPUID_AMD_SVM_GMET 0x0002 #define CPUID_AMD_SVM_SPEC_CTRL __BIT(20) +#define CPUID_AMD_SVM_TLBICTL __BIT(24) /* TLB Inttercept Control */ #define CPUID_AMD_SVM_FLAGS "\20" \ "\1" "NP" "\2" "LbrVirt" "\3" "SVML" "\4" "NRIPS" \ @@ -782,10 +784,11 @@ "\15" "PFThreshold" "\16" "AVIC" "\17" "B14" \ "\20" "V_VMSAVE_VMLOAD" \ "\21" "VGIF" "\22" "GMET" \ - "\25" "SPEC_CTRL" + "\25" "SPEC_CTRL" \ + "\31" "TLBICTL" /* - * AMD Fn8000_0001d Cache Topology Information. + * AMD Fn8000_001d Cache Topology Information. * It's almost the same as Intel Deterministic Cache Parameter Leaf(0x04) * except the following: * No Cores/package (%eax bit 31..26) @@ -793,7 +796,7 @@ */ /* - * AMD Fn8000_0001f Encrypted Memory Capabilities. + * AMD Fn8000_001f Encrypted Memory Capabilities. * %eax: flags * %ebx: 5-0: Cbit Position * 11-6: PhysAddrReduction
CVS commit: src/sys/arch/x86/include
Module Name:src
Committed By: bouyer
Date: Mon Apr 27 16:29:17 UTC 2020
Modified Files:
src/sys/arch/x86/include: cpu.h
Log Message:
Move ci_vcpu under the #ifdef XEN section at the end of the struct cpu_info.
Hopefully will fix the nvmm module.
To generate a diff of this commit:
cvs rdiff -u -r1.122 -r1.123 src/sys/arch/x86/include/cpu.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/include/cpu.h
diff -u src/sys/arch/x86/include/cpu.h:1.122 src/sys/arch/x86/include/cpu.h:1.123
--- src/sys/arch/x86/include/cpu.h:1.122 Sat Apr 25 15:26:18 2020
+++ src/sys/arch/x86/include/cpu.h Mon Apr 27 16:29:17 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu.h,v 1.122 2020/04/25 15:26:18 bouyer Exp $ */
+/* $NetBSD: cpu.h,v 1.123 2020/04/27 16:29:17 bouyer Exp $ */
/*
* Copyright (c) 1990 The Regents of the University of California.
@@ -111,9 +111,6 @@ struct cpu_info {
struct cpu_data ci_data; /* MI per-cpu data */
device_t ci_dev; /* pointer to our device */
struct cpu_info *ci_self; /* self-pointer */
-#ifdef XEN
- volatile struct vcpu_info *ci_vcpu; /* for XEN */
-#endif
/*
* Private members.
@@ -269,6 +266,7 @@ struct cpu_info {
struct evcnt ci_ipi_events[XEN_NIPIS];
#endif
#ifdef XEN
+ volatile struct vcpu_info *ci_vcpu; /* for XEN */
u_long ci_evtmask[NR_EVENT_CHANNELS]; /* events allowed on this CPU */
evtchn_port_t ci_ipi_evtchn;
#if defined(XENPV)
CVS commit: src/sys/arch/x86/include
Module Name:src
Committed By: msaitoh
Date: Fri Apr 24 09:49:05 UTC 2020
Modified Files:
src/sys/arch/x86/include: specialreg.h
Log Message:
- AMD CPUID Fn8000_000a %edx bit 20 is "SPEC_CTRL".
- Add some bit definitions of AMD's CPUID Fn8000_001f Encrypted Memory
features.
To generate a diff of this commit:
cvs rdiff -u -r1.161 -r1.162 src/sys/arch/x86/include/specialreg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/include/specialreg.h
diff -u src/sys/arch/x86/include/specialreg.h:1.161 src/sys/arch/x86/include/specialreg.h:1.162
--- src/sys/arch/x86/include/specialreg.h:1.161 Mon Apr 6 09:24:49 2020
+++ src/sys/arch/x86/include/specialreg.h Fri Apr 24 09:49:05 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: specialreg.h,v 1.161 2020/04/06 09:24:49 msaitoh Exp $ */
+/* $NetBSD: specialreg.h,v 1.162 2020/04/24 09:49:05 msaitoh Exp $ */
/*
* Copyright (c) 2014-2019 The NetBSD Foundation, Inc.
@@ -772,7 +772,9 @@
#define CPUID_AMD_SVM_V_VMSAVE_VMLOAD 0x8000 /* Virtual VM{SAVE/LOAD} */
#define CPUID_AMD_SVM_vGIF 0x0001 /* Virtualized GIF */
#define CPUID_AMD_SVM_GMET 0x0002
-#define CPUID_AMD_SVM_FLAGS "\20" \
+#define CPUID_AMD_SVM_SPEC_CTRL __BIT(20)
+
+#define CPUID_AMD_SVM_FLAGS "\20" \
"\1" "NP" "\2" "LbrVirt" "\3" "SVML" "\4" "NRIPS" \
"\5" "TSCRate" "\6" "VMCBCleanBits" \
"\7" "FlushByASID" "\10" "DecodeAssist" \
@@ -780,7 +782,7 @@
"\15" "PFThreshold" "\16" "AVIC" "\17" "B14" \
"\20" "V_VMSAVE_VMLOAD" \
"\21" "VGIF" "\22" "GMET" \
- "\25" "B20"
+ "\25" "SPEC_CTRL"
/*
* AMD Fn8000_0001d Cache Topology Information.
@@ -795,6 +797,7 @@
* %eax: flags
* %ebx: 5-0: Cbit Position
* 11-6: PhysAddrReduction
+ * 15-12: NumVMPL
* %ecx: 31-0: NumEncryptedGuests
* %edx: 31-0: MinSevNoEsAsid
*/
@@ -802,10 +805,21 @@
#define CPUID_AMD_ENCMEM_SEV __BIT(1) /* Secure Encrypted Virtualiz. */
#define CPUID_AMD_ENCMEM_PGFLMSR __BIT(2) /* Page Flush MSR */
#define CPUID_AMD_ENCMEM_SEVES __BIT(3) /* SEV Encrypted State */
+#define CPUID_AMD_ENCMEM_SEV_SNP __BIT(4) /* Secure Nested Paging */
+#define CPUID_AMD_ENCMEM_VMPL __BIT(5) /* Virtual Machine Privilege Lvl */
+#define CPUID_AMD_ENCMEM_HECC __BIT(10) /* HW Enf Cache Coh across enc dom */
+#define CPUID_AMD_ENCMEM_64BH __BIT(11) /* 64Bit Host */
+#define CPUID_AMD_ENCMEM_RSTRINJ __BIT(12) /* Restricted Injection */
+#define CPUID_AMD_ENCMEM_ALTINJ __BIT(13) /* Alternate Injection */
+#define CPUID_AMD_ENCMEM_DBGSWAP __BIT(14) /* Debug Swap */
+#define CPUID_AMD_ENCMEM_PREVHOSTIBS __BIT(15) /* Prevent Host IBS */
#define CPUID_AMD_ENCMEM_VTE __BIT(16) /* Virtual Transparent Encryption */
#define CPUID_AMD_ENCMEM_FLAGS "\20" \
"\1" "SME" "\2" "SEV" "\3" "PageFlushMsr" "\4" "SEV-ES" \
+ "\5" "SEV-SNP" "\6" "VMPL" \
+ "\13HwEnfCacheCoh" "\14" "64BitHost" \
+ "\15" "RSTRINJ" "\16" "ALTINJ" "\17" "DebugSwap" "\20PreventHostlbs" \
"\21" "VTE"
/*
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: msaitoh Date: Mon Apr 6 02:36:49 UTC 2020 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: CPUID Fn0001 %edx bit 8 is printed as "TSC", so rename CPUID Fn8000_0007 %edx bit 8 from "TSC" to "ITSC" (Invariant TSC) to avoid confusion. To generate a diff of this commit: cvs rdiff -u -r1.159 -r1.160 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/x86/include/specialreg.h diff -u src/sys/arch/x86/include/specialreg.h:1.159 src/sys/arch/x86/include/specialreg.h:1.160 --- src/sys/arch/x86/include/specialreg.h:1.159 Wed Apr 1 08:21:38 2020 +++ src/sys/arch/x86/include/specialreg.h Mon Apr 6 02:36:49 2020 @@ -1,4 +1,4 @@ -/* $NetBSD: specialreg.h,v 1.159 2020/04/01 08:21:38 msaitoh Exp $ */ +/* $NetBSD: specialreg.h,v 1.160 2020/04/06 02:36:49 msaitoh Exp $ */ /* * Copyright (c) 2014-2019 The NetBSD Foundation, Inc. @@ -708,7 +708,7 @@ #define CPUID_APM_STC 0x0020 /* Software thermal control (STC) */ #define CPUID_APM_100 0x0040 /* 100MHz multiplier control */ #define CPUID_APM_HWP 0x0080 /* HW P-State control */ -#define CPUID_APM_TSC 0x0100 /* TSC invariant */ +#define CPUID_APM_TSC 0x0100 /* TSC invariant (Intel, too) */ #define CPUID_APM_CPB 0x0200 /* Core performance boost */ #define CPUID_APM_EFF 0x0400 /* Effective Frequency (read-only) */ #define CPUID_APM_PROCFI 0x0800 /* Proc Feedback Interface */ @@ -719,7 +719,7 @@ #define CPUID_APM_FLAGS "\20" \ "\1" "TS" "\2" "FID" "\3" "VID" "\4" "TTP" \ "\5" "HTC" "\6" "STC" "\7" "100" "\10" "HWP" \ - "\11" "TSC" "\12" "CPB" "\13" "EffFreq" "\14" "PROCFI" \ + "\11" "ITSC" "\12" "CPB" "\13" "EffFreq" "\14" "PROCFI" \ "\15" "PROCPR" "\16" "CONNSTBY" "\17" "RAPL" /*
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: maxv Date: Sat Mar 14 04:55:15 UTC 2020 Modified Files: src/sys/arch/x86/include: pte.h trap.h Log Message: style To generate a diff of this commit: cvs rdiff -u -r1.3 -r1.4 src/sys/arch/x86/include/pte.h cvs rdiff -u -r1.2 -r1.3 src/sys/arch/x86/include/trap.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/x86/include/pte.h diff -u src/sys/arch/x86/include/pte.h:1.3 src/sys/arch/x86/include/pte.h:1.4 --- src/sys/arch/x86/include/pte.h:1.3 Wed Oct 9 17:28:46 2019 +++ src/sys/arch/x86/include/pte.h Sat Mar 14 04:55:14 2020 @@ -1,4 +1,4 @@ -/* $NetBSD: pte.h,v 1.3 2019/10/09 17:28:46 maxv Exp $ */ +/* $NetBSD: pte.h,v 1.4 2020/03/14 04:55:14 maxv Exp $ */ /* * Copyright (c) 2010 The NetBSD Foundation, Inc. @@ -39,7 +39,7 @@ #define PGC_UC (PTE_PWT | PTE_PCD) /* hard UC */ /* - * Page protection exception bits + * #PF exception bits */ #define PGEX_P 0x0001 /* the page was present */ #define PGEX_W 0x0002 /* exception during a write cycle */ Index: src/sys/arch/x86/include/trap.h diff -u src/sys/arch/x86/include/trap.h:1.2 src/sys/arch/x86/include/trap.h:1.3 --- src/sys/arch/x86/include/trap.h:1.2 Thu Aug 7 16:30:33 2003 +++ src/sys/arch/x86/include/trap.h Sat Mar 14 04:55:14 2020 @@ -1,4 +1,4 @@ -/* $NetBSD: trap.h,v 1.2 2003/08/07 16:30:33 agc Exp $ */ +/* $NetBSD: trap.h,v 1.3 2020/03/14 04:55:14 maxv Exp $ */ /*- * Copyright (c) 1990 The Regents of the University of California. @@ -34,35 +34,30 @@ * @(#)trap.h 5.4 (Berkeley) 5/9/91 */ -/* - * Trap type values - * also known in trap.c for name strings - */ - -#define T_PRIVINFLT 0 /* privileged instruction */ -#define T_BPTFLT 1 /* breakpoint trap */ -#define T_ARITHTRAP 2 /* arithmetic trap */ -#define T_ASTFLT 3 /* asynchronous system trap */ -#define T_PROTFLT 4 /* protection fault */ -#define T_TRCTRAP 5 /* trace trap */ -#define T_PAGEFLT 6 /* page fault */ -#define T_ALIGNFLT 7 /* alignment fault */ -#define T_DIVIDE 8 /* integer divide fault */ -#define T_NMI 9 /* non-maskable interrupt */ -#define T_OFLOW 10 /* overflow trap */ -#define T_BOUND 11 /* bounds check fault */ -#define T_DNA 12 /* device not available fault */ -#define T_DOUBLEFLT 13 /* double fault */ -#define T_FPOPFLT 14 /* fp coprocessor operand fetch fault */ -#define T_TSSFLT 15 /* invalid tss fault */ -#define T_SEGNPFLT 16 /* segment not present fault */ -#define T_STKFLT 17 /* stack fault */ -#define T_MCA 18 /* machine check */ +#define T_PRIVINFLT 0 /* privileged instruction */ +#define T_BPTFLT 1 /* breakpoint trap */ +#define T_ARITHTRAP 2 /* arithmetic trap */ +#define T_ASTFLT 3 /* asynchronous system trap */ +#define T_PROTFLT 4 /* protection fault */ +#define T_TRCTRAP 5 /* trace trap */ +#define T_PAGEFLT 6 /* page fault */ +#define T_ALIGNFLT 7 /* alignment fault */ +#define T_DIVIDE 8 /* integer divide fault */ +#define T_NMI 9 /* non-maskable interrupt */ +#define T_OFLOW 10 /* overflow trap */ +#define T_BOUND 11 /* bounds check fault */ +#define T_DNA 12 /* device not available fault */ +#define T_DOUBLEFLT 13 /* double fault */ +#define T_FPOPFLT 14 /* fp coprocessor operand fetch fault */ +#define T_TSSFLT 15 /* invalid tss fault */ +#define T_SEGNPFLT 16 /* segment not present fault */ +#define T_STKFLT 17 /* stack fault */ +#define T_MCA 18 /* machine check */ #define T_XMM 19 /* SSE FP exception */ #define T_RESERVED 20 /* reserved fault base */ /* Trap's coming from user mode */ -#define T_USER 0x100 +#define T_USER 0x100 /* Flags kludged into the trap code */
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: msaitoh Date: Wed Mar 13 05:22:07 UTC 2019 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: Add TSX_FORCE_ABORT related definitions. To generate a diff of this commit: cvs rdiff -u -r1.142 -r1.143 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/x86/include/specialreg.h diff -u src/sys/arch/x86/include/specialreg.h:1.142 src/sys/arch/x86/include/specialreg.h:1.143 --- src/sys/arch/x86/include/specialreg.h:1.142 Sat Mar 9 08:42:26 2019 +++ src/sys/arch/x86/include/specialreg.h Wed Mar 13 05:22:07 2019 @@ -1,4 +1,4 @@ -/* $NetBSD: specialreg.h,v 1.142 2019/03/09 08:42:26 maxv Exp $ */ +/* $NetBSD: specialreg.h,v 1.143 2019/03/13 05:22:07 msaitoh Exp $ */ /*- * Copyright (c) 1991 The Regents of the University of California. @@ -426,6 +426,7 @@ /* %edx */ #define CPUID_SEF_AVX512_4VNNIW __BIT(2) #define CPUID_SEF_AVX512_4FMAPS __BIT(3) +#define CPUID_SEF_TSX_FORCE_ABORT __BIT(13) /* MSR_TSX_FORCE_ABORT bit 0 */ #define CPUID_SEF_IBRS __BIT(26) /* IBRS / IBPB Speculation Control */ #define CPUID_SEF_STIBP __BIT(27) /* STIBP Speculation Control */ #define CPUID_SEF_L1D_FLUSH __BIT(28) /* IA32_FLUSH_CMD MSR */ @@ -435,7 +436,8 @@ #define CPUID_SEF_FLAGS2 "\20" \ "\3" "AVX512_4VNNIW" "\4" "AVX512_4FMAPS" \ - "\33" "IBRS" "\34" "STIBP" \ + "\16" "TSX_FORCE_ABORT"\ + "\33" "IBRS" "\34" "STIBP" \ "\35" "L1D_FLUSH" "\36" "ARCH_CAP" "\37CORE_CAP" "\40" "SSBD" /* @@ -745,8 +747,9 @@ #define IA32_ARCH_RSBA 0x04 #define IA32_ARCH_SKIP_L1DFL_VMENTRY 0x08 #define IA32_ARCH_SSB_NO 0x10 -#define MSR_IA32_FLUSH_CMD 0x10b +#define MSR_IA32_FLUSH_CMD 0x10b #define IA32_FLUSH_CMD_L1D_FLUSH 0x01 +#define MSR_TSX_FORCE_ABORT 0x10f #define MSR_BBL_CR_ADDR 0x116 /* PII+ only */ #define MSR_BBL_CR_DECC 0x118 /* PII+ only */ #define MSR_BBL_CR_CTL 0x119 /* PII+ only */
CVS commit: src/sys/arch/x86/include
Module Name:src
Committed By: cherry
Date: Wed Feb 13 05:28:50 UTC 2019
Modified Files:
src/sys/arch/x86/include: intr.h
Log Message:
Missed the crucial header file in previous commit.
struct intrstub; is now uniform across native and XEN
This should fix the XEN builds.
To generate a diff of this commit:
cvs rdiff -u -r1.58 -r1.59 src/sys/arch/x86/include/intr.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/include/intr.h
diff -u src/sys/arch/x86/include/intr.h:1.58 src/sys/arch/x86/include/intr.h:1.59
--- src/sys/arch/x86/include/intr.h:1.58 Mon Feb 11 14:59:32 2019
+++ src/sys/arch/x86/include/intr.h Wed Feb 13 05:28:50 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: intr.h,v 1.58 2019/02/11 14:59:32 cherry Exp $ */
+/* $NetBSD: intr.h,v 1.59 2019/02/13 05:28:50 cherry Exp $ */
/*-
* Copyright (c) 1998, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -71,9 +71,7 @@
*/
struct intrstub {
-#if !defined(XENPV)
void *ist_entry;
-#endif
void *ist_recurse;
void *ist_resume;
};
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: msaitoh Date: Fri Feb 8 04:06:00 UTC 2019 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: Fix bitstring format of Intel CPUID Architectural Performance Monitoring Fn000a %ebx. To generate a diff of this commit: cvs rdiff -u -r1.138 -r1.139 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/x86/include/specialreg.h diff -u src/sys/arch/x86/include/specialreg.h:1.138 src/sys/arch/x86/include/specialreg.h:1.139 --- src/sys/arch/x86/include/specialreg.h:1.138 Tue Feb 5 08:07:19 2019 +++ src/sys/arch/x86/include/specialreg.h Fri Feb 8 04:06:00 2019 @@ -1,4 +1,4 @@ -/* $NetBSD: specialreg.h,v 1.138 2019/02/05 08:07:19 msaitoh Exp $ */ +/* $NetBSD: specialreg.h,v 1.139 2019/02/08 04:06:00 msaitoh Exp $ */ /*- * Copyright (c) 1991 The Regents of the University of California. @@ -464,8 +464,8 @@ #define CPUID_PERF_BRMISPRRETR __BIT(6) /* No branch mispredict retry */ #define CPUID_PERF_FLAGS1 "\177\20" \ - "b\0\1CORECYCL\0" "b\1\1INSTRETRY\0" "b\2\1REFCYCL\0" "b\3\1LLCREF\0" \ - "b\4\1LLCMISS\0" "b\5\1BRINSRETR\0" "b\6\1BRMISPRRETR\0" + "b\0CORECYCL\0" "b\1INSTRETRY\0" "b\2REFCYCL\0" "b\3LLCREF\0" \ + "b\4LLCMISS\0" "b\5BRINSRETR\0" "b\6BRMISPRRETR\0" /* %edx */ #define CPUID_PERF_NFFPC __BITS(4, 0) /* Num of fixed-funct perfcnt */
CVS commit: src/sys/arch/x86/include
Module Name:src
Committed By: msaitoh
Date: Tue Feb 5 08:07:19 UTC 2019
Modified Files:
src/sys/arch/x86/include: specialreg.h
Log Message:
Add new CPUID flags WAITPKG, CLDEMOTE, MOVDIRI, MOVDIR64B and
IA32_CORE_CAPABILITIES from the latest Intel SDM.
To generate a diff of this commit:
cvs rdiff -u -r1.137 -r1.138 src/sys/arch/x86/include/specialreg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/include/specialreg.h
diff -u src/sys/arch/x86/include/specialreg.h:1.137 src/sys/arch/x86/include/specialreg.h:1.138
--- src/sys/arch/x86/include/specialreg.h:1.137 Sun Jan 13 12:19:09 2019
+++ src/sys/arch/x86/include/specialreg.h Tue Feb 5 08:07:19 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: specialreg.h,v 1.137 2019/01/13 12:19:09 maxv Exp $ */
+/* $NetBSD: specialreg.h,v 1.138 2019/02/05 08:07:19 msaitoh Exp $ */
/*-
* Copyright (c) 1991 The Regents of the University of California.
@@ -398,6 +398,7 @@
#define CPUID_SEF_UMIP __BIT(2) /* User-Mode Instruction prevention */
#define CPUID_SEF_PKU __BIT(3) /* Protection Keys for User-mode pages */
#define CPUID_SEF_OSPKE __BIT(4) /* OS has set CR4.PKE to ena. protec. keys */
+#define CPUID_SEF_WAITPKG __BIT(5) /* TPAUSE,UMONITOR,UMWAIT */
#define CPUID_SEF_AVX512_VBMI2 __BIT(6) /* AVX-512 Vector Byte Manipulation 2 */
#define CPUID_SEF_GFNI __BIT(8)
#define CPUID_SEF_VAES __BIT(9)
@@ -407,16 +408,20 @@
#define CPUID_SEF_AVX512_VPOPCNTDQ __BIT(14)
#define CPUID_SEF_MAWAU __BITS(21, 17) /* MAWAU for BND{LD,ST}X */
#define CPUID_SEF_RDPID __BIT(22) /* RDPID and IA32_TSC_AUX */
+#define CPUID_SEF_CLDEMOTE __BIT(25) /* Cache line demote */
+#define CPUID_SEF_MOVDIRI __BIT(27) /* MOVDIRI instruction */
+#define CPUID_SEF_MOVDIR64B __BIT(28) /* MOVDIR64B instruction */
#define CPUID_SEF_SGXLC __BIT(30) /* SGX Launch Configuration */
#define CPUID_SEF_FLAGS1 "\177\20" \
"b\0PREFETCHWT1\0" "b\1AVX512_VBMI\0" "b\2UMIP\0" "b\3PKU\0" \
- "b\4OSPKE\0" "b\6AVX512_VBMI2\0" \
+ "b\4OSPKE\0" "b\5WAITPKG\0" "b\6AVX512_VBMI2\0" \
"b\10GFNI\0" "b\11VAES\0" "b\12VPCLMULQDQ\0" "b\13AVX512_VNNI\0"\
"b\14AVX512_BITALG\0" "b\16AVX512_VPOPCNTDQ\0" \
"f\21\5MAWAU\0" \
"b\26RDPID\0" \
- "b\36SGXLC\0"
+ "b\31CLDEMOTE\0" "b\33MOVDIRI\0" \
+ "b\34MOVDIR64B\0" "b\36SGXLC\0"
/* %edx */
#define CPUID_SEF_AVX512_4VNNIW __BIT(2)
@@ -425,12 +430,13 @@
#define CPUID_SEF_STIBP __BIT(27) /* STIBP Speculation Control */
#define CPUID_SEF_L1D_FLUSH __BIT(28) /* IA32_FLUSH_CMD MSR */
#define CPUID_SEF_ARCH_CAP __BIT(29) /* IA32_ARCH_CAPABILITIES */
+#define CPUID_SEF_CORE_CAP __BIT(30) /* IA32_CORE_CAPABILITIES */
#define CPUID_SEF_SSBD __BIT(31) /* Speculative Store Bypass Disable */
#define CPUID_SEF_FLAGS2 "\20" \
"\3" "AVX512_4VNNIW" "\4" "AVX512_4FMAPS" \
"\33" "IBRS" "\34" "STIBP" \
- "\35" "L1D_FLUSH" "\36" "ARCH_CAP" "\40" "SSBD"
+ "\35" "L1D_FLUSH" "\36" "ARCH_CAP" "\37CORE_CAP" "\40" "SSBD"
/*
* Intel CPUID Architectural Performance Monitoring Fn000a
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: maxv Date: Sun Jan 13 12:19:09 UTC 2019 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: Forgot to commit file along with identcpu.c::rev1.86. To generate a diff of this commit: cvs rdiff -u -r1.136 -r1.137 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/x86/include/specialreg.h diff -u src/sys/arch/x86/include/specialreg.h:1.136 src/sys/arch/x86/include/specialreg.h:1.137 --- src/sys/arch/x86/include/specialreg.h:1.136 Mon Nov 26 04:43:37 2018 +++ src/sys/arch/x86/include/specialreg.h Sun Jan 13 12:19:09 2019 @@ -1,4 +1,4 @@ -/* $NetBSD: specialreg.h,v 1.136 2018/11/26 04:43:37 msaitoh Exp $ */ +/* $NetBSD: specialreg.h,v 1.137 2019/01/13 12:19:09 maxv Exp $ */ /*- * Copyright (c) 1991 The Regents of the University of California. @@ -971,6 +971,9 @@ #define DE_CFG_ERRATA_721 0x0001 #define DE_CFG_ERRATA_1021 __BIT(13) +#define MSR_BU_CFG2 0xc001102a +#define BU_CFG2_CWPLUS_DIS __BIT(24) + #define MSR_LS_CFG2 0xc001102d #define LS_CFG2_ERRATA_1091 __BIT(34)
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: cherry Date: Thu Dec 13 16:16:51 UTC 2018 Modified Files: src/sys/arch/x86/include: intr.h Log Message: Allow x86 builds to have the opportunity to not have pre-emption enabled by default. This can be effected by having a: "optionsNO_PREEMPTION" line in the kernel configuration file. While it was tempting to tie __HAVE_PREEMPTION to MULTIPROCESSOR, as is currently assumed in sys/kern/kern_stub.c , having MULTIPROCESSOR without __HAVE_PREEMPTION and not having either are valid configuration options which users could have choice of. We thus err on the side of configurability. To generate a diff of this commit: cvs rdiff -u -r1.56 -r1.57 src/sys/arch/x86/include/intr.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/x86/include/intr.h diff -u src/sys/arch/x86/include/intr.h:1.56 src/sys/arch/x86/include/intr.h:1.57 --- src/sys/arch/x86/include/intr.h:1.56 Sun Jun 24 13:35:33 2018 +++ src/sys/arch/x86/include/intr.h Thu Dec 13 16:16:51 2018 @@ -1,4 +1,4 @@ -/* $NetBSD: intr.h,v 1.56 2018/06/24 13:35:33 jdolecek Exp $ */ +/* $NetBSD: intr.h,v 1.57 2018/12/13 16:16:51 cherry Exp $ */ /*- * Copyright (c) 1998, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc. @@ -34,7 +34,9 @@ #if !defined(XEN) #define __HAVE_FAST_SOFTINTS +#if !defined(NO_PREEMPTION) #define __HAVE_PREEMPTION +#endif /* !defined(NO_PREEMPTION) */ #endif /* !defined(XEN) */ #ifdef _KERNEL
CVS commit: src/sys/arch/x86/include
Module Name:src
Committed By: maxv
Date: Thu Dec 6 17:26:18 UTC 2018
Modified Files:
src/sys/arch/x86/include: pmap.h
Log Message:
Fix inconsistency, these are indexes and not types, no real functional
change.
To generate a diff of this commit:
cvs rdiff -u -r1.91 -r1.92 src/sys/arch/x86/include/pmap.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/include/pmap.h
diff -u src/sys/arch/x86/include/pmap.h:1.91 src/sys/arch/x86/include/pmap.h:1.92
--- src/sys/arch/x86/include/pmap.h:1.91 Mon Nov 19 20:44:51 2018
+++ src/sys/arch/x86/include/pmap.h Thu Dec 6 17:26:18 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: pmap.h,v 1.91 2018/11/19 20:44:51 maxv Exp $ */
+/* $NetBSD: pmap.h,v 1.92 2018/12/06 17:26:18 maxv Exp $ */
/*
* Copyright (c) 1997 Charles D. Cranor and Washington University.
@@ -156,16 +156,15 @@ struct bootspace {
vaddr_t emodule;
};
-#define SLSPACE_NONE 0
-#define SLAREA_USER 1
-#define SLAREA_PTE 2
-#define SLAREA_MAIN 3
-#define SLAREA_PCPU 4
-#define SLAREA_DMAP 5
-#define SLAREA_HYPV 6
-#define SLAREA_ASAN 7
-#define SLAREA_KERN 8
-#define SLSPACE_NAREAS 9
+#define SLAREA_USER 0
+#define SLAREA_PTE 1
+#define SLAREA_MAIN 2
+#define SLAREA_PCPU 3
+#define SLAREA_DMAP 4
+#define SLAREA_HYPV 5
+#define SLAREA_ASAN 6
+#define SLAREA_KERN 7
+#define SLSPACE_NAREAS 8
struct slotspace {
struct {
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: msaitoh Date: Mon Nov 26 04:43:37 UTC 2018 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: Add Intel CPUID Architectural Performance Monitoring leaf Fn000a. To generate a diff of this commit: cvs rdiff -u -r1.135 -r1.136 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/x86/include/specialreg.h diff -u src/sys/arch/x86/include/specialreg.h:1.135 src/sys/arch/x86/include/specialreg.h:1.136 --- src/sys/arch/x86/include/specialreg.h:1.135 Thu Nov 22 06:14:35 2018 +++ src/sys/arch/x86/include/specialreg.h Mon Nov 26 04:43:37 2018 @@ -1,4 +1,4 @@ -/* $NetBSD: specialreg.h,v 1.135 2018/11/22 06:14:35 msaitoh Exp $ */ +/* $NetBSD: specialreg.h,v 1.136 2018/11/26 04:43:37 msaitoh Exp $ */ /*- * Copyright (c) 1991 The Regents of the University of California. @@ -433,6 +433,43 @@ "\35" "L1D_FLUSH" "\36" "ARCH_CAP" "\40" "SSBD" /* + * Intel CPUID Architectural Performance Monitoring Fn000a + * + * See also src/usr.sbin/tprof/arch/tprof_x86.c + */ + +/* %eax */ +#define CPUID_PERF_VERSION __BITS(7, 0) /* Version ID */ +#define CPUID_PERF_NGPPC __BITS(15, 8) /* Num of G.P. perf counter */ +#define CPUID_PERF_NBWGPPC __BITS(23, 16) /* Bit width of G.P. perfcnt */ +#define CPUID_PERF_BVECLEN __BITS(31, 24) /* Length of EBX bit vector */ + +#define CPUID_PERF_FLAGS0 "\177\20" \ + "f\0\10VERSION\0" "f\10\10GPCounter\0" \ + "f\20\10GPBitwidth\0" "f\30\10Vectorlen\0" + +/* %ebx */ +#define CPUID_PERF_CORECYCL __BIT(0) /* No core cycle */ +#define CPUID_PERF_INSTRETRY __BIT(1) /* No instruction retried */ +#define CPUID_PERF_REFCYCL __BIT(2) /* No reference cycles */ +#define CPUID_PERF_LLCREF __BIT(3) /* No LLCache reference */ +#define CPUID_PERF_LLCMISS __BIT(4) /* No LLCache miss */ +#define CPUID_PERF_BRINSRETR __BIT(5) /* No branch inst. retried */ +#define CPUID_PERF_BRMISPRRETR __BIT(6) /* No branch mispredict retry */ + +#define CPUID_PERF_FLAGS1 "\177\20" \ + "b\0\1CORECYCL\0" "b\1\1INSTRETRY\0" "b\2\1REFCYCL\0" "b\3\1LLCREF\0" \ + "b\4\1LLCMISS\0" "b\5\1BRINSRETR\0" "b\6\1BRMISPRRETR\0" + +/* %edx */ +#define CPUID_PERF_NFFPC __BITS(4, 0) /* Num of fixed-funct perfcnt */ +#define CPUID_PERF_NBWFFPC __BITS(12, 5) /* Bit width of fixed-func pc */ +#define CPUID_PERF_ANYTHREADDEPR __BIT(15) /* Any Thread deprecation */ + +#define CPUID_PERF_FLAGS3 "\177\20"\ + "f\0\5FixedFunc\0" "f\5\10FFBitwidth\0" "b\17ANYTHREADDEPR\0" + +/* * Intel CPUID Extended Topology Enumeration Fn000b * %ecx == level number * %eax: See below.
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: msaitoh Date: Thu Nov 22 06:14:35 UTC 2018 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: Add Intel/AMD MONITOR/MWAIT leaf. To generate a diff of this commit: cvs rdiff -u -r1.134 -r1.135 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/x86/include/specialreg.h diff -u src/sys/arch/x86/include/specialreg.h:1.134 src/sys/arch/x86/include/specialreg.h:1.135 --- src/sys/arch/x86/include/specialreg.h:1.134 Wed Nov 21 12:18:53 2018 +++ src/sys/arch/x86/include/specialreg.h Thu Nov 22 06:14:35 2018 @@ -1,4 +1,4 @@ -/* $NetBSD: specialreg.h,v 1.134 2018/11/21 12:18:53 msaitoh Exp $ */ +/* $NetBSD: specialreg.h,v 1.135 2018/11/22 06:14:35 msaitoh Exp $ */ /*- * Copyright (c) 1991 The Regents of the University of California. @@ -282,6 +282,24 @@ #define CPUID_DCP_COMPLEX __BIT(2) /* Complex cache indexing */ /* + * Intel/AMD MONITOR/MWAIT + * Fn_0005 + */ +/* %eax */ +#define CPUID_MON_MINSIZE __BITS(15, 0) /* Smallest monitor-line size */ +/* %ebx */ +#define CPUID_MON_MAXSIZE __BITS(15, 0) /* Largest monitor-line size */ +/* %ecx */ +#define CPUID_MON_EMX __BIT(0) /* MONITOR/MWAIT Extensions */ +#define CPUID_MON_IBE __BIT(1) /* Interrupt as Break Event */ + +#define CPUID_MON_FLAGS "\20" \ + "\1" "EMX" "\2" "IBE" + +/* %edx: number of substates for specific C-state */ +#define CPUID_MON_SUBSTATE(edx, cstate) (((edx) >> (cstate * 4)) & 0x000f) + +/* * Intel/AMD Digital Thermal Sensor and * Power Management, Fn_0006 - %eax. */
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: msaitoh Date: Wed Nov 21 12:18:53 UTC 2018 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: Add Intel CPUID Extended Topology Enumeration Fn000b definitions. To generate a diff of this commit: cvs rdiff -u -r1.133 -r1.134 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/x86/include/specialreg.h diff -u src/sys/arch/x86/include/specialreg.h:1.133 src/sys/arch/x86/include/specialreg.h:1.134 --- src/sys/arch/x86/include/specialreg.h:1.133 Wed Nov 21 06:09:49 2018 +++ src/sys/arch/x86/include/specialreg.h Wed Nov 21 12:18:53 2018 @@ -1,4 +1,4 @@ -/* $NetBSD: specialreg.h,v 1.133 2018/11/21 06:09:49 msaitoh Exp $ */ +/* $NetBSD: specialreg.h,v 1.134 2018/11/21 12:18:53 msaitoh Exp $ */ /*- * Copyright (c) 1991 The Regents of the University of California. @@ -415,6 +415,23 @@ "\35" "L1D_FLUSH" "\36" "ARCH_CAP" "\40" "SSBD" /* + * Intel CPUID Extended Topology Enumeration Fn000b + * %ecx == level number + * %eax: See below. + * %ebx: Number of logical processors at this level. + * %ecx: See below. + * %edx: x2APIC ID of the current logical processor. + */ +/* %eax */ +#define CPUID_TOP_SHIFTNUM __BITS(4, 0) /* Topology ID shift value */ +/* %ecx */ +#define CPUID_TOP_LVLNUM __BITS(7, 0) /* Level number */ +#define CPUID_TOP_LVLTYPE __BITS(15, 8) /* Level type */ +#define CPUID_TOP_LVLTYPE_INVAL 0 /* Invalid */ +#define CPUID_TOP_LVLTYPE_SMT 1 /* SMT */ +#define CPUID_TOP_LVLTYPE_CORE 2 /* Core */ + +/* * Intel/AMD CPUID Processor extended state Enumeration Fn000d * * %ecx == 0: supported features info:
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: msaitoh Date: Wed Nov 21 06:09:49 UTC 2018 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: Modify comment. No functional change: - AMD also has CPUID 0x06 and 0x0d. - PCOMMIT was obsoleted. To generate a diff of this commit: cvs rdiff -u -r1.132 -r1.133 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/x86/include/specialreg.h diff -u src/sys/arch/x86/include/specialreg.h:1.132 src/sys/arch/x86/include/specialreg.h:1.133 --- src/sys/arch/x86/include/specialreg.h:1.132 Thu Nov 15 03:50:22 2018 +++ src/sys/arch/x86/include/specialreg.h Wed Nov 21 06:09:49 2018 @@ -1,4 +1,4 @@ -/* $NetBSD: specialreg.h,v 1.132 2018/11/15 03:50:22 msaitoh Exp $ */ +/* $NetBSD: specialreg.h,v 1.133 2018/11/21 06:09:49 msaitoh Exp $ */ /*- * Copyright (c) 1991 The Regents of the University of California. @@ -282,7 +282,7 @@ #define CPUID_DCP_COMPLEX __BIT(2) /* Complex cache indexing */ /* - * Intel Digital Thermal Sensor and + * Intel/AMD Digital Thermal Sensor and * Power Management, Fn_0006 - %eax. */ #define CPUID_DSPM_DTS __BIT(0) /* Digital Thermal Sensor */ @@ -313,7 +313,7 @@ "25" "HWP_IGNIDL" /* - * Intel Digital Thermal Sensor and + * Intel/AMD Digital Thermal Sensor and * Power Management, Fn_0006 - %ecx. */ #define CPUID_DSPM_HWF 0x0001 /* MSR_APERF/MSR_MPERF available */ @@ -322,7 +322,7 @@ #define CPUID_DSPM_FLAGS1 "\20" "\1" "HWF" "\4" "EPB" /* - * Intel Structured Extended Feature leaf Fn_0007 + * Intel/AMD Structured Extended Feature leaf Fn_0007 * %eax == 0: Subleaf 0 * %eax: The Maximum input value for supported subleaf. * %ebx: Feature bits. @@ -353,6 +353,7 @@ #define CPUID_SEF_ADX __BIT(19) /* ADCX/ADOX instructions */ #define CPUID_SEF_SMAP __BIT(20) /* Supervisor-Mode Access Prevention */ #define CPUID_SEF_AVX512_IFMA __BIT(21) /* AVX-512 Integer Fused Multiply Add */ +/* Bit 22 was PCOMMIT */ #define CPUID_SEF_CLFLUSHOPT __BIT(23) /* Cache Line FLUSH OPTimized */ #define CPUID_SEF_CLWB __BIT(24) /* Cache Line Write Back */ #define CPUID_SEF_PT __BIT(25) /* Processor Trace */ @@ -414,7 +415,7 @@ "\35" "L1D_FLUSH" "\36" "ARCH_CAP" "\40" "SSBD" /* - * CPUID Processor extended state Enumeration Fn000d + * Intel/AMD CPUID Processor extended state Enumeration Fn000d * * %ecx == 0: supported features info: * %eax: Valid bits of lower 32bits of XCR0
CVS commit: src/sys/arch/x86/include
Module Name:src
Committed By: msaitoh
Date: Thu Nov 15 03:50:22 UTC 2018
Modified Files:
src/sys/arch/x86/include: specialreg.h
Log Message:
Add MAWAU (for BND{LD,ST}X instruction) from the latest Intel SDM.
To generate a diff of this commit:
cvs rdiff -u -r1.131 -r1.132 src/sys/arch/x86/include/specialreg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/include/specialreg.h
diff -u src/sys/arch/x86/include/specialreg.h:1.131 src/sys/arch/x86/include/specialreg.h:1.132
--- src/sys/arch/x86/include/specialreg.h:1.131 Sat Nov 10 10:52:51 2018
+++ src/sys/arch/x86/include/specialreg.h Thu Nov 15 03:50:22 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: specialreg.h,v 1.131 2018/11/10 10:52:51 maxv Exp $ */
+/* $NetBSD: specialreg.h,v 1.132 2018/11/15 03:50:22 msaitoh Exp $ */
/*-
* Copyright (c) 1991 The Regents of the University of California.
@@ -386,16 +386,18 @@
#define CPUID_SEF_AVX512_VNNI __BIT(11) /* Vector neural Network Instruction */
#define CPUID_SEF_AVX512_BITALG __BIT(12)
#define CPUID_SEF_AVX512_VPOPCNTDQ __BIT(14)
+#define CPUID_SEF_MAWAU __BITS(21, 17) /* MAWAU for BND{LD,ST}X */
#define CPUID_SEF_RDPID __BIT(22) /* RDPID and IA32_TSC_AUX */
#define CPUID_SEF_SGXLC __BIT(30) /* SGX Launch Configuration */
-#define CPUID_SEF_FLAGS1 "\20" \
- "\1" "PREFETCHWT1" "\2" "AVX512_VBMI" "\3" "UMIP" "\4" "PKU" \
- "\5" "OSPKE" "\7" "AVX512_VBMI2" \
- "\11" "GFNI" "\12" "VAES" "\13" "VPCLMULQDQ" "\14" "AVX512_VNNI"\
- "\15" "AVX512_BITALG" "\17" "AVX512_VPOPCNTDQ" \
- "\27" "RDPID" \
- "\37" "SGXLC"
+#define CPUID_SEF_FLAGS1 "\177\20" \
+ "b\0PREFETCHWT1\0" "b\1AVX512_VBMI\0" "b\2UMIP\0" "b\3PKU\0" \
+ "b\4OSPKE\0" "b\6AVX512_VBMI2\0" \
+ "b\10GFNI\0" "b\11VAES\0" "b\12VPCLMULQDQ\0" "b\13AVX512_VNNI\0"\
+ "b\14AVX512_BITALG\0" "b\16AVX512_VPOPCNTDQ\0" \
+ "f\21\5MAWAU\0" \
+ "b\26RDPID\0" \
+ "b\36SGXLC\0"
/* %edx */
#define CPUID_SEF_AVX512_4VNNIW __BIT(2)
CVS commit: src/sys/arch/x86/include
Module Name:src
Committed By: pgoyette
Date: Mon Jul 16 07:07:30 UTC 2018
Modified Files:
src/sys/arch/x86/include: cpu.h
Log Message:
More rearrangement of struct cpu_info to keep all the un-conditional
members at fixed locations.
Should address my PR kern/52919
OK maxv@
XXX kernel version bump coming momentarily.
To generate a diff of this commit:
cvs rdiff -u -r1.95 -r1.96 src/sys/arch/x86/include/cpu.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/include/cpu.h
diff -u src/sys/arch/x86/include/cpu.h:1.95 src/sys/arch/x86/include/cpu.h:1.96
--- src/sys/arch/x86/include/cpu.h:1.95 Sun Jul 15 08:47:43 2018
+++ src/sys/arch/x86/include/cpu.h Mon Jul 16 07:07:30 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu.h,v 1.95 2018/07/15 08:47:43 maxv Exp $ */
+/* $NetBSD: cpu.h,v 1.96 2018/07/16 07:07:30 pgoyette Exp $ */
/*
* Copyright (c) 1990 The Regents of the University of California.
@@ -127,9 +127,6 @@ struct cpu_info {
uint64_t ci_scratch;
uintptr_t ci_pmap_data[128 / sizeof(uintptr_t)];
-#ifdef XEN
- u_long ci_evtmask[NR_EVENT_CHANNELS]; /* events allowed on this CPU */
-#endif
struct intrsource *ci_isources[MAX_INTR_SOURCES];
volatile int ci_mtx_count; /* Negative count of spin mutexes */
@@ -174,6 +171,44 @@ struct cpu_info {
u_int ci_cflush_lsize; /* CLFLUSH insn line size */
struct x86_cache_info ci_cinfo[CAI_COUNT];
+ device_t ci_frequency; /* Frequency scaling technology */
+ device_t ci_padlock; /* VIA PadLock private storage */
+ device_t ci_temperature; /* Intel coretemp(4) or equivalent */
+ device_t ci_vm; /* Virtual machine guest driver */
+
+ /*
+ * Segmentation-related data.
+ */
+ union descriptor *ci_gdt;
+ struct cpu_tss *ci_tss; /* Per-cpu TSSes; shared among LWPs */
+ int ci_tss_sel; /* TSS selector of this cpu */
+
+ /*
+ * The following two are actually region_descriptors,
+ * but that would pollute the namespace.
+ */
+ uintptr_t ci_suspend_gdt;
+ uint16_t ci_suspend_gdt_padding;
+ uintptr_t ci_suspend_idt;
+ uint16_t ci_suspend_idt_padding;
+
+ uint16_t ci_suspend_tr;
+ uint16_t ci_suspend_ldt;
+ uintptr_t ci_suspend_fs;
+ uintptr_t ci_suspend_gs;
+ uintptr_t ci_suspend_kgs;
+ uintptr_t ci_suspend_efer;
+ uintptr_t ci_suspend_reg[12];
+ uintptr_t ci_suspend_cr0;
+ uintptr_t ci_suspend_cr2;
+ uintptr_t ci_suspend_cr3;
+ uintptr_t ci_suspend_cr4;
+ uintptr_t ci_suspend_cr8;
+
+ /* The following must be in a single cache line. */
+ int ci_want_resched __aligned(64);
+ int ci_padout __aligned(64);
+
#ifndef __HAVE_DIRECT_MAP
#define VPAGE_SRC 0
#define VPAGE_DST 1
@@ -201,42 +236,24 @@ struct cpu_info {
vaddr_t ci_svs_utls;
#endif
-#if defined(XEN) && (defined(PAE) || defined(__x86_64__))
+#if defined(XEN)
+#if defined(PAE) || defined(__x86_64__)
/* Currently active user PGD (can't use rcr3() with Xen) */
pd_entry_t * ci_kpm_pdir; /* per-cpu PMD (va) */
paddr_t ci_kpm_pdirpa; /* per-cpu PMD (pa) */
kmutex_t ci_kpm_mtx;
+#endif /* defined(PAE) || defined(__x86_64__) */
+
#if defined(__x86_64__)
/* per-cpu version of normal_pdes */
pd_entry_t * ci_normal_pdes[3]; /* Ok to hardcode. only for x86_64 && XEN */
paddr_t ci_xen_current_user_pgd;
-#endif /* __x86_64__ */
-#endif /* XEN et.al */
-
-#ifdef XEN
- size_t ci_xpq_idx;
-#endif
+#endif /* defined(__x86_64__) */
-#ifndef XEN
- struct evcnt ci_ipi_events[X86_NIPI];
-#else /* XEN */
+ u_long ci_evtmask[NR_EVENT_CHANNELS]; /* events allowed on this CPU */
struct evcnt ci_ipi_events[XEN_NIPIS];
evtchn_port_t ci_ipi_evtchn;
-#endif /* XEN */
-
- device_t ci_frequency; /* Frequency scaling technology */
- device_t ci_padlock; /* VIA PadLock private storage */
- device_t ci_temperature; /* Intel coretemp(4) or equivalent */
- device_t ci_vm; /* Virtual machine guest driver */
-
- /*
- * Segmentation-related data.
- */
- union descriptor *ci_gdt;
- struct cpu_tss *ci_tss; /* Per-cpu TSSes; shared among LWPs */
- int ci_tss_sel; /* TSS selector of this cpu */
-
-#ifdef XEN
+ size_t ci_xpq_idx;
/* Xen raw system time at which we last ran hardclock. */
uint64_t ci_xen_hardclock_systime_ns;
@@ -263,33 +280,10 @@ struct cpu_info {
struct evcnt ci_xen_raw_systime_backwards_evcnt;
struct evcnt ci_xen_systime_backwards_hardclock_evcnt;
struct evcnt ci_xen_missed_hardclock_evcnt;
-#endif
-
- /*
- * The following two are actually region_descriptors,
- * but that would pollute the namespace.
- */
- uintptr_t ci_suspend_gdt;
- uint16_t ci_suspend_gdt_padding;
- uintptr_t ci_suspend_idt;
- uint16_t ci_suspend_idt_padding;
-
- uint16_t ci_suspend_tr;
- uint16_t ci_suspend_ldt;
- uintptr_t ci_suspend_fs;
- uintptr_t ci_suspend_gs;
- uintptr_t ci_suspend_kgs;
- uintptr_t ci_suspend_efer;
- uintptr_t ci_suspend_reg[12];
- uintptr_t ci_suspend_cr0;
- uintptr_t ci_suspend_cr2;
- uintptr_t ci_suspend_cr3;
- uintptr_t ci_suspend_cr4;
- uintptr_t
CVS commit: src/sys/arch/x86/include
Module Name:src
Committed By: maxv
Date: Sun Jul 15 08:47:43 UTC 2018
Modified Files:
src/sys/arch/x86/include: cpu.h
Log Message:
Hum. Move the __HAVE_DIRECT_MAP block a little below, otherwise dynamically
loaded kernel modules use a wrong offset for some ci_* fields. Found when
modloading tprof_amd on an AMD 10h, the read of ci_signature was at a
wrong address, and the cpu family was not detected correctly.
To generate a diff of this commit:
cvs rdiff -u -r1.94 -r1.95 src/sys/arch/x86/include/cpu.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/include/cpu.h
diff -u src/sys/arch/x86/include/cpu.h:1.94 src/sys/arch/x86/include/cpu.h:1.95
--- src/sys/arch/x86/include/cpu.h:1.94 Sat Jun 30 14:21:19 2018
+++ src/sys/arch/x86/include/cpu.h Sun Jul 15 08:47:43 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu.h,v 1.94 2018/06/30 14:21:19 riastradh Exp $ */
+/* $NetBSD: cpu.h,v 1.95 2018/07/15 08:47:43 maxv Exp $ */
/*
* Copyright (c) 1990 The Regents of the University of California.
@@ -135,16 +135,6 @@ struct cpu_info {
volatile int ci_mtx_count; /* Negative count of spin mutexes */
volatile int ci_mtx_oldspl; /* Old SPL at this ci_idepth */
-#ifndef __HAVE_DIRECT_MAP
-#define VPAGE_SRC 0
-#define VPAGE_DST 1
-#define VPAGE_ZER 2
-#define VPAGE_PTP 3
-#define VPAGE_MAX 4
- vaddr_t vpage[VPAGE_MAX];
- pt_entry_t *vpage_pte[VPAGE_MAX];
-#endif
-
/* The following must be aligned for cmpxchg8b. */
struct {
uint32_t ipending;
@@ -184,6 +174,16 @@ struct cpu_info {
u_int ci_cflush_lsize; /* CLFLUSH insn line size */
struct x86_cache_info ci_cinfo[CAI_COUNT];
+#ifndef __HAVE_DIRECT_MAP
+#define VPAGE_SRC 0
+#define VPAGE_DST 1
+#define VPAGE_ZER 2
+#define VPAGE_PTP 3
+#define VPAGE_MAX 4
+ vaddr_t vpage[VPAGE_MAX];
+ pt_entry_t *vpage_pte[VPAGE_MAX];
+#endif
+
#ifdef PAE
uint32_t ci_pae_l3_pdirpa; /* PA of L3 PD */
pd_entry_t * ci_pae_l3_pdir; /* VA pointer to L3 PD */
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: msaitoh Date: Thu May 31 03:29:01 UTC 2018 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: Fix the bit location of SSBD in the macro for snprintb. To generate a diff of this commit: cvs rdiff -u -r1.125 -r1.126 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/x86/include/specialreg.h diff -u src/sys/arch/x86/include/specialreg.h:1.125 src/sys/arch/x86/include/specialreg.h:1.126 --- src/sys/arch/x86/include/specialreg.h:1.125 Wed May 23 07:24:37 2018 +++ src/sys/arch/x86/include/specialreg.h Thu May 31 03:29:01 2018 @@ -1,4 +1,4 @@ -/* $NetBSD: specialreg.h,v 1.125 2018/05/23 07:24:37 maxv Exp $ */ +/* $NetBSD: specialreg.h,v 1.126 2018/05/31 03:29:01 msaitoh Exp $ */ /*- * Copyright (c) 1991 The Regents of the University of California. @@ -405,9 +405,10 @@ #define CPUID_SEF_ARCH_CAP __BIT(29) /* IA32_ARCH_CAPABILITIES */ #define CPUID_SEF_SSBD __BIT(31) /* Speculative Store Bypass Disable */ -#define CPUID_SEF_FLAGS2 \ - "\20" "\3" "AVX512_4VNNIW" "\4" "AVX512_4FMAPS" \ - "\33" "IBRS" "\34" "STIBP" "\36" "ARCH_CAP" "\38" "SSBD" +#define CPUID_SEF_FLAGS2 "\20" \ +"\3" "AVX512_4VNNIW" "\4" "AVX512_4FMAPS" \ + "\33" "IBRS" "\34" "STIBP" \ + "\36" "ARCH_CAP" "\40" "SSBD" /* * CPUID Processor extended state Enumeration Fn000d
CVS commit: src/sys/arch/x86/include
Module Name:src
Committed By: maxv
Date: Wed May 23 07:24:38 UTC 2018
Modified Files:
src/sys/arch/x86/include: cpu_extended_state.h specialreg.h
Log Message:
Clean up the FPU headers.
To generate a diff of this commit:
cvs rdiff -u -r1.15 -r1.16 src/sys/arch/x86/include/cpu_extended_state.h
cvs rdiff -u -r1.124 -r1.125 src/sys/arch/x86/include/specialreg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/include/cpu_extended_state.h
diff -u src/sys/arch/x86/include/cpu_extended_state.h:1.15 src/sys/arch/x86/include/cpu_extended_state.h:1.16
--- src/sys/arch/x86/include/cpu_extended_state.h:1.15 Wed Nov 8 17:55:54 2017
+++ src/sys/arch/x86/include/cpu_extended_state.h Wed May 23 07:24:37 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu_extended_state.h,v 1.15 2017/11/08 17:55:54 maxv Exp $ */
+/* $NetBSD: cpu_extended_state.h,v 1.16 2018/05/23 07:24:37 maxv Exp $ */
#ifndef _X86_CPU_EXTENDED_STATE_H_
#define _X86_CPU_EXTENDED_STATE_H_
@@ -18,8 +18,8 @@
* This includes registers (etc) used by SSE/SSE2/SSE3/SSSE3/SSE4 and the later
* AVX instructions.
*
- * The definitions are such that any future 'extended state' should be handled
- * (provided the kernel doesn't need to know the actual contents).
+ * The definitions are such that any future 'extended state' should be handled,
+ * provided the kernel doesn't need to know the actual contents.
*
* The actual structures the cpu accesses must be aligned to 16 bytes for FXSAVE
* and 64 for XSAVE. The types aren't aligned because copies do not need extra
@@ -30,18 +30,18 @@
* support the fxsave instruction.
*
* Associated save instructions:
- * FNSAVE: Saves x87 state in 108 bytes (original i387 layout).
- * Then reinitializes the fpu.
+ * FNSAVE: Saves x87 state in 108 bytes (original i387 layout). Then
+ * reinitializes the fpu.
* FSAVE:Encodes to FWAIT followed by FNSAVE.
- * FXSAVE: Saves the x87 state and XMM (aka SSE) registers to the
- * first 448 (max) bytes of a 512 byte area.
- * This layout does not match that written by FNSAVE.
- * XSAVE:Uses the same layout for the x87 and XMM registers,
- * followed by a 64byte header and separate save areas
- * for additional extended cpu state.
- * The x87 state is always saved, the others conditionally.
- * XSAVEOPT: As XSAVE but only writes the registers blocks that have been
- * modified.
+ * FXSAVE: Saves the x87 state and XMM (aka SSE) registers to the first
+ * 448 (max) bytes of a 512 byte area. This layout does not match
+ * that written by FNSAVE.
+ * XSAVE:Uses the same layout for the x87 and XMM registers, followed by
+ * a 64byte header and separate save areas for additional extended
+ * cpu states. The x87 state is always saved, the others
+ * conditionally.
+ * XSAVEOPT: Same as XSAVE but only writes the registers blocks that have
+ * been modified.
*/
/*
@@ -80,10 +80,11 @@ struct ymmreg {
};
/*
- * Floating point unit registers (fsave instruction).
- * The s87_ac[] and fx_87_ac[] are relative to the stack top.
- * The 'tag word' contains 2 bits per register and refers to absolute register
- * numbers.
+ * Floating point unit registers (FSAVE instruction).
+ *
+ * The s87_ac[] and fx_87_ac[] are relative to the stack top. The 'tag word'
+ * contains 2 bits per register and refers to absolute register numbers.
+ *
* The cpu sets the tag values 0b01 (zero) and 0b10 (special) when a value
* is loaded. The software need only set 0b00 (used) and 0xb11 (unused).
* The fxsave 'Abridged tag word' in inverted.
@@ -100,7 +101,7 @@ struct save87 {
__CTASSERT_NOLINT(sizeof(struct save87) == 108);
/*
- * FPU/MMX/SSE/SSE2 context
+ * FPU/MMX/SSE/SSE2 context (FXSAVE instruction).
*/
struct fxsave {
uint16_t fx_cw; /* FPU Control Word */
@@ -122,7 +123,7 @@ __CTASSERT_NOLINT(sizeof(struct fxsave)
* For XSAVE, a 64byte header follows the fxsave data.
*/
struct xsave_header {
- uint8_t xsh_fxsave[512]; /* to align in the union */
+ uint8_t xsh_fxsave[512]; /* struct fxsave */
uint64_t xsh_xstate_bv; /* bitmap of saved sub structures */
uint64_t xsh_xcomp_bv; /* bitmap of compact sub structures */
uint8_t xsh_rsrvd[8]; /* must be zero */
@@ -145,10 +146,10 @@ __CTASSERT(sizeof(struct xsave_ymm) == 2
* NB: Some userspace stuff (eg firefox) uses it to parse ucontext.
*/
union savefpu {
- struct save87 sv_87;
- struct fxsave sv_xmm;
+ struct save87 sv_87;
+ struct fxsave sv_xmm;
#ifdef _KERNEL
- struct xsave_header sv_xsave_hdr;
+ struct xsave_header sv_xsave_hdr;
#endif
};
Index: src/sys/arch/x86/include/specialreg.h
diff -u src/sys/arch/x86/include/specialreg.h:1.124 src/sys/arch/x86/include/specialreg.h:1.125
--- src/sys/arch/x86/include/specialreg.h:1.124 Tue
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: maxv Date: Tue May 22 07:24:08 UTC 2018 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: Add RSBA. When set, it indicates that the CPU is vulnerable to SpectreV2 via the RSB. To generate a diff of this commit: cvs rdiff -u -r1.121 -r1.122 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/x86/include/specialreg.h diff -u src/sys/arch/x86/include/specialreg.h:1.121 src/sys/arch/x86/include/specialreg.h:1.122 --- src/sys/arch/x86/include/specialreg.h:1.121 Tue May 22 07:11:53 2018 +++ src/sys/arch/x86/include/specialreg.h Tue May 22 07:24:08 2018 @@ -1,4 +1,4 @@ -/* $NetBSD: specialreg.h,v 1.121 2018/05/22 07:11:53 maxv Exp $ */ +/* $NetBSD: specialreg.h,v 1.122 2018/05/22 07:24:08 maxv Exp $ */ /*- * Copyright (c) 1991 The Regents of the University of California. @@ -661,6 +661,7 @@ #define MSR_IA32_ARCH_CAPABILITIES 0x10a #define IA32_ARCH_RDCL_NO 0x01 #define IA32_ARCH_IBRS_ALL 0x02 +#define IA32_ARCH_RSBA 0x04 #define IA32_ARCH_SSB_NO 0x10 #define MSR_BBL_CR_ADDR 0x116 /* PII+ only */ #define MSR_BBL_CR_DECC 0x118 /* PII+ only */
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: jakllsch Date: Sat May 19 16:55:59 UTC 2018 Modified Files: src/sys/arch/x86/include: pmap.h Log Message: remove some remaining uvm_emap(9)-related function prototypes To generate a diff of this commit: cvs rdiff -u -r1.78 -r1.79 src/sys/arch/x86/include/pmap.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/x86/include/pmap.h diff -u src/sys/arch/x86/include/pmap.h:1.78 src/sys/arch/x86/include/pmap.h:1.79 --- src/sys/arch/x86/include/pmap.h:1.78 Sat May 19 11:39:37 2018 +++ src/sys/arch/x86/include/pmap.h Sat May 19 16:55:59 2018 @@ -1,4 +1,4 @@ -/* $NetBSD: pmap.h,v 1.78 2018/05/19 11:39:37 jdolecek Exp $ */ +/* $NetBSD: pmap.h,v 1.79 2018/05/19 16:55:59 jakllsch Exp $ */ /* * Copyright (c) 1997 Charles D. Cranor and Washington University. @@ -317,10 +317,6 @@ void pmap_ldt_cleanup(struct lwp *); void pmap_ldt_sync(struct pmap *); void pmap_kremove_local(vaddr_t, vsize_t); -void pmap_emap_enter(vaddr_t, paddr_t, vm_prot_t); -void pmap_emap_remove(vaddr_t, vsize_t); -void pmap_emap_sync(bool); - #define __HAVE_PMAP_PV_TRACK 1 void pmap_pv_init(void); void pmap_pv_track(paddr_t, psize_t);
CVS commit: src/sys/arch/x86/include
Module Name:src
Committed By: nonaka
Date: Fri Apr 13 11:24:34 UTC 2018
Modified Files:
src/sys/arch/x86/include: bootinfo.h
Log Message:
x86: Increase BOOTINFO_MAXSIZE to 8Kib.
Proposed on port-i386 and port-amd64 with no objections:
http://mail-index.netbsd.org/port-i386/2018/04/11/msg003692.html
http://mail-index.netbsd.org/port-amd64/2018/04/11/msg002697.html
To generate a diff of this commit:
cvs rdiff -u -r1.28 -r1.29 src/sys/arch/x86/include/bootinfo.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/include/bootinfo.h
diff -u src/sys/arch/x86/include/bootinfo.h:1.28 src/sys/arch/x86/include/bootinfo.h:1.29
--- src/sys/arch/x86/include/bootinfo.h:1.28 Thu Nov 9 01:01:33 2017
+++ src/sys/arch/x86/include/bootinfo.h Fri Apr 13 11:24:34 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: bootinfo.h,v 1.28 2017/11/09 01:01:33 christos Exp $ */
+/* $NetBSD: bootinfo.h,v 1.29 2018/04/13 11:24:34 nonaka Exp $ */
/*
* Copyright (c) 1997
@@ -251,7 +251,7 @@ struct btinfo_efimemmap {
#ifdef _KERNEL
-#define BOOTINFO_MAXSIZE 4096
+#define BOOTINFO_MAXSIZE 8192
#ifndef _LOCORE
/*
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: maxv Date: Fri Mar 30 19:49:49 UTC 2018 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: Add RDCL_NO and IBRS_ALL. To generate a diff of this commit: cvs rdiff -u -r1.119 -r1.120 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/x86/include/specialreg.h diff -u src/sys/arch/x86/include/specialreg.h:1.119 src/sys/arch/x86/include/specialreg.h:1.120 --- src/sys/arch/x86/include/specialreg.h:1.119 Fri Mar 30 09:30:56 2018 +++ src/sys/arch/x86/include/specialreg.h Fri Mar 30 19:49:49 2018 @@ -1,4 +1,4 @@ -/* $NetBSD: specialreg.h,v 1.119 2018/03/30 09:30:56 msaitoh Exp $ */ +/* $NetBSD: specialreg.h,v 1.120 2018/03/30 19:49:49 maxv Exp $ */ /*- * Copyright (c) 1991 The Regents of the University of California. @@ -658,6 +658,8 @@ #define MSR_IA32_EXT_CONFIG 0x0ee /* Undocumented. Core Solo/Duo only */ #define MSR_MTRRcap 0x0fe #define MSR_IA32_ARCH_CAPABILITIES 0x10a +#define IA32_ARCH_RDCL_NO 0x01 +#define IA32_ARCH_IBRS_ALL 0x02 #define MSR_BBL_CR_ADDR 0x116 /* PII+ only */ #define MSR_BBL_CR_DECC 0x118 /* PII+ only */ #define MSR_BBL_CR_CTL 0x119 /* PII+ only */
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: msaitoh Date: Fri Mar 30 09:30:57 UTC 2018 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: Add Some bit definitions of AMD Fn8001 %edx: - MMX - FXSR To generate a diff of this commit: cvs rdiff -u -r1.118 -r1.119 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/x86/include/specialreg.h diff -u src/sys/arch/x86/include/specialreg.h:1.118 src/sys/arch/x86/include/specialreg.h:1.119 --- src/sys/arch/x86/include/specialreg.h:1.118 Fri Mar 30 09:28:37 2018 +++ src/sys/arch/x86/include/specialreg.h Fri Mar 30 09:30:56 2018 @@ -1,4 +1,4 @@ -/* $NetBSD: specialreg.h,v 1.118 2018/03/30 09:28:37 msaitoh Exp $ */ +/* $NetBSD: specialreg.h,v 1.119 2018/03/30 09:30:56 msaitoh Exp $ */ /*- * Copyright (c) 1991 The Regents of the University of California. @@ -498,6 +498,8 @@ #define CPUID_MPC 0x0008 /* Multiprocessing Capable */ #define CPUID_NOX 0x0010 /* No Execute Page Protection */ #define CPUID_MMXX 0x0040 /* AMD MMX Extensions */ +/* CPUID_MMX MMX supported */ +/* CPUID_FXSR fast FP/MMX save/restore */ #define CPUID_FFXSR 0x0200 /* FXSAVE/FXSTOR Extensions */ /* CPUID_P1GB 1GB Large Page Support */ /* CPUID_RDTSCP Read TSC Pair Instruction */ @@ -506,9 +508,11 @@ #define CPUID_3DNOW 0x8000 /* 3DNow! Instructions */ #define CPUID_EXT_FLAGS "\20" \ - "\14" "SYSCALL/SYSRET" "\24" "MPC" "\25" "NOX" \ - "\27" "MMXX" "\32" "FFXSR" "\33" "P1GB" "\34" "RDTSCP" \ - "\36" "LONG" "\37" "3DNOW2" "\40" "3DNOW" + "\14" "SYSCALL/SYSRET" \ + "\24" "MPC" \ + "\25" "NOX" "\27" "MMXX" "\30" "MMX" \ + "\31" "FXSR" "\32" "FFXSR" "\33" "P1GB" "\34" "RDTSCP" \ + "\36" "LONG" "\37" "3DNOW2" "\40" "3DNOW" /* AMD Fn8001 extended features - %ecx */ /* CPUID_LAHF LAHF/SAHF instruction */
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: msaitoh Date: Fri Mar 30 09:28:37 UTC 2018 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: >From the latest Intel SDM: - Add Intel Fn_0006 %eax new bit 14-20 (HWP stuff). - Intel Fn_0007 %ecx bit 22 is for both RDPID and IA32_TSC_AUX. To generate a diff of this commit: cvs rdiff -u -r1.117 -r1.118 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/x86/include/specialreg.h diff -u src/sys/arch/x86/include/specialreg.h:1.117 src/sys/arch/x86/include/specialreg.h:1.118 --- src/sys/arch/x86/include/specialreg.h:1.117 Wed Mar 14 15:03:16 2018 +++ src/sys/arch/x86/include/specialreg.h Fri Mar 30 09:28:37 2018 @@ -1,4 +1,4 @@ -/* $NetBSD: specialreg.h,v 1.117 2018/03/14 15:03:16 maxv Exp $ */ +/* $NetBSD: specialreg.h,v 1.118 2018/03/30 09:28:37 msaitoh Exp $ */ /*- * Copyright (c) 1991 The Regents of the University of California. @@ -300,12 +300,19 @@ #define CPUID_DSPM_HWP_PLR __BIT(11) /* HWP Package Level Request */ #define CPUID_DSPM_HDC __BIT(13) /* Hardware Duty Cycling */ #define CPUID_DSPM_TBMT3 __BIT(14) /* Turbo Boost Max Technology 3.0 */ +#define CPUID_DSPM_HWP_CAP__BIT(15) /* HWP Capabilities */ +#define CPUID_DSPM_HWP_PECI __BIT(16) /* HWP PECI override */ +#define CPUID_DSPM_HWP_FLEX __BIT(17) /* Flexible HWP */ +#define CPUID_DSPM_HWP_FAST __BIT(18) /* Fast access for IA32_HWP_REQUEST */ +#define CPUID_DSPM_HWP_IGNIDL __BIT(20) /* Ignore Idle Logical Processor HWP */ #define CPUID_DSPM_FLAGS "\20" \ "\1" "DTS" "\2" "IDA" "\3" "ARAT" \ "\5" "PLN" "\6" "ECMD" "\7" "PTM" "\10" "HWP" \ "\11" "HWP_NOTIFY" "\12" "HWP_ACTWIN" "\13" "HWP_EPP" "\14" "HWP_PLR" \ - "\16" "HDC" "\17" "TBM3" + "\16" "HDC" "\17" "TBM3" "\20" "HWP_CAP" \ + "\21" "HWP_PECI" "\22" "HWP_FLEX" "\23" "HWP_FAST" \ + "25" "HWP_IGNIDL" /* * Intel Digital Thermal Sensor and @@ -381,7 +388,7 @@ #define CPUID_SEF_AVX512_VNNI __BIT(11) /* Vector neural Network Instruction */ #define CPUID_SEF_AVX512_BITALG __BIT(12) #define CPUID_SEF_AVX512_VPOPCNTDQ __BIT(14) -#define CPUID_SEF_RDPID __BIT(22) /* ReaD Processor ID */ +#define CPUID_SEF_RDPID __BIT(22) /* RDPID and IA32_TSC_AUX */ #define CPUID_SEF_SGXLC __BIT(30) /* SGX Launch Configuration */ #define CPUID_SEF_FLAGS1 "\20" \
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: maxv Date: Wed Mar 14 15:03:16 UTC 2018 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: ... and also add IBPB ... To generate a diff of this commit: cvs rdiff -u -r1.116 -r1.117 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/x86/include/specialreg.h diff -u src/sys/arch/x86/include/specialreg.h:1.116 src/sys/arch/x86/include/specialreg.h:1.117 --- src/sys/arch/x86/include/specialreg.h:1.116 Wed Mar 14 14:44:25 2018 +++ src/sys/arch/x86/include/specialreg.h Wed Mar 14 15:03:16 2018 @@ -1,4 +1,4 @@ -/* $NetBSD: specialreg.h,v 1.116 2018/03/14 14:44:25 maxv Exp $ */ +/* $NetBSD: specialreg.h,v 1.117 2018/03/14 15:03:16 maxv Exp $ */ /*- * Copyright (c) 1991 The Regents of the University of California. @@ -633,6 +633,7 @@ #define IA32_SPEC_CTRL_IBRS 0x01 #define IA32_SPEC_CTRL_STIBP 0x02 #define MSR_IA32_PRED_CMD 0x049 +#define IA32_PRED_CMD_IBPB 0x01 #define MSR_BIOS_UPDT_TRIG 0x079 #define MSR_BBL_CR_D0 0x088 /* PII+ only */ #define MSR_BBL_CR_D1 0x089 /* PII+ only */
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: maxv Date: Wed Mar 14 14:44:25 UTC 2018 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: Add the IBRS and STIBP MSRs. To generate a diff of this commit: cvs rdiff -u -r1.115 -r1.116 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/x86/include/specialreg.h diff -u src/sys/arch/x86/include/specialreg.h:1.115 src/sys/arch/x86/include/specialreg.h:1.116 --- src/sys/arch/x86/include/specialreg.h:1.115 Wed Mar 14 14:15:02 2018 +++ src/sys/arch/x86/include/specialreg.h Wed Mar 14 14:44:25 2018 @@ -1,4 +1,4 @@ -/* $NetBSD: specialreg.h,v 1.115 2018/03/14 14:15:02 maxv Exp $ */ +/* $NetBSD: specialreg.h,v 1.116 2018/03/14 14:44:25 maxv Exp $ */ /*- * Copyright (c) 1991 The Regents of the University of California. @@ -630,6 +630,8 @@ #define MSR_EBC_FREQUENCY_ID 0x02c /* PIV only */ #define MSR_TEST_CTL 0x033 #define MSR_IA32_SPEC_CTRL 0x048 +#define IA32_SPEC_CTRL_IBRS 0x01 +#define IA32_SPEC_CTRL_STIBP 0x02 #define MSR_IA32_PRED_CMD 0x049 #define MSR_BIOS_UPDT_TRIG 0x079 #define MSR_BBL_CR_D0 0x088 /* PII+ only */
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: maxv Date: Wed Mar 14 14:15:02 UTC 2018 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: Add IC_CFG.DIS_IND: "Disable Indirect Branch Predictor". Available (at least) on AMD Families 10h, 12h and 16h. To generate a diff of this commit: cvs rdiff -u -r1.114 -r1.115 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/x86/include/specialreg.h diff -u src/sys/arch/x86/include/specialreg.h:1.114 src/sys/arch/x86/include/specialreg.h:1.115 --- src/sys/arch/x86/include/specialreg.h:1.114 Mon Mar 12 07:12:54 2018 +++ src/sys/arch/x86/include/specialreg.h Wed Mar 14 14:15:02 2018 @@ -1,4 +1,4 @@ -/* $NetBSD: specialreg.h,v 1.114 2018/03/12 07:12:54 msaitoh Exp $ */ +/* $NetBSD: specialreg.h,v 1.115 2018/03/14 14:15:02 maxv Exp $ */ /*- * Copyright (c) 1991 The Regents of the University of California. @@ -842,6 +842,7 @@ #define MSR_IC_CFG 0xc0011021 #define IC_CFG_DIS_SEQ_PREFETCH 0x0800 +#define IC_CFG_DIS_IND 0x4000 #define MSR_DC_CFG 0xc0011022 #define DC_CFG_DIS_CNV_WC_SSO 0x0008
CVS commit: src/sys/arch/x86/include
Module Name:src
Committed By: msaitoh
Date: Mon Mar 12 07:35:45 UTC 2018
Modified Files:
src/sys/arch/x86/include: cacheinfo.h
Log Message:
AMD L3 cache association bitfield is not 8bit but 4bit like others association
bitfields.
To generate a diff of this commit:
cvs rdiff -u -r1.25 -r1.26 src/sys/arch/x86/include/cacheinfo.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/include/cacheinfo.h
diff -u src/sys/arch/x86/include/cacheinfo.h:1.25 src/sys/arch/x86/include/cacheinfo.h:1.26
--- src/sys/arch/x86/include/cacheinfo.h:1.25 Mon Mar 12 06:20:33 2018
+++ src/sys/arch/x86/include/cacheinfo.h Mon Mar 12 07:35:45 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: cacheinfo.h,v 1.25 2018/03/12 06:20:33 msaitoh Exp $ */
+/* $NetBSD: cacheinfo.h,v 1.26 2018/03/12 07:35:45 msaitoh Exp $ */
#ifndef _X86_CACHEINFO_H_
#define _X86_CACHEINFO_H_
@@ -140,7 +140,7 @@ struct x86_cache_info {
/* L3 Cache */
#define AMD_L3_EDX_C_SIZE(x) x) >> 18) & 0x) * 1024 * 512)
-#define AMD_L3_EDX_C_ASSOC(x) (((x) >> 12) & 0xff)
+#define AMD_L3_EDX_C_ASSOC(x) (((x) >> 12) & 0xf)
#define AMD_L3_EDX_C_LPT(x) (((x) >> 8) & 0xf)
#define AMD_L3_EDX_C_LS(x) ( (x)& 0xff)
CVS commit: src/sys/arch/x86/include
Module Name:src
Committed By: msaitoh
Date: Mon Mar 12 06:20:33 UTC 2018
Modified Files:
src/sys/arch/x86/include: cacheinfo.h
Log Message:
Add 3way and 6way of L2 cache or TLB on AMD CPU.
To generate a diff of this commit:
cvs rdiff -u -r1.24 -r1.25 src/sys/arch/x86/include/cacheinfo.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/include/cacheinfo.h
diff -u src/sys/arch/x86/include/cacheinfo.h:1.24 src/sys/arch/x86/include/cacheinfo.h:1.25
--- src/sys/arch/x86/include/cacheinfo.h:1.24 Fri Mar 9 08:49:32 2018
+++ src/sys/arch/x86/include/cacheinfo.h Mon Mar 12 06:20:33 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: cacheinfo.h,v 1.24 2018/03/09 08:49:32 msaitoh Exp $ */
+/* $NetBSD: cacheinfo.h,v 1.25 2018/03/12 06:20:33 msaitoh Exp $ */
#ifndef _X86_CACHEINFO_H_
#define _X86_CACHEINFO_H_
@@ -342,7 +342,9 @@ __CI_TBL(0, 0,0,
#define AMD_L2CACHE_INFO { \
__CI_TBL(0, 0x01,1, 0, 0, NULL), \
__CI_TBL(0, 0x02,2, 0, 0, NULL), \
+__CI_TBL(0, 0x03,3, 0, 0, NULL), \
__CI_TBL(0, 0x04,4, 0, 0, NULL), \
+__CI_TBL(0, 0x05,6, 0, 0, NULL), \
__CI_TBL(0, 0x06,8, 0, 0, NULL), \
__CI_TBL(0, 0x08, 16, 0, 0, NULL), \
__CI_TBL(0, 0x0a, 32, 0, 0, NULL), \
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: msaitoh Date: Thu Mar 8 04:15:11 UTC 2018 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: Sort entries. No functional change. To generate a diff of this commit: cvs rdiff -u -r1.112 -r1.113 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/x86/include/specialreg.h diff -u src/sys/arch/x86/include/specialreg.h:1.112 src/sys/arch/x86/include/specialreg.h:1.113 --- src/sys/arch/x86/include/specialreg.h:1.112 Mon Mar 5 05:44:07 2018 +++ src/sys/arch/x86/include/specialreg.h Thu Mar 8 04:15:11 2018 @@ -1,4 +1,4 @@ -/* $NetBSD: specialreg.h,v 1.112 2018/03/05 05:44:07 msaitoh Exp $ */ +/* $NetBSD: specialreg.h,v 1.113 2018/03/08 04:15:11 msaitoh Exp $ */ /*- * Copyright (c) 1991 The Regents of the University of California. @@ -435,28 +435,6 @@ #define CPUID_PES1_FLAGS "\20" \ "\1" "XSAVEOPT" "\2" "XSAVEC" "\3" "XGETBV" "\4" "XSAVES" -/* Intel Fn8001 extended features - %edx */ -#define CPUID_SYSCALL 0x0800 /* SYSCALL/SYSRET */ -#define CPUID_XD 0x0010 /* Execute Disable (like CPUID_NOX) */ -#define CPUID_P1GB 0x0400 /* 1GB Large Page Support */ -#define CPUID_RDTSCP 0x0800 /* Read TSC Pair Instruction */ -#define CPUID_EM64T 0x2000 /* Intel EM64T */ - -#define CPUID_INTEL_EXT_FLAGS "\20" \ - "\14" "SYSCALL/SYSRET" "\25" "XD" "\33" "P1GB" \ - "\34" "RDTSCP" "\36" "EM64T" - -/* Intel Fn8001 extended features - %ecx */ -#define CPUID_LAHF 0x0001 /* LAHF/SAHF in IA-32e mode, 64bit sub*/ - /* 0x0020 */ /* LZCNT. Same as AMD's CPUID_LZCNT */ -#define CPUID_PREFETCHW 0x0100 /* PREFETCHW */ - -#define CPUID_INTEL_FLAGS4 "\20"\ - "\1" "LAHF" "\02" "B01" "\03" "B02" \ - "\06" "LZCNT"\ - "\11" "PREFETCHW" - - /* * Intel Deterministic Address Translation Parameter Leaf * Fn_0018 @@ -486,6 +464,28 @@ #define CPUID_DATP_SHAREING __BITS(25, 14) /* shareing */ +/* Intel Fn8001 extended features - %edx */ +#define CPUID_SYSCALL 0x0800 /* SYSCALL/SYSRET */ +#define CPUID_XD 0x0010 /* Execute Disable (like CPUID_NOX) */ +#define CPUID_P1GB 0x0400 /* 1GB Large Page Support */ +#define CPUID_RDTSCP 0x0800 /* Read TSC Pair Instruction */ +#define CPUID_EM64T 0x2000 /* Intel EM64T */ + +#define CPUID_INTEL_EXT_FLAGS "\20" \ + "\14" "SYSCALL/SYSRET" "\25" "XD" "\33" "P1GB" \ + "\34" "RDTSCP" "\36" "EM64T" + +/* Intel Fn8001 extended features - %ecx */ +#define CPUID_LAHF 0x0001 /* LAHF/SAHF in IA-32e mode, 64bit sub*/ + /* 0x0020 */ /* LZCNT. Same as AMD's CPUID_LZCNT */ +#define CPUID_PREFETCHW 0x0100 /* PREFETCHW */ + +#define CPUID_INTEL_FLAGS4 "\20"\ + "\1" "LAHF" "\02" "B01" "\03" "B02" \ + "\06" "LZCNT"\ + "\11" "PREFETCHW" + + /* AMD/VIA Fn8001 extended features - %edx */ /* CPUID_SYSCALL SYSCALL/SYSRET */ #define CPUID_MPC 0x0008 /* Multiprocessing Capable */
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: msaitoh Date: Mon Mar 5 05:44:07 UTC 2018 Modified Files: src/sys/arch/x86/include: cacheinfo.h specialreg.h Log Message: Add Intel Deterministic Address Translation Parameter Leaf(0x18) definitions. To generate a diff of this commit: cvs rdiff -u -r1.22 -r1.23 src/sys/arch/x86/include/cacheinfo.h cvs rdiff -u -r1.111 -r1.112 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/x86/include/cacheinfo.h diff -u src/sys/arch/x86/include/cacheinfo.h:1.22 src/sys/arch/x86/include/cacheinfo.h:1.23 --- src/sys/arch/x86/include/cacheinfo.h:1.22 Wed Apr 27 08:47:03 2016 +++ src/sys/arch/x86/include/cacheinfo.h Mon Mar 5 05:44:07 2018 @@ -1,4 +1,4 @@ -/* $NetBSD: cacheinfo.h,v 1.22 2016/04/27 08:47:03 msaitoh Exp $ */ +/* $NetBSD: cacheinfo.h,v 1.23 2018/03/05 05:44:07 msaitoh Exp $ */ #ifndef _X86_CACHEINFO_H_ #define _X86_CACHEINFO_H_ @@ -333,6 +333,7 @@ __CI_TBL(CAI_L3CACHE, 0xeb, 24,18 * 1 __CI_TBL(CAI_L3CACHE, 0xec, 24,24 * 1024 * 1024, 64, NULL), \ __CI_TBL(CAI_PREFETCH, 0xf0,0, 0, 64, NULL), \ __CI_TBL(CAI_PREFETCH, 0xf1,0, 0,128, NULL), \ +/* 0xfe means no TLB information in CPUID leaf 2 (and use leaf 0x18) */ \ /* 0xff means no cache information in CPUID leaf 2 (and use leaf 4) */ \ __CI_TBL(0, 0,0, 0, 0, NULL) \ } Index: src/sys/arch/x86/include/specialreg.h diff -u src/sys/arch/x86/include/specialreg.h:1.111 src/sys/arch/x86/include/specialreg.h:1.112 --- src/sys/arch/x86/include/specialreg.h:1.111 Mon Jan 15 08:17:20 2018 +++ src/sys/arch/x86/include/specialreg.h Mon Mar 5 05:44:07 2018 @@ -1,4 +1,4 @@ -/* $NetBSD: specialreg.h,v 1.111 2018/01/15 08:17:20 msaitoh Exp $ */ +/* $NetBSD: specialreg.h,v 1.112 2018/03/05 05:44:07 msaitoh Exp $ */ /*- * Copyright (c) 1991 The Regents of the University of California. @@ -456,6 +456,36 @@ "\06" "LZCNT"\ "\11" "PREFETCHW" + +/* + * Intel Deterministic Address Translation Parameter Leaf + * Fn_0018 + */ + +/* %ecx=0 %eax __BITS(31, 0): the maximum input value of supported sub-leaf */ + +/* %ebx */ +#define CPUID_DATP_PGSIZE __BITS(3, 0) /* page size */ +#define CPUID_DATP_PGSIZE_4KB __BIT(0) /* 4KB page support */ +#define CPUID_DATP_PGSIZE_2MB __BIT(1) /* 2MB page support */ +#define CPUID_DATP_PGSIZE_4MB __BIT(2) /* 4MB page support */ +#define CPUID_DATP_PGSIZE_1GB __BIT(3) /* 1GB page support */ +#define CPUID_DATP_PARTITIONING __BITS(10, 8) /* Partitioning */ +#define CPUID_DATP_WAYS __BITS(31, 16) /* Ways of associativity */ + +/* Number of sets: %ecx */ + +/* %edx */ +#define CPUID_DATP_TCTYPE __BITS(4, 0) /* Translation Cache type */ +#define CPUID_DATP_TCTYPE_N 0 /* NULL (not valid) */ +#define CPUID_DATP_TCTYPE_D 1 /* Data TLB */ +#define CPUID_DATP_TCTYPE_I 2 /* Instruction TLB */ +#define CPUID_DATP_TCTYPE_U 3 /* Unified TLB */ +#define CPUID_DATP_TCLEVEL __BITS(7, 5) /* TLB level (start at 1) */ +#define CPUID_DATP_FULLASSOC __BIT(8) /* Full associative */ +#define CPUID_DATP_SHAREING __BITS(25, 14) /* shareing */ + + /* AMD/VIA Fn8001 extended features - %edx */ /* CPUID_SYSCALL SYSCALL/SYSRET */ #define CPUID_MPC 0x0008 /* Multiprocessing Capable */
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: kamil Date: Sat Feb 17 13:01:23 UTC 2018 Modified Files: src/sys/arch/x86/include: Makefile Log Message: Stop installing dbregs.h This is now kernel-only header. The behavior is well specified by the CPU documents and we don't introduce changes to it. Noted by To generate a diff of this commit: cvs rdiff -u -r1.21 -r1.22 src/sys/arch/x86/include/Makefile Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/x86/include/Makefile diff -u src/sys/arch/x86/include/Makefile:1.21 src/sys/arch/x86/include/Makefile:1.22 --- src/sys/arch/x86/include/Makefile:1.21 Thu Dec 15 12:04:18 2016 +++ src/sys/arch/x86/include/Makefile Sat Feb 17 13:01:23 2018 @@ -1,4 +1,4 @@ -# $NetBSD: Makefile,v 1.21 2016/12/15 12:04:18 kamil Exp $ +# $NetBSD: Makefile,v 1.22 2018/02/17 13:01:23 kamil Exp $ INCSDIR=/usr/include/x86 @@ -11,7 +11,6 @@ INCS= aout_machdep.h \ cpu_ucode.h \ cputypes.h \ cpuvar.h \ - dbregs.h \ float.h \ fpu.h \ ieee.h ieeefp.h \
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: msaitoh Date: Mon Jan 15 08:17:20 UTC 2018 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: Add IA32_SPEC_CTRL MSR and IA32_PRED_CMD MSR. To generate a diff of this commit: cvs rdiff -u -r1.110 -r1.111 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/x86/include/specialreg.h diff -u src/sys/arch/x86/include/specialreg.h:1.110 src/sys/arch/x86/include/specialreg.h:1.111 --- src/sys/arch/x86/include/specialreg.h:1.110 Mon Jan 15 07:19:00 2018 +++ src/sys/arch/x86/include/specialreg.h Mon Jan 15 08:17:20 2018 @@ -1,4 +1,4 @@ -/* $NetBSD: specialreg.h,v 1.110 2018/01/15 07:19:00 msaitoh Exp $ */ +/* $NetBSD: specialreg.h,v 1.111 2018/01/15 08:17:20 msaitoh Exp $ */ /*- * Copyright (c) 1991 The Regents of the University of California. @@ -599,6 +599,8 @@ #define MSR_EBL_CR_POWERON 0x02a #define MSR_EBC_FREQUENCY_ID 0x02c /* PIV only */ #define MSR_TEST_CTL 0x033 +#define MSR_IA32_SPEC_CTRL 0x048 +#define MSR_IA32_PRED_CMD 0x049 #define MSR_BIOS_UPDT_TRIG 0x079 #define MSR_BBL_CR_D0 0x088 /* PII+ only */ #define MSR_BBL_CR_D1 0x089 /* PII+ only */
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: msaitoh Date: Mon Jan 15 07:19:00 UTC 2018 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: Add MSR_IA32_ARCH_CAPABILITIES definition. To generate a diff of this commit: cvs rdiff -u -r1.109 -r1.110 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/x86/include/specialreg.h diff -u src/sys/arch/x86/include/specialreg.h:1.109 src/sys/arch/x86/include/specialreg.h:1.110 --- src/sys/arch/x86/include/specialreg.h:1.109 Mon Jan 15 06:08:40 2018 +++ src/sys/arch/x86/include/specialreg.h Mon Jan 15 07:19:00 2018 @@ -1,4 +1,4 @@ -/* $NetBSD: specialreg.h,v 1.109 2018/01/15 06:08:40 msaitoh Exp $ */ +/* $NetBSD: specialreg.h,v 1.110 2018/01/15 07:19:00 msaitoh Exp $ */ /*- * Copyright (c) 1991 The Regents of the University of California. @@ -611,6 +611,7 @@ #define MSR_APERF 0x0e8 #define MSR_IA32_EXT_CONFIG 0x0ee /* Undocumented. Core Solo/Duo only */ #define MSR_MTRRcap 0x0fe +#define MSR_IA32_ARCH_CAPABILITIES 0x10a #define MSR_BBL_CR_ADDR 0x116 /* PII+ only */ #define MSR_BBL_CR_DECC 0x118 /* PII+ only */ #define MSR_BBL_CR_CTL 0x119 /* PII+ only */
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: msaitoh Date: Mon Jan 15 06:08:41 UTC 2018 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: - Add Intel cpuid 7 %edx bit 29 IA32_ARCH_CAPABILITIES supported bit. - Add comment. To generate a diff of this commit: cvs rdiff -u -r1.108 -r1.109 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/x86/include/specialreg.h diff -u src/sys/arch/x86/include/specialreg.h:1.108 src/sys/arch/x86/include/specialreg.h:1.109 --- src/sys/arch/x86/include/specialreg.h:1.108 Sat Jan 13 17:55:57 2018 +++ src/sys/arch/x86/include/specialreg.h Mon Jan 15 06:08:40 2018 @@ -1,4 +1,4 @@ -/* $NetBSD: specialreg.h,v 1.108 2018/01/13 17:55:57 jdolecek Exp $ */ +/* $NetBSD: specialreg.h,v 1.109 2018/01/15 06:08:40 msaitoh Exp $ */ /*- * Copyright (c) 1991 The Regents of the University of California. @@ -322,6 +322,7 @@ * %eax: The Maximum input value for supported subleaf. * %ebx: Feature bits. * %ecx: Feature bits. + * %edx: Feature bits. */ /* %ebx */ @@ -396,10 +397,12 @@ #define CPUID_SEF_AVX512_4FMAPS __BIT(3) #define CPUID_SEF_IBRS __BIT(26) /* IBRS / IBPB Speculation Control */ #define CPUID_SEF_STIBP __BIT(27) /* STIBP Speculation Control */ +#define CPUID_SEF_ARCH_CAP __BIT(29) /* IA32_ARCH_CAPABILITIES */ #define CPUID_SEF_FLAGS2 "\20" \ "\3" "AVX512_4VNNIW" "\4" "AVX512_4FMAPS" \ - "\33" "IBRS" "\34" "STIBP" + "\33" "IBRS" "\34" "STIBP" \ + "\36" "ARCH_CAP" /* * CPUID Processor extended state Enumeration Fn000d
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: jdolecek Date: Sat Jan 13 17:55:57 UTC 2018 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: fix swapped comments for EFER LME and LMA To generate a diff of this commit: cvs rdiff -u -r1.107 -r1.108 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/x86/include/specialreg.h diff -u src/sys/arch/x86/include/specialreg.h:1.107 src/sys/arch/x86/include/specialreg.h:1.108 --- src/sys/arch/x86/include/specialreg.h:1.107 Wed Jan 10 07:04:54 2018 +++ src/sys/arch/x86/include/specialreg.h Sat Jan 13 17:55:57 2018 @@ -1,4 +1,4 @@ -/* $NetBSD: specialreg.h,v 1.107 2018/01/10 07:04:54 msaitoh Exp $ */ +/* $NetBSD: specialreg.h,v 1.108 2018/01/13 17:55:57 jdolecek Exp $ */ /*- * Copyright (c) 1991 The Regents of the University of California. @@ -764,8 +764,8 @@ #define MSR_EFER 0xc080 /* Extended feature enable */ #define EFER_SCE 0x0001 /* SYSCALL extension */ -#define EFER_LME 0x0100 /* Long Mode Active */ -#define EFER_LMA 0x0400 /* Long Mode Enabled */ +#define EFER_LME 0x0100 /* Long Mode Enable */ +#define EFER_LMA 0x0400 /* Long Mode Active */ #define EFER_NXE 0x0800 /* No-Execute Enabled */ #define EFER_SVME 0x1000 /* Secure Virtual Machine En. */ #define EFER_LMSLE 0x2000 /* Long Mode Segment Limit E. */
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: msaitoh Date: Wed Jan 10 07:04:54 UTC 2018 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: Add Intel cpuid 7 %edx IBRS(IBPB Speculation Control) and STIBP(STIBP Speculation Control) from OpenBSD. To generate a diff of this commit: cvs rdiff -u -r1.106 -r1.107 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/x86/include/specialreg.h diff -u src/sys/arch/x86/include/specialreg.h:1.106 src/sys/arch/x86/include/specialreg.h:1.107 --- src/sys/arch/x86/include/specialreg.h:1.106 Wed Jan 10 04:45:24 2018 +++ src/sys/arch/x86/include/specialreg.h Wed Jan 10 07:04:54 2018 @@ -1,4 +1,4 @@ -/* $NetBSD: specialreg.h,v 1.106 2018/01/10 04:45:24 msaitoh Exp $ */ +/* $NetBSD: specialreg.h,v 1.107 2018/01/10 07:04:54 msaitoh Exp $ */ /*- * Copyright (c) 1991 The Regents of the University of California. @@ -394,9 +394,12 @@ /* %edx */ #define CPUID_SEF_AVX512_4VNNIW __BIT(2) #define CPUID_SEF_AVX512_4FMAPS __BIT(3) +#define CPUID_SEF_IBRS __BIT(26) /* IBRS / IBPB Speculation Control */ +#define CPUID_SEF_STIBP __BIT(27) /* STIBP Speculation Control */ #define CPUID_SEF_FLAGS2 "\20" \ -"\3" "AVX512_4VNNIW" "\4" "AVX512_4FMAPS" +"\3" "AVX512_4VNNIW" "\4" "AVX512_4FMAPS" \ + "\33" "IBRS" "\34" "STIBP" /* * CPUID Processor extended state Enumeration Fn000d
CVS commit: src/sys/arch/x86/include
Module Name:src
Committed By: msaitoh
Date: Wed Jan 10 04:45:24 UTC 2018
Modified Files:
src/sys/arch/x86/include: specialreg.h
Log Message:
Add comment.
To generate a diff of this commit:
cvs rdiff -u -r1.105 -r1.106 src/sys/arch/x86/include/specialreg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/include/specialreg.h
diff -u src/sys/arch/x86/include/specialreg.h:1.105 src/sys/arch/x86/include/specialreg.h:1.106
--- src/sys/arch/x86/include/specialreg.h:1.105 Thu Oct 19 06:29:16 2017
+++ src/sys/arch/x86/include/specialreg.h Wed Jan 10 04:45:24 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: specialreg.h,v 1.105 2017/10/19 06:29:16 msaitoh Exp $ */
+/* $NetBSD: specialreg.h,v 1.106 2018/01/10 04:45:24 msaitoh Exp $ */
/*-
* Copyright (c) 1991 The Regents of the University of California.
@@ -325,37 +325,37 @@
*/
/* %ebx */
-#define CPUID_SEF_FSGSBASE __BIT(0)
-#define CPUID_SEF_TSC_ADJUST __BIT(1)
-#define CPUID_SEF_SGX __BIT(2)
-#define CPUID_SEF_BMI1 __BIT(3)
-#define CPUID_SEF_HLE __BIT(4)
-#define CPUID_SEF_AVX2 __BIT(5)
-#define CPUID_SEF_FDPEXONLY __BIT(6)
-#define CPUID_SEF_SMEP __BIT(7)
-#define CPUID_SEF_BMI2 __BIT(8)
-#define CPUID_SEF_ERMS __BIT(9)
-#define CPUID_SEF_INVPCID __BIT(10)
-#define CPUID_SEF_RTM __BIT(11)
-#define CPUID_SEF_QM __BIT(12)
-#define CPUID_SEF_FPUCSDS __BIT(13)
-#define CPUID_SEF_MPX __BIT(14)
-#define CPUID_SEF_PQE __BIT(15)
-#define CPUID_SEF_AVX512F __BIT(16)
-#define CPUID_SEF_AVX512DQ __BIT(17)
-#define CPUID_SEF_RDSEED __BIT(18)
-#define CPUID_SEF_ADX __BIT(19)
-#define CPUID_SEF_SMAP __BIT(20)
-#define CPUID_SEF_AVX512_IFMA __BIT(21)
-#define CPUID_SEF_CLFLUSHOPT __BIT(23)
-#define CPUID_SEF_CLWB __BIT(24)
-#define CPUID_SEF_PT __BIT(25)
-#define CPUID_SEF_AVX512PF __BIT(26)
-#define CPUID_SEF_AVX512ER __BIT(27)
-#define CPUID_SEF_AVX512CD __BIT(28)
-#define CPUID_SEF_SHA __BIT(29)
-#define CPUID_SEF_AVX512BW __BIT(30)
-#define CPUID_SEF_AVX512VL __BIT(31)
+#define CPUID_SEF_FSGSBASE __BIT(0) /* {RD,WR}{FS,GS}BASE */
+#define CPUID_SEF_TSC_ADJUST __BIT(1) /* IA32_TSC_ADJUST MSR support */
+#define CPUID_SEF_SGX __BIT(2) /* Software Guard Extentions */
+#define CPUID_SEF_BMI1 __BIT(3) /* advanced bit manipulation ext. 1st grp */
+#define CPUID_SEF_HLE __BIT(4) /* Hardware Lock Elision */
+#define CPUID_SEF_AVX2 __BIT(5) /* Advanced Vector Extensions 2 */
+#define CPUID_SEF_FDPEXONLY __BIT(6) /* x87FPU Data ptr updated only on x87exp */
+#define CPUID_SEF_SMEP __BIT(7) /* Supervisor-Mode Excecution Prevention */
+#define CPUID_SEF_BMI2 __BIT(8) /* advanced bit manipulation ext. 2nd grp */
+#define CPUID_SEF_ERMS __BIT(9) /* Enhanced REP MOVSB/STOSB */
+#define CPUID_SEF_INVPCID __BIT(10) /* INVPCID instruction */
+#define CPUID_SEF_RTM __BIT(11) /* Restricted Transactional Memory */
+#define CPUID_SEF_QM __BIT(12) /* Resource Director Technology Monitoring */
+#define CPUID_SEF_FPUCSDS __BIT(13) /* Deprecate FPU CS and FPU DS values */
+#define CPUID_SEF_MPX __BIT(14) /* Memory Protection Extensions */
+#define CPUID_SEF_PQE __BIT(15) /* Resource Director Technology Allocation */
+#define CPUID_SEF_AVX512F __BIT(16) /* AVX-512 Foundation */
+#define CPUID_SEF_AVX512DQ __BIT(17) /* AVX-512 Double/Quadword */
+#define CPUID_SEF_RDSEED __BIT(18) /* RDSEED instruction */
+#define CPUID_SEF_ADX __BIT(19) /* ADCX/ADOX instructions */
+#define CPUID_SEF_SMAP __BIT(20) /* Supervisor-Mode Access Prevention */
+#define CPUID_SEF_AVX512_IFMA __BIT(21) /* AVX-512 Integer Fused Multiply Add */
+#define CPUID_SEF_CLFLUSHOPT __BIT(23) /* Cache Line FLUSH OPTimized */
+#define CPUID_SEF_CLWB __BIT(24) /* Cache Line Write Back */
+#define CPUID_SEF_PT __BIT(25) /* Processor Trace */
+#define CPUID_SEF_AVX512PF __BIT(26) /* AVX-512 PreFetch */
+#define CPUID_SEF_AVX512ER __BIT(27) /* AVX-512 Exponential and Reciprocal */
+#define CPUID_SEF_AVX512CD __BIT(28) /* AVX-512 Conflict Detection */
+#define CPUID_SEF_SHA __BIT(29) /* SHA Extensions */
+#define CPUID_SEF_AVX512BW __BIT(30) /* AVX-512 Byte and Word */
+#define CPUID_SEF_AVX512VL __BIT(31) /* AVX-512 Vector Length */
#define CPUID_SEF_FLAGS "\20" \
"\1" "FSGSBASE" "\2" "TSCADJUST" "\3" "SGX" "\4" "BMI1" \
@@ -368,20 +368,20 @@
"\35" "AVX512CD""\36" "SHA" "\37" "AVX512BW" "\40" "AVX512VL"
/* %ecx */
-#define CPUID_SEF_PREFETCHWT1 __BIT(0)
-#define CPUID_SEF_AVX512_VBMI __BIT(1)
-#define CPUID_SEF_UMIP __BIT(2)
-#define CPUID_SEF_PKU __BIT(3)
-#define CPUID_SEF_OSPKE __BIT(4)
-#define CPUID_SEF_AVX512_VBMI2 __BIT(6)
+#define CPUID_SEF_PREFETCHWT1 __BIT(0) /* PREFETCHWT1 instruction */
+#define CPUID_SEF_AVX512_VBMI __BIT(1) /* AVX-512 Vector Byte Manipulation */
+#define CPUID_SEF_UMIP __BIT(2) /* User-Mode Instruction prevention */
+#define CPUID_SEF_PKU __BIT(3) /* Protection Keys for User-mode pages */
+#define CPUID_SEF_OSPKE
CVS commit: src/sys/arch/x86/include
Module Name:src
Committed By: maxv
Date: Thu Dec 28 08:30:36 UTC 2017
Modified Files:
src/sys/arch/x86/include: cpu.h
Log Message:
typos
To generate a diff of this commit:
cvs rdiff -u -r1.83 -r1.84 src/sys/arch/x86/include/cpu.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/include/cpu.h
diff -u src/sys/arch/x86/include/cpu.h:1.83 src/sys/arch/x86/include/cpu.h:1.84
--- src/sys/arch/x86/include/cpu.h:1.83 Sat Dec 2 21:04:59 2017
+++ src/sys/arch/x86/include/cpu.h Thu Dec 28 08:30:36 2017
@@ -1,6 +1,6 @@
-/* $NetBSD: cpu.h,v 1.83 2017/12/02 21:04:59 christos Exp $ */
+/* $NetBSD: cpu.h,v 1.84 2017/12/28 08:30:36 maxv Exp $ */
-/*-
+/*
* Copyright (c) 1990 The Regents of the University of California.
* All rights reserved.
*
@@ -101,7 +101,7 @@ struct cpu_info {
struct lwp *ci_fpcurlwp; /* current owner of the FPU */
cpuid_t ci_cpuid; /* our CPU ID */
uint32_t ci_acpiid; /* our ACPI/MADT ID */
- uint32_t ci_initapicid; /* our intitial APIC ID */
+ uint32_t ci_initapicid; /* our initial APIC ID */
/*
* Private members.
@@ -264,7 +264,7 @@ struct cpu_info {
/*
* Processor flag notes: The "primary" CPU has certain MI-defined
* roles (mostly relating to hardclock handling); we distinguish
- * betwen the processor which booted us, and the processor currently
+ * between the processor which booted us, and the processor currently
* holding the "primary" role just to give us the flexibility later to
* change primaries should we be sufficiently twisted.
*/
@@ -504,7 +504,7 @@ void x86_bus_space_mallocok(void);
* 3: maximum frequency
*/
#define CPU_TMLR_FREQUENCY 12 /* int: current frequency */
-#define CPU_TMLR_VOLTAGE 13 /* int: curret voltage */
+#define CPU_TMLR_VOLTAGE 13 /* int: current voltage */
#define CPU_TMLR_PERCENTAGE 14 /* int: current clock percentage */
#define CPU_FPU_SAVE 15 /* int: FPU Instructions layout
* to use this, CPU_OSFXSR must be true
CVS commit: src/sys/arch/x86/include
Module Name:src
Committed By: christos
Date: Sat Dec 2 21:04:59 UTC 2017
Modified Files:
src/sys/arch/x86/include: cpu.h
Log Message:
Add padding to make the 32/64 bit structs the same.
To generate a diff of this commit:
cvs rdiff -u -r1.82 -r1.83 src/sys/arch/x86/include/cpu.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/include/cpu.h
diff -u src/sys/arch/x86/include/cpu.h:1.82 src/sys/arch/x86/include/cpu.h:1.83
--- src/sys/arch/x86/include/cpu.h:1.82 Mon Nov 27 04:10:12 2017
+++ src/sys/arch/x86/include/cpu.h Sat Dec 2 16:04:59 2017
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu.h,v 1.82 2017/11/27 09:10:12 maxv Exp $ */
+/* $NetBSD: cpu.h,v 1.83 2017/12/02 21:04:59 christos Exp $ */
/*-
* Copyright (c) 1990 The Regents of the University of California.
@@ -526,6 +526,7 @@ void x86_bus_space_mallocok(void);
struct disklist {
int dl_nbiosdisks; /* number of bios disks */
+ int dl_unused;
struct biosdisk_info {
int bi_dev; /* BIOS device # (0x80 ..) */
int bi_cyl; /* cylinders on disk */
@@ -535,6 +536,7 @@ struct disklist {
#define BIFLAG_INVALID 0x01
#define BIFLAG_EXTINT13 0x02
int bi_flags;
+ int bi_unused;
} dl_biosdisks[MAX_BIOSDISKS];
int dl_nnativedisks; /* number of native disks */
CVS commit: src/sys/arch/x86/include
Module Name:src
Committed By: maxv
Date: Mon Nov 27 09:10:12 UTC 2017
Modified Files:
src/sys/arch/x86/include: cpu.h
Log Message:
Remove unused fields, there is no alignment we need to enforce.
To generate a diff of this commit:
cvs rdiff -u -r1.81 -r1.82 src/sys/arch/x86/include/cpu.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/include/cpu.h
diff -u src/sys/arch/x86/include/cpu.h:1.81 src/sys/arch/x86/include/cpu.h:1.82
--- src/sys/arch/x86/include/cpu.h:1.81 Thu Nov 23 16:30:50 2017
+++ src/sys/arch/x86/include/cpu.h Mon Nov 27 09:10:12 2017
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu.h,v 1.81 2017/11/23 16:30:50 kamil Exp $ */
+/* $NetBSD: cpu.h,v 1.82 2017/11/27 09:10:12 maxv Exp $ */
/*-
* Copyright (c) 1990 The Regents of the University of California.
@@ -92,8 +92,6 @@ struct cpu_info {
device_t ci_dev; /* pointer to our device */
struct cpu_info *ci_self; /* self-pointer */
volatile struct vcpu_info *ci_vcpu; /* for XEN */
- void *ci_tlog_base; /* Trap log base */
- int32_t ci_tlog_offset; /* Trap log current offset */
/*
* Will be accessed by other CPUs.
@@ -101,18 +99,14 @@ struct cpu_info {
struct cpu_info *ci_next; /* next cpu */
struct lwp *ci_curlwp; /* current owner of the processor */
struct lwp *ci_fpcurlwp; /* current owner of the FPU */
- int _unused1[2];
cpuid_t ci_cpuid; /* our CPU ID */
- int _unused;
uint32_t ci_acpiid; /* our ACPI/MADT ID */
uint32_t ci_initapicid; /* our intitial APIC ID */
/*
* Private members.
*/
- struct evcnt ci_tlb_evcnt; /* tlb shootdown counter */
struct pmap *ci_pmap; /* current pmap */
- int ci_need_tlbwait; /* need to wait for TLB invalidations */
int ci_want_pmapload; /* pmap_load() is needed */
volatile int ci_tlbstate; /* one of TLBSTATE_ states. see below */
#define TLBSTATE_VALID 0 /* all user tlbs are valid */
@@ -156,11 +150,9 @@ struct cpu_info {
uint32_t ci_flags; /* flags; see below */
uint32_t ci_ipis; /* interprocessor interrupts pending */
- uint32_t sc_apic_version; /* local APIC version */
uint32_t ci_signature; /* X86 cpuid type (cpuid.1.%eax) */
uint32_t ci_vendor[4]; /* vendor string */
- uint32_t _unused2;
uint32_t ci_max_cpuid; /* cpuid.0:%eax */
uint32_t ci_max_ext_cpuid; /* cpuid.8000:%eax */
volatile uint32_t ci_lapic_counter;
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: christos Date: Thu Nov 9 01:01:33 UTC 2017 Modified Files: src/sys/arch/x86/include: bootinfo.h Log Message: add "prekern" to the string list. To generate a diff of this commit: cvs rdiff -u -r1.27 -r1.28 src/sys/arch/x86/include/bootinfo.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/x86/include/bootinfo.h diff -u src/sys/arch/x86/include/bootinfo.h:1.27 src/sys/arch/x86/include/bootinfo.h:1.28 --- src/sys/arch/x86/include/bootinfo.h:1.27 Sat Oct 7 06:26:38 2017 +++ src/sys/arch/x86/include/bootinfo.h Wed Nov 8 20:01:33 2017 @@ -1,4 +1,4 @@ -/* $NetBSD: bootinfo.h,v 1.27 2017/10/07 10:26:38 maxv Exp $ */ +/* $NetBSD: bootinfo.h,v 1.28 2017/11/09 01:01:33 christos Exp $ */ /* * Copyright (c) 1997 @@ -44,7 +44,7 @@ #define BTINFO_STR "bootpath", "rootdevice", "bootdisk", "netif", \ "console", "biosgeom", "symtab", "memmap", "bootwedge", "modulelist", \ -"framebuffer", "userconfcommands", "efi", "efimemmap", +"framebuffer", "userconfcommands", "efi", "efimemmap", "prekern", #ifndef _LOCORE
CVS commit: src/sys/arch/x86/include
Module Name:src
Committed By: maxv
Date: Wed Nov 8 17:55:54 UTC 2017
Modified Files:
src/sys/arch/x86/include: cpu_extended_state.h
Log Message:
remove vestige
To generate a diff of this commit:
cvs rdiff -u -r1.14 -r1.15 src/sys/arch/x86/include/cpu_extended_state.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/include/cpu_extended_state.h
diff -u src/sys/arch/x86/include/cpu_extended_state.h:1.14 src/sys/arch/x86/include/cpu_extended_state.h:1.15
--- src/sys/arch/x86/include/cpu_extended_state.h:1.14 Tue Oct 31 18:30:36 2017
+++ src/sys/arch/x86/include/cpu_extended_state.h Wed Nov 8 17:55:54 2017
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu_extended_state.h,v 1.14 2017/10/31 18:30:36 maxv Exp $ */
+/* $NetBSD: cpu_extended_state.h,v 1.15 2017/11/08 17:55:54 maxv Exp $ */
#ifndef _X86_CPU_EXTENDED_STATE_H_
#define _X86_CPU_EXTENDED_STATE_H_
@@ -114,8 +114,7 @@ struct fxsave {
uint32_t fx_mxcsr_mask;
struct fpaccfx fx_87_ac[8]; /* 8 x87 registers */
struct xmmreg fx_xmm[16]; /* XMM regs (8 in 32bit modes) */
- uint8_t fx_rsvd[48];
- uint8_t fx_kernel[48]; /* Not written by the hardware */
+ uint8_t fx_rsvd[96];
} __aligned(16);
__CTASSERT_NOLINT(sizeof(struct fxsave) == 512);
CVS commit: src/sys/arch/x86/include
Module Name:src
Committed By: maxv
Date: Tue Oct 31 18:30:36 UTC 2017
Modified Files:
src/sys/arch/x86/include: cpu_extended_state.h
Log Message:
Remove outdated comment.
To generate a diff of this commit:
cvs rdiff -u -r1.13 -r1.14 src/sys/arch/x86/include/cpu_extended_state.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/include/cpu_extended_state.h
diff -u src/sys/arch/x86/include/cpu_extended_state.h:1.13 src/sys/arch/x86/include/cpu_extended_state.h:1.14
--- src/sys/arch/x86/include/cpu_extended_state.h:1.13 Tue Oct 31 12:02:20 2017
+++ src/sys/arch/x86/include/cpu_extended_state.h Tue Oct 31 18:30:36 2017
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu_extended_state.h,v 1.13 2017/10/31 12:02:20 maxv Exp $ */
+/* $NetBSD: cpu_extended_state.h,v 1.14 2017/10/31 18:30:36 maxv Exp $ */
#ifndef _X86_CPU_EXTENDED_STATE_H_
#define _X86_CPU_EXTENDED_STATE_H_
@@ -203,12 +203,6 @@ union savefpu {
* and then again when it is truncated to 53 bits.
*
* However the C language explicitly allows the extra precision.
- *
- * The iBCS control word has underflow, overflow, zero divide, and invalid
- * operation exceptions unmasked. But that causes an unexpected exception
- * in the test program 'paranoia' and makes denormals useless (DBL_MIN / 2
- * underflows). It doesn't make a lot of sense to trap underflow without
- * trapping denormals.
*/
#define __INITIAL_NPXCW__ 0x037f
/* Modern NetBSD uses the default control word.. */
CVS commit: src/sys/arch/x86/include
Module Name:src
Committed By: maxv
Date: Tue Oct 31 10:39:13 UTC 2017
Modified Files:
src/sys/arch/x86/include: cpu_extended_state.h
Log Message:
Add xsh_xcomp_bv and fx_zero, and use uint8_t instead.
To generate a diff of this commit:
cvs rdiff -u -r1.11 -r1.12 src/sys/arch/x86/include/cpu_extended_state.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/include/cpu_extended_state.h
diff -u src/sys/arch/x86/include/cpu_extended_state.h:1.11 src/sys/arch/x86/include/cpu_extended_state.h:1.12
--- src/sys/arch/x86/include/cpu_extended_state.h:1.11 Thu Aug 10 12:46:31 2017
+++ src/sys/arch/x86/include/cpu_extended_state.h Tue Oct 31 10:39:13 2017
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu_extended_state.h,v 1.11 2017/08/10 12:46:31 maxv Exp $ */
+/* $NetBSD: cpu_extended_state.h,v 1.12 2017/10/31 10:39:13 maxv Exp $ */
#ifndef _X86_CPU_EXTENDED_STATE_H_
#define _X86_CPU_EXTENDED_STATE_H_
@@ -106,6 +106,7 @@ struct fxsave {
uint16_t fx_cw; /* FPU Control Word */
uint16_t fx_sw; /* FPU Status Word */
uint8_t fx_tw; /* FPU Tag Word (abridged) */
+ uint8_t fx_zero; /* zero */
uint16_t fx_opcode; /* FPU Opcode */
union fp_addr fx_ip; /* FPU Instruction Pointer */
union fp_addr fx_dp; /* FPU Data pointer */
@@ -131,10 +132,11 @@ struct fxsave_os {
* For XSAVE, a 64byte header follows the fxsave data.
*/
struct xsave_header {
- uint64_t xsh_fxsave[64]; /* to align in the union */
+ uint8_t xsh_fxsave[512]; /* to align in the union */
uint64_t xsh_xstate_bv; /* bitmap of saved sub structures */
- uint64_t xsh_rsrvd[2]; /* must be zero */
- uint64_t xsh_reserved[5]; /* best if zero */
+ uint64_t xsh_xcomp_bv; /* bitmap of compact sub structures */
+ uint8_t xsh_rsrvd[8]; /* must be zero */
+ uint8_t xsh_reserved[40]; /* best if zero */
};
__CTASSERT(sizeof(struct xsave_header) == 512 + 64);
CVS commit: src/sys/arch/x86/include
Module Name:src
Committed By: msaitoh
Date: Thu Oct 19 06:29:16 UTC 2017
Modified Files:
src/sys/arch/x86/include: specialreg.h
Log Message:
Add the following bits in AMD Fn800a %edx features (SVM features):
PFThreshold (PAUSE filter threshold)
AVIC (AMD virtual interrupt controller)
V_VMSAVE_VMLOAD (virtualized VMSAVE and VMLOAD)
vGIF (virtualized GIF)
To generate a diff of this commit:
cvs rdiff -u -r1.104 -r1.105 src/sys/arch/x86/include/specialreg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/include/specialreg.h
diff -u src/sys/arch/x86/include/specialreg.h:1.104 src/sys/arch/x86/include/specialreg.h:1.105
--- src/sys/arch/x86/include/specialreg.h:1.104 Wed Oct 18 03:38:32 2017
+++ src/sys/arch/x86/include/specialreg.h Thu Oct 19 06:29:16 2017
@@ -1,4 +1,4 @@
-/* $NetBSD: specialreg.h,v 1.104 2017/10/18 03:38:32 msaitoh Exp $ */
+/* $NetBSD: specialreg.h,v 1.105 2017/10/19 06:29:16 msaitoh Exp $ */
/*-
* Copyright (c) 1991 The Regents of the University of California.
@@ -539,13 +539,18 @@
#define CPUID_AMD_SVM_FlushByASID 0x0040
#define CPUID_AMD_SVM_DecodeAssist 0x0080
#define CPUID_AMD_SVM_PauseFilter 0x0400
+#define CPUID_AMD_SVM_PFThreshold 0x0x001000 /* PAUSE filter threshold */
+#define CPUID_AMD_SVM_AVIC 0x2000 /* AMD Virtual intr. ctrl */
+#define CPUID_AMD_SVM_V_VMSAVE_VMLOAD 0x8000 /* Virtual VM{SAVE/LOAD} */
+#define CPUID_AMD_SVM_vGIF 0x0001 /* Virtualized GIF */
#define CPUID_AMD_SVM_FLAGS "\20" \
- "\1" "NP" "\2" "LbrVirt" "\3" "SVML" "\4" "NRIPS" \
- "\5" "TSCRate" "\6" "VMCBCleanBits" \
- "\7" "FlushByASID" "\10" "DecodeAssist" \
+ "\1" "NP" "\2" "LbrVirt" "\3" "SVML" "\4" "NRIPS" \
+ "\5" "TSCRate" "\6" "VMCBCleanBits" \
+ "\7" "FlushByASID" "\10" "DecodeAssist" \
"\11" "B08" "\12" "B09" "\13" "PauseFilter" "\14" "B11" \
- "\15" "B12" "\16" "B13" "\17" "B17" "\20" "B18" \
- "\21" "B19"
+ "\15" "PFThreshold" "\16" "AVIC" "\17" "B14" \
+ "\20" "V_VMSAVE_VMLOAD" \
+ "\21" "VGIF"
/*
* Centaur Extended Feature flags
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: msaitoh Date: Wed Oct 18 03:38:32 UTC 2017 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: Add Turbo Boost Max Technology 3.0 bit. To generate a diff of this commit: cvs rdiff -u -r1.103 -r1.104 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/x86/include/specialreg.h diff -u src/sys/arch/x86/include/specialreg.h:1.103 src/sys/arch/x86/include/specialreg.h:1.104 --- src/sys/arch/x86/include/specialreg.h:1.103 Fri Oct 13 13:53:54 2017 +++ src/sys/arch/x86/include/specialreg.h Wed Oct 18 03:38:32 2017 @@ -1,4 +1,4 @@ -/* $NetBSD: specialreg.h,v 1.103 2017/10/13 13:53:54 msaitoh Exp $ */ +/* $NetBSD: specialreg.h,v 1.104 2017/10/18 03:38:32 msaitoh Exp $ */ /*- * Copyright (c) 1991 The Regents of the University of California. @@ -299,12 +299,13 @@ #define CPUID_DSPM_HWP_EPP __BIT(10) /* HWP Energy Performance Preference */ #define CPUID_DSPM_HWP_PLR __BIT(11) /* HWP Package Level Request */ #define CPUID_DSPM_HDC __BIT(13) /* Hardware Duty Cycling */ +#define CPUID_DSPM_TBMT3 __BIT(14) /* Turbo Boost Max Technology 3.0 */ #define CPUID_DSPM_FLAGS "\20" \ "\1" "DTS" "\2" "IDA" "\3" "ARAT" \ "\5" "PLN" "\6" "ECMD" "\7" "PTM" "\10" "HWP" \ "\11" "HWP_NOTIFY" "\12" "HWP_ACTWIN" "\13" "HWP_EPP" "\14" "HWP_PLR" \ - "\16" "HDC" + "\16" "HDC" "\17" "TBM3" /* * Intel Digital Thermal Sensor and
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: msaitoh Date: Fri Oct 13 13:53:54 UTC 2017 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: Add the following instruction bits in Structured Extended Flags Enumeration Leaf from "Intel Architecture Instruction Set Extensions and Future Features Programming Reference" (319433-030): AVX512_IFMA AVX512_VBMI AVX512_VBMI2 GFNI VAES VPCLMULQDQ AVX512_VNNI AVX512_BITALG AVX512_VPOPCNTDQ AVX512_4VNNIW AVX512_4FMAPS To generate a diff of this commit: cvs rdiff -u -r1.102 -r1.103 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/x86/include/specialreg.h diff -u src/sys/arch/x86/include/specialreg.h:1.102 src/sys/arch/x86/include/specialreg.h:1.103 --- src/sys/arch/x86/include/specialreg.h:1.102 Thu Sep 7 06:40:42 2017 +++ src/sys/arch/x86/include/specialreg.h Fri Oct 13 13:53:54 2017 @@ -1,4 +1,4 @@ -/* $NetBSD: specialreg.h,v 1.102 2017/09/07 06:40:42 msaitoh Exp $ */ +/* $NetBSD: specialreg.h,v 1.103 2017/10/13 13:53:54 msaitoh Exp $ */ /*- * Copyright (c) 1991 The Regents of the University of California. @@ -345,6 +345,7 @@ #define CPUID_SEF_RDSEED __BIT(18) #define CPUID_SEF_ADX __BIT(19) #define CPUID_SEF_SMAP __BIT(20) +#define CPUID_SEF_AVX512_IFMA __BIT(21) #define CPUID_SEF_CLFLUSHOPT __BIT(23) #define CPUID_SEF_CLWB __BIT(24) #define CPUID_SEF_PT __BIT(25) @@ -361,24 +362,41 @@ "\11" "BMI2" "\12" "ERMS" "\13" "INVPCID" "\14" "RTM" \ "\15" "QM" "\16" "FPUCSDS" "\17" "MPX" "\20" "PQE" \ "\21" "AVX512F" "\22" "AVX512DQ" "\23" "RDSEED" "\24" "ADX" \ - "\25" "SMAP" "\30" "CLFLUSHOPT" \ + "\25" "SMAP" "\26" "AVX512_IFMA" "\30" "CLFLUSHOPT" \ "\31" "CLWB" "\32" "PT" "\33" "AVX512PF" "\34" "AVX512ER" \ "\35" "AVX512CD""\36" "SHA" "\37" "AVX512BW" "\40" "AVX512VL" /* %ecx */ #define CPUID_SEF_PREFETCHWT1 __BIT(0) +#define CPUID_SEF_AVX512_VBMI __BIT(1) #define CPUID_SEF_UMIP __BIT(2) #define CPUID_SEF_PKU __BIT(3) #define CPUID_SEF_OSPKE __BIT(4) +#define CPUID_SEF_AVX512_VBMI2 __BIT(6) +#define CPUID_SEF_GFNI __BIT(8) +#define CPUID_SEF_VAES __BIT(9) +#define CPUID_SEF_VPCLMULQDQ __BIT(10) +#define CPUID_SEF_AVX512_VNNI __BIT(11) +#define CPUID_SEF_AVX512_BITALG __BIT(12) +#define CPUID_SEF_AVX512_VPOPCNTDQ __BIT(14) #define CPUID_SEF_RDPID __BIT(22) #define CPUID_SEF_SGXLC __BIT(30) #define CPUID_SEF_FLAGS1 "\20" \ - "\1" "PREFETCHWT1" "\3" "UMIP" "\4" "PKU" \ - "\5" "OSPKE" \ + "\1" "PREFETCHWT1" "\2" "AVX512_VBMI" "\3" "UMIP" "\4" "PKU" \ + "\5" "OSPKE" "\7" "AVX512_VBMI2" \ + "\11" "GFNI" "\12" "VAES" "\13" "VPCLMULQDQ" "\14" "AVX512_VNNI"\ + "\15" "AVX512_BITALG" "\17" "AVX512_VPOPCNTDQ" \ "\27" "RDPID" \ "\37" "SGXLC" +/* %edx */ +#define CPUID_SEF_AVX512_4VNNIW __BIT(2) +#define CPUID_SEF_AVX512_4FMAPS __BIT(3) + +#define CPUID_SEF_FLAGS2 "\20" \ +"\3" "AVX512_4VNNIW" "\4" "AVX512_4FMAPS" + /* * CPUID Processor extended state Enumeration Fn000d *
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: ozaki-r Date: Fri Sep 29 03:17:18 UTC 2017 Modified Files: src/sys/arch/x86/include: pmap.h Log Message: Fix build sys/arch/x86/x86/cpu.c:920:20: error: 'pmap_largepages' undeclared (first use in this function) smp_data.large = (pmap_largepages != 0); ^ To generate a diff of this commit: cvs rdiff -u -r1.67 -r1.68 src/sys/arch/x86/include/pmap.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/x86/include/pmap.h diff -u src/sys/arch/x86/include/pmap.h:1.67 src/sys/arch/x86/include/pmap.h:1.68 --- src/sys/arch/x86/include/pmap.h:1.67 Sat Jun 17 08:07:03 2017 +++ src/sys/arch/x86/include/pmap.h Fri Sep 29 03:17:18 2017 @@ -1,4 +1,4 @@ -/* $NetBSD: pmap.h,v 1.67 2017/06/17 08:07:03 maxv Exp $ */ +/* $NetBSD: pmap.h,v 1.68 2017/09/29 03:17:18 ozaki-r Exp $ */ /* * Copyright (c) 1997 Charles D. Cranor and Washington University. @@ -200,6 +200,7 @@ extern u_long PDPpaddr; extern pd_entry_t pmap_pg_g; /* do we support PG_G? */ extern pd_entry_t pmap_pg_nx; /* do we support PG_NX? */ +extern int pmap_largepages; extern long nkptp[PTP_LEVELS]; /*
CVS commit: src/sys/arch/x86/include
Module Name:src
Committed By: christos
Date: Sat Sep 16 23:55:45 UTC 2017
Modified Files:
src/sys/arch/x86/include: lock.h
Log Message:
more const
To generate a diff of this commit:
cvs rdiff -u -r1.27 -r1.28 src/sys/arch/x86/include/lock.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/include/lock.h
diff -u src/sys/arch/x86/include/lock.h:1.27 src/sys/arch/x86/include/lock.h:1.28
--- src/sys/arch/x86/include/lock.h:1.27 Tue Jan 22 17:09:44 2013
+++ src/sys/arch/x86/include/lock.h Sat Sep 16 19:55:45 2017
@@ -1,4 +1,4 @@
-/* $NetBSD: lock.h,v 1.27 2013/01/22 22:09:44 christos Exp $ */
+/* $NetBSD: lock.h,v 1.28 2017/09/16 23:55:45 christos Exp $ */
/*-
* Copyright (c) 2000, 2006 The NetBSD Foundation, Inc.
@@ -39,13 +39,13 @@
#include
static __inline int
-__SIMPLELOCK_LOCKED_P(__cpu_simple_lock_t *__ptr)
+__SIMPLELOCK_LOCKED_P(const __cpu_simple_lock_t *__ptr)
{
return *__ptr == __SIMPLELOCK_LOCKED;
}
static __inline int
-__SIMPLELOCK_UNLOCKED_P(__cpu_simple_lock_t *__ptr)
+__SIMPLELOCK_UNLOCKED_P(const __cpu_simple_lock_t *__ptr)
{
return *__ptr == __SIMPLELOCK_UNLOCKED;
}
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: maxv Date: Sat Aug 12 12:33:31 UTC 2017 Modified Files: src/sys/arch/x86/include: psl.h Log Message: Don't include opt_vm86.h. To generate a diff of this commit: cvs rdiff -u -r1.9 -r1.10 src/sys/arch/x86/include/psl.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/x86/include/psl.h diff -u src/sys/arch/x86/include/psl.h:1.9 src/sys/arch/x86/include/psl.h:1.10 --- src/sys/arch/x86/include/psl.h:1.9 Sat Aug 12 07:21:57 2017 +++ src/sys/arch/x86/include/psl.h Sat Aug 12 12:33:31 2017 @@ -1,4 +1,4 @@ -/* $NetBSD: psl.h,v 1.9 2017/08/12 07:21:57 maxv Exp $ */ +/* $NetBSD: psl.h,v 1.10 2017/08/12 12:33:31 maxv Exp $ */ /*- * Copyright (c) 1990 The Regents of the University of California. @@ -62,11 +62,6 @@ #define PSL_MBZ 0xffc08028 /* must be zero bits */ #define PSL_USERSET (PSL_MBO | PSL_I) -#ifdef i386 -#if defined(_KERNEL_OPT) -#include "opt_vm86.h" -#endif -#endif #define PSL_USERSTATIC (PSL_MBO | PSL_MBZ | PSL_I | PSL_IOPL | PSL_NT | PSL_VM | PSL_VIF | PSL_VIP) #define PSL_USER (PSL_C | PSL_PF | PSL_AF | PSL_Z | PSL_N | \ PSL_T | PSL_V | PSL_D | PSL_AC)
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: maxv Date: Fri Aug 11 06:27:12 UTC 2017 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: Add a comment about APICBASE_PHYSADDR. Has to do with PR/42597. To generate a diff of this commit: cvs rdiff -u -r1.100 -r1.101 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/x86/include/specialreg.h diff -u src/sys/arch/x86/include/specialreg.h:1.100 src/sys/arch/x86/include/specialreg.h:1.101 --- src/sys/arch/x86/include/specialreg.h:1.100 Tue Jul 11 14:00:15 2017 +++ src/sys/arch/x86/include/specialreg.h Fri Aug 11 06:27:12 2017 @@ -1,4 +1,4 @@ -/* $NetBSD: specialreg.h,v 1.100 2017/07/11 14:00:15 gson Exp $ */ +/* $NetBSD: specialreg.h,v 1.101 2017/08/11 06:27:12 maxv Exp $ */ /*- * Copyright (c) 1991 The Regents of the University of California. @@ -554,6 +554,11 @@ #define APICBASE_BSP 0x0100 /* boot processor */ #define APICBASE_EXTD 0x0400 /* x2APIC mode */ #define APICBASE_EN 0x0800 /* software enable */ +/* + * APICBASE_PHYSADDR is actually variable-sized on some CPUs. But we're + * only interested in the initial value, which is guaranteed to fit the + * first 32 bits. So this macro is fine. + */ #define APICBASE_PHYSADDR 0xf000 /* physical address */ #define MSR_EBL_CR_POWERON 0x02a #define MSR_EBC_FREQUENCY_ID 0x02c /* PIV only */
CVS commit: src/sys/arch/x86/include
Module Name:src
Committed By: maxv
Date: Thu Aug 10 12:46:31 UTC 2017
Modified Files:
src/sys/arch/x86/include: cpu_extended_state.h
Log Message:
Remove the svr4/ibcs2 fpu flags.
To generate a diff of this commit:
cvs rdiff -u -r1.10 -r1.11 src/sys/arch/x86/include/cpu_extended_state.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/include/cpu_extended_state.h
diff -u src/sys/arch/x86/include/cpu_extended_state.h:1.10 src/sys/arch/x86/include/cpu_extended_state.h:1.11
--- src/sys/arch/x86/include/cpu_extended_state.h:1.10 Thu Aug 18 13:00:54 2016
+++ src/sys/arch/x86/include/cpu_extended_state.h Thu Aug 10 12:46:31 2017
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu_extended_state.h,v 1.10 2016/08/18 13:00:54 maxv Exp $ */
+/* $NetBSD: cpu_extended_state.h,v 1.11 2017/08/10 12:46:31 maxv Exp $ */
#ifndef _X86_CPU_EXTENDED_STATE_H_
#define _X86_CPU_EXTENDED_STATE_H_
@@ -225,12 +225,8 @@ union savefpu {
#define __NetBSD_COMPAT_NPXCW__ 0x127f
/* FreeBSD leaves some exceptions unmasked as well. */
#define __FreeBSD_NPXCW__ 0x1272
-/* iBCS2 goes a bit further and leaves the underflow exception unmasked. */
-#define __iBCS2_NPXCW__ 0x0262
/* Linux just uses the default control word. */
#define __Linux_NPXCW__ __INITIAL_NPXCW__
-/* SVR4 uses the same control word as iBCS2. */
-#define __SVR4_NPXCW__ 0x0262
/*
* The default MXCSR value at reset is 0x1f80, IA-32 Instruction
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: gson Date: Tue Jul 11 14:00:16 UTC 2017 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: Fix typo in comment To generate a diff of this commit: cvs rdiff -u -r1.99 -r1.100 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/x86/include/specialreg.h diff -u src/sys/arch/x86/include/specialreg.h:1.99 src/sys/arch/x86/include/specialreg.h:1.100 --- src/sys/arch/x86/include/specialreg.h:1.99 Wed Jun 14 08:45:42 2017 +++ src/sys/arch/x86/include/specialreg.h Tue Jul 11 14:00:15 2017 @@ -1,4 +1,4 @@ -/* $NetBSD: specialreg.h,v 1.99 2017/06/14 08:45:42 maxv Exp $ */ +/* $NetBSD: specialreg.h,v 1.100 2017/07/11 14:00:15 gson Exp $ */ /*- * Copyright (c) 1991 The Regents of the University of California. @@ -130,7 +130,7 @@ #define CPUID_DE 0x0004 /* has debugging extension */ #define CPUID_PSE 0x0008 /* has 4MB page size extension */ #define CPUID_TSC 0x0010 /* has time stamp counter */ -#define CPUID_MSR 0x0020 /* has mode specific registers */ +#define CPUID_MSR 0x0020 /* has model specific registers */ #define CPUID_PAE 0x0040 /* has phys address extension */ #define CPUID_MCE 0x0080 /* has machine check exception */ #define CPUID_CX8 0x0100 /* has CMPXCHG8B instruction */
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: maxv Date: Sat Jun 17 08:07:03 UTC 2017 Modified Files: src/sys/arch/x86/include: pmap.h Log Message: Actually, use slot 456 instead, so that it fits a cache line. To generate a diff of this commit: cvs rdiff -u -r1.66 -r1.67 src/sys/arch/x86/include/pmap.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/x86/include/pmap.h diff -u src/sys/arch/x86/include/pmap.h:1.66 src/sys/arch/x86/include/pmap.h:1.67 --- src/sys/arch/x86/include/pmap.h:1.66 Wed Jun 14 14:17:15 2017 +++ src/sys/arch/x86/include/pmap.h Sat Jun 17 08:07:03 2017 @@ -1,4 +1,4 @@ -/* $NetBSD: pmap.h,v 1.66 2017/06/14 14:17:15 maxv Exp $ */ +/* $NetBSD: pmap.h,v 1.67 2017/06/17 08:07:03 maxv Exp $ */ /* * Copyright (c) 1997 Charles D. Cranor and Washington University. @@ -485,7 +485,7 @@ void pmap_free_ptps(struct vm_page *); #ifdef __HAVE_DIRECT_MAP -#define L4_SLOT_DIRECT 460 +#define L4_SLOT_DIRECT 456 #define PDIR_SLOT_DIRECT L4_SLOT_DIRECT #define NL4_SLOT_DIRECT 32
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: maxv Date: Wed Jun 14 12:49:37 UTC 2017 Modified Files: src/sys/arch/x86/include: pmap.h Log Message: Move the direct map from slot 509 to slot 460. We will increase its size dynamically. To generate a diff of this commit: cvs rdiff -u -r1.64 -r1.65 src/sys/arch/x86/include/pmap.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/x86/include/pmap.h diff -u src/sys/arch/x86/include/pmap.h:1.64 src/sys/arch/x86/include/pmap.h:1.65 --- src/sys/arch/x86/include/pmap.h:1.64 Thu Mar 23 18:08:06 2017 +++ src/sys/arch/x86/include/pmap.h Wed Jun 14 12:49:37 2017 @@ -1,4 +1,4 @@ -/* $NetBSD: pmap.h,v 1.64 2017/03/23 18:08:06 maxv Exp $ */ +/* $NetBSD: pmap.h,v 1.65 2017/06/14 12:49:37 maxv Exp $ */ /* * Copyright (c) 1997 Charles D. Cranor and Washington University. @@ -485,7 +485,7 @@ void pmap_free_ptps(struct vm_page *); #ifdef __HAVE_DIRECT_MAP -#define L4_SLOT_DIRECT 509 +#define L4_SLOT_DIRECT 460 #define PDIR_SLOT_DIRECT L4_SLOT_DIRECT #define PMAP_DIRECT_BASE (VA_SIGN_NEG((L4_SLOT_DIRECT * NBPD_L4)))
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: maxv Date: Wed Jun 14 08:45:42 UTC 2017 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: Add EFER_TCE. This would be an interesting feature to have, since it reduces the indirect cost of invlpg; but I'm not convinced the way we flush upper-levels is correct for this yet. To generate a diff of this commit: cvs rdiff -u -r1.98 -r1.99 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/x86/include/specialreg.h diff -u src/sys/arch/x86/include/specialreg.h:1.98 src/sys/arch/x86/include/specialreg.h:1.99 --- src/sys/arch/x86/include/specialreg.h:1.98 Mon May 15 04:02:52 2017 +++ src/sys/arch/x86/include/specialreg.h Wed Jun 14 08:45:42 2017 @@ -1,4 +1,4 @@ -/* $NetBSD: specialreg.h,v 1.98 2017/05/15 04:02:52 msaitoh Exp $ */ +/* $NetBSD: specialreg.h,v 1.99 2017/06/14 08:45:42 maxv Exp $ */ /*- * Copyright (c) 1991 The Regents of the University of California. @@ -732,6 +732,7 @@ #define EFER_SVME 0x1000 /* Secure Virtual Machine En. */ #define EFER_LMSLE 0x2000 /* Long Mode Segment Limit E. */ #define EFER_FFXSR 0x4000 /* Fast FXSAVE/FXRSTOR En. */ +#define EFER_TCE 0x8000 /* Translation Cache Ext. */ #define MSR_STAR 0xc081 /* 32 bit syscall gate addr */ #define MSR_LSTAR 0xc082 /* 64 bit syscall gate addr */
CVS commit: src/sys/arch/x86/include
Module Name:src
Committed By: msaitoh
Date: Mon May 15 04:02:52 UTC 2017
Modified Files:
src/sys/arch/x86/include: cpu.h specialreg.h
Log Message:
CPUID_CFLUSH bit is not for CFLUSH insn but CLFLUSH insn, so modify comments
and snprintb() sring.
To generate a diff of this commit:
cvs rdiff -u -r1.69 -r1.70 src/sys/arch/x86/include/cpu.h
cvs rdiff -u -r1.97 -r1.98 src/sys/arch/x86/include/specialreg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/include/cpu.h
diff -u src/sys/arch/x86/include/cpu.h:1.69 src/sys/arch/x86/include/cpu.h:1.70
--- src/sys/arch/x86/include/cpu.h:1.69 Fri Apr 14 04:43:47 2017
+++ src/sys/arch/x86/include/cpu.h Mon May 15 04:02:52 2017
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu.h,v 1.69 2017/04/14 04:43:47 kamil Exp $ */
+/* $NetBSD: cpu.h,v 1.70 2017/05/15 04:02:52 msaitoh Exp $ */
/*-
* Copyright (c) 1990 The Regents of the University of California.
@@ -180,7 +180,7 @@ struct cpu_info {
const struct cpu_functions *ci_func; /* start/stop functions */
struct trapframe *ci_ddb_regs;
- u_int ci_cflush_lsize; /* CFLUSH insn line size */
+ u_int ci_cflush_lsize; /* CLFLUSH insn line size */
struct x86_cache_info ci_cinfo[CAI_COUNT];
union descriptor *ci_gdt;
Index: src/sys/arch/x86/include/specialreg.h
diff -u src/sys/arch/x86/include/specialreg.h:1.97 src/sys/arch/x86/include/specialreg.h:1.98
--- src/sys/arch/x86/include/specialreg.h:1.97 Sat Apr 22 04:24:25 2017
+++ src/sys/arch/x86/include/specialreg.h Mon May 15 04:02:52 2017
@@ -1,4 +1,4 @@
-/* $NetBSD: specialreg.h,v 1.97 2017/04/22 04:24:25 nonaka Exp $ */
+/* $NetBSD: specialreg.h,v 1.98 2017/05/15 04:02:52 msaitoh Exp $ */
/*-
* Copyright (c) 1991 The Regents of the University of California.
@@ -144,7 +144,7 @@
#define CPUID_PAT 0x0001 /* Page Attribute Table */
#define CPUID_PSE36 0x0002 /* 36-bit PSE */
#define CPUID_PN 0x0004 /* processor serial number */
-#define CPUID_CFLUSH 0x0008 /* CFLUSH insn supported */
+#define CPUID_CFLUSH 0x0008 /* CLFLUSH insn supported */
#define CPUID_B20 0x0010 /* reserved */
#define CPUID_DS 0x0020 /* Debug Store */
#define CPUID_ACPI 0x0040 /* ACPI performance modulation regs */
@@ -163,7 +163,7 @@
"\5" "TSC" "\6" "MSR" "\7" "PAE" "\10" "MCE" \
"\11" "CX8" "\12" "APIC" "\13" "B10" "\14" "SEP" \
"\15" "MTRR" "\16" "PGE" "\17" "MCA" "\20" "CMOV" \
- "\21" "PAT" "\22" "PSE36" "\23" "PN" "\24" "CFLUSH" \
+ "\21" "PAT" "\22" "PSE36" "\23" "PN" "\24" "CLFLUSH" \
"\25" "B20" "\26" "DS" "\27" "ACPI" "\30" "MMX" \
"\31" "FXSR" "\32" "SSE" "\33" "SSE2" "\34" "SS" \
"\35" "HTT" "\36" "TM" "\37" "IA64" "\40" "SBF"
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: nonaka Date: Fri Apr 28 01:23:58 UTC 2017 Modified Files: src/sys/arch/x86/include: i82489reg.h Log Message: Added AMD extended APIC register space present definition. To generate a diff of this commit: cvs rdiff -u -r1.15 -r1.16 src/sys/arch/x86/include/i82489reg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/x86/include/i82489reg.h diff -u src/sys/arch/x86/include/i82489reg.h:1.15 src/sys/arch/x86/include/i82489reg.h:1.16 --- src/sys/arch/x86/include/i82489reg.h:1.15 Sat Apr 22 04:24:25 2017 +++ src/sys/arch/x86/include/i82489reg.h Fri Apr 28 01:23:58 2017 @@ -1,4 +1,4 @@ -/* $NetBSD: i82489reg.h,v 1.15 2017/04/22 04:24:25 nonaka Exp $ */ +/* $NetBSD: i82489reg.h,v 1.16 2017/04/28 01:23:58 nonaka Exp $ */ /*- * Copyright (c) 1998, 2008 The NetBSD Foundation, Inc. @@ -44,6 +44,7 @@ # define LAPIC_VERSION_LVT_MASK 0x00ff # define LAPIC_VERSION_LVT_SHIFT 16 # define LAPIC_VERSION_DIRECTED_EOI 0x0100 +# define LAPIC_VERSION_EXTAPIC_SPACE 0x8000 #define LAPIC_TPRI 0x080 /* Task Prio. RW */ # define LAPIC_TPRI_MASK 0x00ff
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: nonaka Date: Sat Apr 22 04:25:09 UTC 2017 Modified Files: src/sys/arch/x86/include: i82093reg.h Log Message: Added I/O APIC EOI register definition. To generate a diff of this commit: cvs rdiff -u -r1.4 -r1.5 src/sys/arch/x86/include/i82093reg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/x86/include/i82093reg.h diff -u src/sys/arch/x86/include/i82093reg.h:1.4 src/sys/arch/x86/include/i82093reg.h:1.5 --- src/sys/arch/x86/include/i82093reg.h:1.4 Sat Jan 26 17:37:39 2013 +++ src/sys/arch/x86/include/i82093reg.h Sat Apr 22 04:25:09 2017 @@ -1,4 +1,4 @@ -/* $NetBSD: i82093reg.h,v 1.4 2013/01/26 17:37:39 dyoung Exp $ */ +/* $NetBSD: i82093reg.h,v 1.5 2017/04/22 04:25:09 nonaka Exp $ */ /*- * Copyright (c) 2000 The NetBSD Foundation, Inc. @@ -50,6 +50,8 @@ #define IOAPIC_REG 0x #define IOAPIC_DATA 0x0010 +#define IOAPIC_EOI 0x0040 +#define IOAPIC_EOI_MASK 0x00ff /* * Internal I/O APIC registers.
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: nonaka Date: Sat Apr 22 04:23:17 UTC 2017 Modified Files: src/sys/arch/x86/include: i82489reg.h specialreg.h Log Message: Add x2APIC register definitions. To generate a diff of this commit: cvs rdiff -u -r1.13 -r1.14 src/sys/arch/x86/include/i82489reg.h cvs rdiff -u -r1.95 -r1.96 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/x86/include/i82489reg.h diff -u src/sys/arch/x86/include/i82489reg.h:1.13 src/sys/arch/x86/include/i82489reg.h:1.14 --- src/sys/arch/x86/include/i82489reg.h:1.13 Fri Jul 17 05:16:09 2015 +++ src/sys/arch/x86/include/i82489reg.h Sat Apr 22 04:23:17 2017 @@ -1,4 +1,4 @@ -/* $NetBSD: i82489reg.h,v 1.13 2015/07/17 05:16:09 msaitoh Exp $ */ +/* $NetBSD: i82489reg.h,v 1.14 2017/04/22 04:23:17 nonaka Exp $ */ /*- * Copyright (c) 1998, 2008 The NetBSD Foundation, Inc. @@ -35,29 +35,30 @@ * "local" APIC. */ -#define LAPIC_ID 0x020 /* ID. RW */ +#define LAPIC_ID 0x020 /* ID. (xAPIC: RW, x2APIC: RO) */ # define LAPIC_ID_MASK 0xff00 # define LAPIC_ID_SHIFT 24 -#define LAPIC_VERS 0x030 /* Version. R */ +#define LAPIC_VERS 0x030 /* Version. RO */ # define LAPIC_VERSION_MASK 0x00ff # define LAPIC_VERSION_LVT_MASK 0x00ff # define LAPIC_VERSION_LVT_SHIFT 16 +# define LAPIC_VERSION_DIRECTED_EOI 0x0100 #define LAPIC_TPRI 0x080 /* Task Prio. RW */ # define LAPIC_TPRI_MASK 0x00ff # define LAPIC_TPRI_INT_MASK 0x00f0 # define LAPIC_TPRI_SUB_MASK 0x000f -#define LAPIC_APRI 0x090 /* Arbitration prio R */ +#define LAPIC_APRI 0x090 /* Arbitration prio (xAPIC: RO, x2APIC: NA) */ # define LAPIC_APRI_MASK 0x00ff -#define LAPIC_PPRI 0x0a0 /* Processor prio. R */ +#define LAPIC_PPRI 0x0a0 /* Processor prio. RO */ #define LAPIC_EOI 0x0b0 /* End Int. W */ -#define LAPIC_RRR 0x0c0 /* Remote read R */ -#define LAPIC_LDR 0x0d0 /* Logical dest. RW */ +#define LAPIC_RRR 0x0c0 /* Remote read (xAPIC: RO, x2APIC: NA) */ +#define LAPIC_LDR 0x0d0 /* Logical dest. (xAPIC: RW, x2APIC: RO) */ -#define LAPIC_DFR 0x0e0 /* Dest. format RW */ +#define LAPIC_DFR 0x0e0 /* Dest. format (xAPIC: RW, x2APIC: NA) */ # define LAPIC_DFR_MASK 0xf000 # define LAPIC_DFR_FLAT 0xf000 # define LAPIC_DFR_CLUSTER 0x @@ -70,27 +71,30 @@ # define LAPIC_SVR_SWEN 0x0100 # define LAPIC_SVR_FOCUS 0x0200 # define LAPIC_SVR_FDIS 0x0200 +# define LAPIC_SVR_EOI_BC_DIS 0x1000 -#define LAPIC_ISR 0x100 /* In-Service Status */ -#define LAPIC_TMR 0x180 /* Trigger Mode */ -#define LAPIC_IRR 0x200 /* Interrupt Req */ -#define LAPIC_ESR 0x280 /* Err status. R */ +#define LAPIC_ISR 0x100 /* In-Service Status RO */ +#define LAPIC_TMR 0x180 /* Trigger Mode RO */ +#define LAPIC_IRR 0x200 /* Interrupt Req RO */ +#define LAPIC_ESR 0x280 /* Err status. RW */ -#define LAPIC_ICRLO 0x300 /* Int. cmd. RW */ -# define LAPIC_DLMODE_MASK 0x0700 +#define LAPIC_LVT_CMCI 0x2f0 /* LVT CMCI RW */ + +#define LAPIC_ICRLO 0x300 /* Int. cmd. (xAPIC: RW, x2APIC: RW64) */ +# define LAPIC_DLMODE_MASK 0x0700 /* Delivery Mode */ # define LAPIC_DLMODE_FIXED 0x -# define LAPIC_DLMODE_LOW 0x0100 +# define LAPIC_DLMODE_LOW 0x0100 /* N/A in x2APIC mode */ # define LAPIC_DLMODE_SMI 0x0200 # define LAPIC_DLMODE_NMI 0x0400 # define LAPIC_DLMODE_INIT 0x0500 # define LAPIC_DLMODE_STARTUP 0x0600 -# define LAPIC_DLMODE_EXTINT 0x0700 +# define LAPIC_DLMODE_EXTINT 0x0700 /* N/A in x2APIC mode */ # define LAPIC_DSTMODE_PHYS 0x # define LAPIC_DSTMODE_LOG 0x0800 -# define LAPIC_DLSTAT_BUSY 0x1000 -# define LAPIC_DLSTAT_IDLE 0x +# define LAPIC_DLSTAT_BUSY 0x1000 /* N/A in x2APIC mode */ +# define LAPIC_DLSTAT_IDLE 0x /* N/A in x2APIC mode */ # define LAPIC_LEVEL_MASK 0x4000 # define LAPIC_LEVEL_ASSERT 0x4000 @@ -106,8 +110,7 @@ # define LAPIC_DEST_ALLINCL 0x0008 # define LAPIC_DEST_ALLEXCL 0x000c - -#define LAPIC_ICRHI 0x310 /* Int. cmd. RW */ +#define LAPIC_ICRHI 0x310 /* Int. cmd. (xAPIC: RW, x2APIC: NA) */ #define LAPIC_LVTT 0x320 /* Loc.vec.(timer) RW */ # define LAPIC_LVTT_VEC_MASK 0x00ff @@ -115,9 +118,15 @@ # define LAPIC_LVTT_M 0x0001 # define LAPIC_LVTT_TM 0x0002 -#define LAPIC_TMINT 0x330 /* Loc.vec (Thermal) */ -#define LAPIC_PCINT 0x340 /* Loc.vec (Perf Mon) */ +#define LAPIC_TMINT 0x330 /* Loc.vec (Thermal) RW */ +#define LAPIC_PCINT 0x340 /* Loc.vec (Perf Mon) RW */ #define LAPIC_LVINT0 0x350 /* Loc.vec (LINT0) RW */ +# define LAPIC_LVT_DM_MASK 0x0700 +# define LAPIC_LVT_DM_FIXED 0x +# define LAPIC_LVT_DM_SMI 0x0200 +# define LAPIC_LVT_DM_NMI 0x0400 +# define LAPIC_LVT_DM_INIT 0x0500 +# define LAPIC_LVT_DM_EXTINT 0x0700 # define LAPIC_LVT_MASKED 0x0001 # define
CVS commit: src/sys/arch/x86/include
Module Name:src
Committed By: nonaka
Date: Wed Apr 19 06:43:05 UTC 2017
Modified Files:
src/sys/arch/x86/include: cpuvar.h i82489var.h
Log Message:
remove prototypes of nonexistent function.
To generate a diff of this commit:
cvs rdiff -u -r1.48 -r1.49 src/sys/arch/x86/include/cpuvar.h
cvs rdiff -u -r1.16 -r1.17 src/sys/arch/x86/include/i82489var.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/include/cpuvar.h
diff -u src/sys/arch/x86/include/cpuvar.h:1.48 src/sys/arch/x86/include/cpuvar.h:1.49
--- src/sys/arch/x86/include/cpuvar.h:1.48 Fri Jan 13 05:26:42 2017
+++ src/sys/arch/x86/include/cpuvar.h Wed Apr 19 06:43:05 2017
@@ -1,4 +1,4 @@
-/* $NetBSD: cpuvar.h,v 1.48 2017/01/13 05:26:42 christos Exp $ */
+/* $NetBSD: cpuvar.h,v 1.49 2017/04/19 06:43:05 nonaka Exp $ */
/*-
* Copyright (c) 2000, 2007 The NetBSD Foundation, Inc.
@@ -102,7 +102,6 @@ struct cpufeature_attach_args {
#endif /* defined(_KERNEL_OPT) */
int x86_ipi(int, int, int);
-void x86_self_ipi(int);
int x86_ipi_init(int);
int x86_ipi_startup(int, int);
void x86_errata(void);
Index: src/sys/arch/x86/include/i82489var.h
diff -u src/sys/arch/x86/include/i82489var.h:1.16 src/sys/arch/x86/include/i82489var.h:1.17
--- src/sys/arch/x86/include/i82489var.h:1.16 Fri Nov 25 14:12:56 2016
+++ src/sys/arch/x86/include/i82489var.h Wed Apr 19 06:43:05 2017
@@ -1,4 +1,4 @@
-/* $NetBSD: i82489var.h,v 1.16 2016/11/25 14:12:56 maxv Exp $ */
+/* $NetBSD: i82489var.h,v 1.17 2017/04/19 06:43:05 nonaka Exp $ */
/*-
* Copyright (c) 1998 The NetBSD Foundation, Inc.
@@ -95,12 +95,6 @@ extern void Xrecurse_lapic_ltimer(void);
#define LAPIC_PIN_LVINT1 4
#define LAPIC_PIN_LVERR 5
-extern void Xintr_lapic0(void);
-extern void Xintr_lapic2(void);
-extern void Xintr_lapic3(void);
-extern void Xintr_lapic4(void);
-extern void Xintr_lapic5(void);
-
struct cpu_info;
CVS commit: src/sys/arch/x86/include
Module Name:src
Committed By: maxv
Date: Sun Mar 5 09:08:18 UTC 2017
Modified Files:
src/sys/arch/x86/include: pmap.h
Log Message:
Remove PG_u from the kernel pages on Xen. Otherwise there is no privilege
separation between the kernel and userland.
On Xen-amd64, the kernel runs in ring3 just like userland, and the
separation is guaranteed by the hypervisor - each syscall/trap is
intercepted by Xen and sent manually to the kernel. Before that, the
hypervisor modifies the page tables so that the kernel becomes accessible.
Later, when returning to userland, the hypervisor removes the kernel pages
and flushes the TLB.
However, TLB flushes are costly, and in order to reduce the number of pages
flushed Xen marks the userland pages as global, while keeping the kernel
ones as local. This way, when returning to userland, only the kernel pages
get flushed - which makes sense since they are the only ones that got
removed from the mapping.
Xen differentiates the userland pages by looking at their PG_u bit in the
PTE; if a page has this bit then Xen tags it as global, otherwise Xen
manually adds the bit but keeps the page as local. The thing is, since we
set PG_u in the kernel pages, Xen believes our kernel pages are in fact
userland pages, so it marks them as global. Therefore, when returning to
userland, the kernel pages indeed get removed from the page tree, but are
not flushed from the TLB. Which means that they are still accessible.
With this - and depending on the DTLB size - userland has a small window
where it can read/write to the last kernel pages accessed, which is enough
to completely escalate privileges: the sysent structure systematically gets
read when performing a syscall, and chances are that it will still be
cached in the TLB. Userland can then use this to patch a chosen syscall,
make it point to a userland function, retrieve %gs and compute the address
of its credentials, and finally grant itself root privileges.
To generate a diff of this commit:
cvs rdiff -u -r1.62 -r1.63 src/sys/arch/x86/include/pmap.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/include/pmap.h
diff -u src/sys/arch/x86/include/pmap.h:1.62 src/sys/arch/x86/include/pmap.h:1.63
--- src/sys/arch/x86/include/pmap.h:1.62 Sat Feb 11 14:11:24 2017
+++ src/sys/arch/x86/include/pmap.h Sun Mar 5 09:08:18 2017
@@ -1,4 +1,4 @@
-/* $NetBSD: pmap.h,v 1.62 2017/02/11 14:11:24 maxv Exp $ */
+/* $NetBSD: pmap.h,v 1.63 2017/03/05 09:08:18 maxv Exp $ */
/*
* Copyright (c) 1997 Charles D. Cranor and Washington University.
@@ -180,15 +180,7 @@ struct pmap {
((pmap)->pm_pdirpa[0] + (index) * sizeof(pd_entry_t))
#endif
-/*
- * flag to be used for kernel mappings: PG_u on Xen/amd64,
- * 0 otherwise.
- */
-#if defined(XEN) && defined(__x86_64__)
-#define PG_k PG_u
-#else
#define PG_k 0
-#endif
/*
* MD flags that we use for pmap_enter and pmap_kenter_pa:
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: maxv Date: Sat Feb 18 16:15:51 UTC 2017 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: Add the AMD 10h family PMC values. Some values depend on the CPU revision, they are commented out. Several other values are common with K7, we could merge them later. This family of CPUs has a 12bit event selector, contrary to K7 (8bit). The thing is, i386's PMC interface takes as argument a uint8_t from userland, so these counters are not accessible (yet). To generate a diff of this commit: cvs rdiff -u -r1.93 -r1.94 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/x86/include/specialreg.h diff -u src/sys/arch/x86/include/specialreg.h:1.93 src/sys/arch/x86/include/specialreg.h:1.94 --- src/sys/arch/x86/include/specialreg.h:1.93 Sat Feb 11 15:11:45 2017 +++ src/sys/arch/x86/include/specialreg.h Sat Feb 18 16:15:51 2017 @@ -1,4 +1,4 @@ -/* $NetBSD: specialreg.h,v 1.93 2017/02/11 15:11:45 maxv Exp $ */ +/* $NetBSD: specialreg.h,v 1.94 2017/02/18 16:15:51 maxv Exp $ */ /*- * Copyright (c) 1991 The Regents of the University of California. @@ -997,7 +997,7 @@ #define PMC6_RET_SEG_RENAMES 0xd6 /* P-II and P-III only */ /* - * AMD K7 Event Selector MSR format. + * AMD K7 Event Selector MSR format. [Doc: 22007K.pdf, Feb 2002] */ #define K7_EVTSEL_EVENT 0x00ff @@ -1084,3 +1084,164 @@ #define K7_BP1_MATCH 0xdd #define K7_BP2_MATCH 0xde #define K7_BP3_MATCH 0xdf + +/* + * AMD 10h family PMCs. [Doc: 31116.pdf, Jan 2013] + */ +/* Register MSRs */ +#define MSR_F10H_EVNTSEL0 0xc001 +#define MSR_F10H_EVNTSEL1 0xc0010001 +#define MSR_F10H_EVNTSEL2 0xc0010002 +#define MSR_F10H_EVNTSEL3 0xc0010003 +#define MSR_F10H_PERFCTR0 0xc0010004 +#define MSR_F10H_PERFCTR1 0xc0010005 +#define MSR_F10H_PERFCTR2 0xc0010006 +#define MSR_F10H_PERFCTR3 0xc0010007 +/* Event Selector MSR format */ +#define F10H_EVTSEL_EVENT_MASK 0x000F00FF +#define F10H_EVTSEL_EVENT_SHIFT_LOW 0 +#define F10H_EVTSEL_EVENT_SHIFT_HIGH 32 +#define F10H_EVTSEL_UNIT_MASK 0xFF00 +#define F10H_EVTSEL_UNIT_SHIFT 8 +#define F10H_EVTSEL_USR__BIT(16) +#define F10H_EVTSEL_OS__BIT(17) +#define F10H_EVTSEL_EDGE __BIT(18) +#define F10H_EVTSEL_RSVD1 __BIT(19) +#define F10H_EVTSEL_INT__BIT(20) +#define F10H_EVTSEL_RSVD2 __BIT(21) +#define F10H_EVTSEL_EN__BIT(22) +#define F10H_EVTSEL_INV__BIT(23) +#define F10H_EVTSEL_COUNTER_MASK 0xFF00 +#define F10H_EVTSEL_COUNTER_MASK_SHIFT 24 +/* Floating Point Events */ +#define F10H_FP_DISPATCHED_FPU_OPS 0x00 +#define F10H_FP_CYCLES_EMPTY_FPU_OPS 0x01 +#define F10H_FP_DISPATCHED_FASTFLAG_OPS 0x02 +#define F10H_FP_RETIRED_SSE_OPS 0x03 +#define F10H_FP_RETIRED_MOVE_OPS 0x04 +#define F10H_FP_RETIRED_SERIALIZING_OPS 0x05 +#define F10H_FP_CYCLES_SERIALIZING_OP_SCHEDULER 0x06 +/* Load/Store and TLB Events */ +#define F10H_SEGMENT_REG_LOADS 0x20 +#define F10H_PIPELINE_RESTART_SELFMOD_CODE 0x21 +#define F10H_PIPELINE_RESTART_PROBE_HIT 0x22 +#define F10H_LS_BUFFER_2_FILL 0x23 +#define F10H_LOCKED_OPERATIONS 0x24 +#define F10H_RETIRED_CLFLUSH_INSTRUCTIONS 0x26 +#define F10H_RETIRED_CPUID_INSTRUCTIONS 0x27 +#define F10H_CANCELLED_STORE_LOAD_FORWARD_OPS 0x2A +#define F10H_SMI_RECEIVED 0x2B +/* Data Cache Events */ +#define F10H_DATA_CACHE_ACCESSES 0x40 +#define F10H_DATA_CACHE_MISSES 0x41 +#define F10H_DATA_CACHE_REFILLS_FROM_L2 0x42 +#define F10H_DATA_CACHE_REFILLS_FROM_NORTHBRIDGE 0x43 +#define F10H_CACHE_LINES_EVICTED 0x44 +#define F10H_L1_DTLB_MISS 0x45 +#define F10H_L2_DTLB_MISS 0x46 +#define F10H_MISALIGNED_ACCESSES 0x47 +#define F10H_MICROARCH_LATE_CANCEL_OF_ACCESS 0x48 +#define F10H_MICROARCH_EARLY_CANCEL_OF_ACCESS 0x49 +#define F10H_SINGLE_BIT_ECC_ERRORS_RECORDED 0x4A +#define F10H_PREFETCH_INSTRUCTIONS_DISPATCHED 0x4B +#define F10H_DCACHE_MISSES_LOCKED_INSTRUCTIONS 0x4C +#define F10H_L1_DTLB_HIT 0x4D +#define F10H_INEFFECTIVE_SOFTWARE_PREFETCHS 0x52 +#define F10H_GLOBAL_TLB_FLUSHES 0x54 +#define F10H_MEMORY_REQUESTS_BY_TYPE 0x65 +#define F10H_DATA_PREFETCHER 0x67 +#define F10H_MAB_REQUESTS 0x68 +#define F10H_MAB_WAIT_CYCLES 0x69 +#define F10H_NORTHBRIDGE_READ_RESP_BY_COH_STATE 0x6C +#define F10H_OCTWORDS_WRITTEN_TO_SYSTEM 0x6D +#define F10H_CPU_CLOCKS_NOT_HALTED 0x76 +#define F10H_REQUESTS_TO_L2_CACHE 0x7D +#define F10H_L2_CACHE_MISSES 0x7E +#define F10H_L2_FILL0x7F +/* F10H_PAGE_SIZE_MISMATCHES (0x01C0): reserved on some revisions */ +/* Instruction Cache Events */ +#define F10H_INSTRUCTION_CACHE_FETCHES 0x80 +#define F10H_INSTRUCTION_CACHE_MISSES 0x81 +#define F10H_INSTRUCTION_CACHE_REFILLS_FROM_L2 0x82 +#define F10H_INSTRUCTION_CACHE_REFILLS_FROM_SYS 0x83 +#define F10H_L1_ITLB_MISS 0x84 +#define F10H_L2_ITLB_MISS 0x85 +#define F10H_PIPELINE_RESTART_INSTR_STREAM_PROBE 0x86 +#define
CVS commit: src/sys/arch/x86/include
Module Name:src
Committed By: nonaka
Date: Tue Feb 14 13:25:22 UTC 2017
Modified Files:
src/sys/arch/x86/include: bootinfo.h
Log Message:
x86: add e820 memory type.
To generate a diff of this commit:
cvs rdiff -u -r1.25 -r1.26 src/sys/arch/x86/include/bootinfo.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/include/bootinfo.h
diff -u src/sys/arch/x86/include/bootinfo.h:1.25 src/sys/arch/x86/include/bootinfo.h:1.26
--- src/sys/arch/x86/include/bootinfo.h:1.25 Tue Jan 24 11:09:14 2017
+++ src/sys/arch/x86/include/bootinfo.h Tue Feb 14 13:25:22 2017
@@ -1,4 +1,4 @@
-/* $NetBSD: bootinfo.h,v 1.25 2017/01/24 11:09:14 nonaka Exp $ */
+/* $NetBSD: bootinfo.h,v 1.26 2017/02/14 13:25:22 nonaka Exp $ */
/*
* Copyright (c) 1997
@@ -119,6 +119,10 @@ struct bi_memmap_entry {
#define BIM_Reserved 2 /* in use or reserved by the system */
#define BIM_ACPI 3 /* ACPI Reclaim memory */
#define BIM_NVS 4 /* ACPI NVS memory */
+#define BIM_Unusable 5 /* errors have been detected */
+#define BIM_Disabled 6 /* not enabled */
+#define BIM_PMEM 7 /* Persistent memory */
+#define BIM_PRAM 12 /* legacy NVDIMM (OEM defined) */
struct btinfo_memmap {
struct btinfo_common common;
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: maxv Date: Sat Feb 11 15:11:45 UTC 2017 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: Fix a few (unused) MSR values, and add some others that I believe are relevant. >From Murray Armfield (PR/42861). To generate a diff of this commit: cvs rdiff -u -r1.92 -r1.93 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/x86/include/specialreg.h diff -u src/sys/arch/x86/include/specialreg.h:1.92 src/sys/arch/x86/include/specialreg.h:1.93 --- src/sys/arch/x86/include/specialreg.h:1.92 Thu Feb 2 05:43:48 2017 +++ src/sys/arch/x86/include/specialreg.h Sat Feb 11 15:11:45 2017 @@ -1,4 +1,4 @@ -/* $NetBSD: specialreg.h,v 1.92 2017/02/02 05:43:48 msaitoh Exp $ */ +/* $NetBSD: specialreg.h,v 1.93 2017/02/11 15:11:45 maxv Exp $ */ /*- * Copyright (c) 1991 The Regents of the University of California. @@ -651,14 +651,14 @@ #define MSR_MC2_STATUS 0x409 #define MSR_MC2_ADDR 0x40a #define MSR_MC2_MISC 0x40b -#define MSR_MC4_CTL 0x40c -#define MSR_MC4_STATUS 0x40d -#define MSR_MC4_ADDR 0x40e -#define MSR_MC4_MISC 0x40f -#define MSR_MC3_CTL 0x410 -#define MSR_MC3_STATUS 0x411 -#define MSR_MC3_ADDR 0x412 -#define MSR_MC3_MISC 0x413 +#define MSR_MC3_CTL 0x40c +#define MSR_MC3_STATUS 0x40d +#define MSR_MC3_ADDR 0x40e +#define MSR_MC3_MISC 0x40f +#define MSR_MC4_CTL 0x410 +#define MSR_MC4_STATUS 0x411 +#define MSR_MC4_ADDR 0x412 +#define MSR_MC4_MISC 0x413 /* 0x480 - 0x490 VMX */ /* @@ -694,13 +694,16 @@ /* * AMD K8 (Opteron) MSRs. */ -#define MSR_SYSCFG 0xc010 +#define MSR_SYSCFG 0xc0010010 #define MSR_EFER 0xc080 /* Extended feature enable */ -#define EFER_SCE 0x0001 /* SYSCALL extension */ -#define EFER_LME 0x0100 /* Long Mode Active */ -#define EFER_LMA 0x0400 /* Long Mode Enabled */ -#define EFER_NXE 0x0800 /* No-Execute Enabled */ +#define EFER_SCE 0x0001 /* SYSCALL extension */ +#define EFER_LME 0x0100 /* Long Mode Active */ +#define EFER_LMA 0x0400 /* Long Mode Enabled */ +#define EFER_NXE 0x0800 /* No-Execute Enabled */ +#define EFER_SVME 0x1000 /* Secure Virtual Machine En. */ +#define EFER_LMSLE 0x2000 /* Long Mode Segment Limit E. */ +#define EFER_FFXSR 0x4000 /* Fast FXSAVE/FXRSTOR En. */ #define MSR_STAR 0xc081 /* 32 bit syscall gate addr */ #define MSR_LSTAR 0xc082 /* 64 bit syscall gate addr */
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: msaitoh Date: Thu Feb 2 05:43:48 UTC 2017 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: Modify comment. Use long form. To generate a diff of this commit: cvs rdiff -u -r1.91 -r1.92 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/x86/include/specialreg.h diff -u src/sys/arch/x86/include/specialreg.h:1.91 src/sys/arch/x86/include/specialreg.h:1.92 --- src/sys/arch/x86/include/specialreg.h:1.91 Thu Dec 8 06:11:03 2016 +++ src/sys/arch/x86/include/specialreg.h Thu Feb 2 05:43:48 2017 @@ -1,4 +1,4 @@ -/* $NetBSD: specialreg.h,v 1.91 2016/12/08 06:11:03 msaitoh Exp $ */ +/* $NetBSD: specialreg.h,v 1.92 2017/02/02 05:43:48 msaitoh Exp $ */ /*- * Copyright (c) 1991 The Regents of the University of California. @@ -292,7 +292,7 @@ #define CPUID_DSPM_HWP_ACTWIN __BIT(9) /* HWP Activity Window */ #define CPUID_DSPM_HWP_EPP __BIT(10) /* HWP Energy Performance Preference */ #define CPUID_DSPM_HWP_PLR __BIT(11) /* HWP Package Level Request */ -#define CPUID_DSPM_HDC __BIT(13) /* HDC */ +#define CPUID_DSPM_HDC __BIT(13) /* Hardware Duty Cycling */ #define CPUID_DSPM_FLAGS "\20" \ "\1" "DTS" "\2" "IDA" "\3" "ARAT" \
CVS commit: src/sys/arch/x86/include
Module Name:src
Committed By: christos
Date: Fri Jan 13 05:26:42 UTC 2017
Modified Files:
src/sys/arch/x86/include: cpuvar.h
Log Message:
Add missing forward decl.
To generate a diff of this commit:
cvs rdiff -u -r1.47 -r1.48 src/sys/arch/x86/include/cpuvar.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/include/cpuvar.h
diff -u src/sys/arch/x86/include/cpuvar.h:1.47 src/sys/arch/x86/include/cpuvar.h:1.48
--- src/sys/arch/x86/include/cpuvar.h:1.47 Sun Dec 13 10:02:19 2015
+++ src/sys/arch/x86/include/cpuvar.h Fri Jan 13 00:26:42 2017
@@ -1,4 +1,4 @@
-/* $NetBSD: cpuvar.h,v 1.47 2015/12/13 15:02:19 maxv Exp $ */
+/* $NetBSD: cpuvar.h,v 1.48 2017/01/13 05:26:42 christos Exp $ */
/*-
* Copyright (c) 2000, 2007 The NetBSD Foundation, Inc.
@@ -66,6 +66,7 @@
#ifndef _X86_CPUVAR_H_
#define _X86_CPUVAR_H_
+struct cpu_info;
struct cpu_functions {
#ifndef XEN
int (*start)(struct cpu_info *, paddr_t);
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: msaitoh Date: Thu Dec 8 06:11:03 UTC 2016 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: Add CLWB bit. To generate a diff of this commit: cvs rdiff -u -r1.90 -r1.91 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/x86/include/specialreg.h diff -u src/sys/arch/x86/include/specialreg.h:1.90 src/sys/arch/x86/include/specialreg.h:1.91 --- src/sys/arch/x86/include/specialreg.h:1.90 Mon Dec 5 03:59:47 2016 +++ src/sys/arch/x86/include/specialreg.h Thu Dec 8 06:11:03 2016 @@ -1,4 +1,4 @@ -/* $NetBSD: specialreg.h,v 1.90 2016/12/05 03:59:47 msaitoh Exp $ */ +/* $NetBSD: specialreg.h,v 1.91 2016/12/08 06:11:03 msaitoh Exp $ */ /*- * Copyright (c) 1991 The Regents of the University of California. @@ -340,6 +340,7 @@ #define CPUID_SEF_ADX __BIT(19) #define CPUID_SEF_SMAP __BIT(20) #define CPUID_SEF_CLFLUSHOPT __BIT(23) +#define CPUID_SEF_CLWB __BIT(24) #define CPUID_SEF_PT __BIT(25) #define CPUID_SEF_AVX512PF __BIT(26) #define CPUID_SEF_AVX512ER __BIT(27) @@ -355,7 +356,7 @@ "\15" "QM" "\16" "FPUCSDS" "\17" "MPX" "\20" "PQE" \ "\21" "AVX512F" "\22" "AVX512DQ" "\23" "RDSEED" "\24" "ADX" \ "\25" "SMAP" "\30" "CLFLUSHOPT" \ - "\32" "PT" "\33" "AVX512PF" "\34" "AVX512ER" \ + "\31" "CLWB" "\32" "PT" "\33" "AVX512PF" "\34" "AVX512ER" \ "\35" "AVX512CD""\36" "SHA" "\37" "AVX512BW" "\40" "AVX512VL" /* %ecx */
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: msaitoh Date: Mon Dec 5 03:59:47 UTC 2016 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: Fix CPUID_SEF_FLAGS. Octal value has no 8. To generate a diff of this commit: cvs rdiff -u -r1.89 -r1.90 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/x86/include/specialreg.h diff -u src/sys/arch/x86/include/specialreg.h:1.89 src/sys/arch/x86/include/specialreg.h:1.90 --- src/sys/arch/x86/include/specialreg.h:1.89 Fri Aug 19 18:53:29 2016 +++ src/sys/arch/x86/include/specialreg.h Mon Dec 5 03:59:47 2016 @@ -1,4 +1,4 @@ -/* $NetBSD: specialreg.h,v 1.89 2016/08/19 18:53:29 maxv Exp $ */ +/* $NetBSD: specialreg.h,v 1.90 2016/12/05 03:59:47 msaitoh Exp $ */ /*- * Copyright (c) 1991 The Regents of the University of California. @@ -354,9 +354,9 @@ "\11" "BMI2" "\12" "ERMS" "\13" "INVPCID" "\14" "RTM" \ "\15" "QM" "\16" "FPUCSDS" "\17" "MPX" "\20" "PQE" \ "\21" "AVX512F" "\22" "AVX512DQ" "\23" "RDSEED" "\24" "ADX" \ - "\25" "SMAP" "\28" "CLFLUSHOPT" \ + "\25" "SMAP" "\30" "CLFLUSHOPT" \ "\32" "PT" "\33" "AVX512PF" "\34" "AVX512ER" \ - "\35" "AVX512CD""\36" "SHA" "\37" "AVX512BW" "\38" "AVX512VL" + "\35" "AVX512CD""\36" "SHA" "\37" "AVX512BW" "\40" "AVX512VL" /* %ecx */ #define CPUID_SEF_PREFETCHWT1 __BIT(0)
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: maxv Date: Fri Aug 19 18:53:29 UTC 2016 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: KNF so NXR likes it, and some typos To generate a diff of this commit: cvs rdiff -u -r1.88 -r1.89 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/x86/include/specialreg.h diff -u src/sys/arch/x86/include/specialreg.h:1.88 src/sys/arch/x86/include/specialreg.h:1.89 --- src/sys/arch/x86/include/specialreg.h:1.88 Sat Jul 16 13:47:01 2016 +++ src/sys/arch/x86/include/specialreg.h Fri Aug 19 18:53:29 2016 @@ -1,4 +1,4 @@ -/* $NetBSD: specialreg.h,v 1.88 2016/07/16 13:47:01 maxv Exp $ */ +/* $NetBSD: specialreg.h,v 1.89 2016/08/19 18:53:29 maxv Exp $ */ /*- * Copyright (c) 1991 The Regents of the University of California. @@ -34,12 +34,12 @@ /* * Bits in 386 special registers: */ -#define CR0_PE 0x0001 /* Protected mode Enable */ -#define CR0_MP 0x0002 /* "Math" Present (NPX or NPX emulator) */ -#define CR0_EM 0x0004 /* EMulate non-NPX coproc. (trap ESC only) */ -#define CR0_TS 0x0008 /* Task Switched (if MP, trap ESC and WAIT) */ -#define CR0_ET 0x0010 /* Extension Type (387 (if set) vs 287) */ -#define CR0_PG 0x8000 /* PaGing enable */ +#define CR0_PE 0x0001 /* Protected mode Enable */ +#define CR0_MP 0x0002 /* "Math" Present (NPX or NPX emulator) */ +#define CR0_EM 0x0004 /* EMulate non-NPX coproc. (trap ESC only) */ +#define CR0_TS 0x0008 /* Task Switched (if MP, trap ESC and WAIT) */ +#define CR0_ET 0x0010 /* Extension Type (387 (if set) vs 287) */ +#define CR0_PG 0x8000 /* PaGing enable */ /* * Bits in 486 special registers: @@ -47,8 +47,8 @@ #define CR0_NE 0x0020 /* Numeric Error enable (EX16 vs IRQ13) */ #define CR0_WP 0x0001 /* Write Protect (honor PG_RW in all modes) */ #define CR0_AM 0x0004 /* Alignment Mask (set to enable AC flag) */ -#define CR0_NW 0x2000 /* Not Write-through */ -#define CR0_CD 0x4000 /* Cache Disable */ +#define CR0_NW 0x2000 /* Not Write-through */ +#define CR0_CD 0x4000 /* Cache Disable */ /* * Cyrix 486 DLC special registers, accessible as IO ports. @@ -94,14 +94,14 @@ /* * Extended Control Register XCR0 */ -#define XCR0_X87 0x0001 /* x87 FPU/MMX state */ -#define XCR0_SSE 0x0002 /* SSE state */ -#define XCR0_YMM_Hi128 0x0004 /* AVX-256 (ymmn registers) */ -#define XCR0_BNDREGS 0x0008 /* Memory protection ext bounds */ -#define XCR0_BNDCSR 0x0010 /* Memory protection ext state */ -#define XCR0_Opmask 0x0020 /* AVX-512 Opmask */ -#define XCR0_ZMM_Hi256 0x0040 /* AVX-512 upper 256 bits low regs */ -#define XCR0_Hi16_ZMM 0x0080 /* AVX-512 512 bits upper registers */ +#define XCR0_X87 0x0001 /* x87 FPU/MMX state */ +#define XCR0_SSE 0x0002 /* SSE state */ +#define XCR0_YMM_Hi128 0x0004 /* AVX-256 (ymmn registers) */ +#define XCR0_BNDREGS 0x0008 /* Memory protection ext bounds */ +#define XCR0_BNDCSR 0x0010 /* Memory protection ext state */ +#define XCR0_Opmask 0x0020 /* AVX-512 Opmask */ +#define XCR0_ZMM_Hi256 0x0040 /* AVX-512 upper 256 bits low regs */ +#define XCR0_Hi16_ZMM 0x0080 /* AVX-512 512 bits upper registers */ /* * Known fpu bits - only these get enabled @@ -125,38 +125,38 @@ */ /* Fn0001 %edx features */ -#define CPUID_FPU 0x0001 /* processor has an FPU? */ -#define CPUID_VME 0x0002 /* has virtual mode (%cr4's VME/PVI) */ -#define CPUID_DE 0x0004 /* has debugging extension */ -#define CPUID_PSE 0x0008 /* has 4MB page size extension */ -#define CPUID_TSC 0x0010 /* has time stamp counter */ -#define CPUID_MSR 0x0020 /* has mode specific registers */ -#define CPUID_PAE 0x0040 /* has phys address extension */ -#define CPUID_MCE 0x0080 /* has machine check exception */ -#define CPUID_CX8 0x0100 /* has CMPXCHG8B instruction */ -#define CPUID_APIC 0x0200 /* has enabled APIC */ -#define CPUID_B10 0x0400 /* reserved, MTRR */ -#define CPUID_SEP 0x0800 /* has SYSENTER/SYSEXIT extension */ -#define CPUID_MTRR 0x1000 /* has memory type range register */ -#define CPUID_PGE 0x2000 /* has page global extension */ -#define CPUID_MCA 0x4000 /* has machine check architecture */ -#define CPUID_CMOV 0x8000 /* has CMOVcc instruction */ -#define CPUID_PAT 0x0001 /* Page Attribute Table */ -#define CPUID_PSE36 0x0002 /* 36-bit PSE */ -#define CPUID_PN 0x0004 /* processor serial number */ -#define CPUID_CFLUSH 0x0008 /* CFLUSH insn supported */ -#define CPUID_B20 0x0010 /* reserved */ -#define CPUID_DS 0x0020 /* Debug Store */ -#define CPUID_ACPI 0x0040 /* ACPI performance modulation regs */ -#define CPUID_MMX 0x0080 /* MMX supported */ -#define CPUID_FXSR 0x0100 /* fast FP/MMX save/restore */ -#define CPUID_SSE
CVS commit: src/sys/arch/x86/include
Module Name:src
Committed By: maxv
Date: Thu Aug 18 13:00:54 UTC 2016
Modified Files:
src/sys/arch/x86/include: cpu_extended_state.h
Log Message:
KNF and simplify.
To generate a diff of this commit:
cvs rdiff -u -r1.9 -r1.10 src/sys/arch/x86/include/cpu_extended_state.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/include/cpu_extended_state.h
diff -u src/sys/arch/x86/include/cpu_extended_state.h:1.9 src/sys/arch/x86/include/cpu_extended_state.h:1.10
--- src/sys/arch/x86/include/cpu_extended_state.h:1.9 Tue Feb 25 22:16:52 2014
+++ src/sys/arch/x86/include/cpu_extended_state.h Thu Aug 18 13:00:54 2016
@@ -1,40 +1,8 @@
-/* $NetBSD: cpu_extended_state.h,v 1.9 2014/02/25 22:16:52 dsl Exp $ */
+/* $NetBSD: cpu_extended_state.h,v 1.10 2016/08/18 13:00:54 maxv Exp $ */
#ifndef _X86_CPU_EXTENDED_STATE_H_
#define _X86_CPU_EXTENDED_STATE_H_
-/*
- * This file contains definitions of structures that match the memory
- * layouts used x86 processors to save floating point registers and other
- * extended cpu state.
- * This includes registers (etc) used by SSE/SSE2/SSE3/SSSE3/SSE4 and
- * the later AVX instructions.
- * The definitions are such that any future 'extended state' should
- * be handled (provided the kernel doesn't need to know the actual contents.
- *
- * The actual structures the cpu accesses must be aligned to 16 for
- * FXSAVE and 64 for XSAVE. The types aren't aligned because copies
- * do not need extra alignment.
- *
- * The slightly different layout saved by the i387 fsave in also defined.
- * This is only normally written by pre Pentium II type cpus that don't
- * support the fxsave instruction.
- *
- * Associated save instructions:
- * FNSAVE: Saves x87 state in 108 bytes (original i387 layout).
- * Then reinitialies the fpu.
- * FSAVE: Encodes to FWAIT followed by FNSAVE.
- * FXSAVE: Saves the x87 state and XMM (aka SSE) registers to the
- * first 448 (max) bytes of a 512 byte area.
- * This layout does not match that written by FNSAVE.
- * XSAVE: Uses the same layout for the x87 and XMM registers,
- * followed by a 64byte header and separate save areas
- * for additional extended cpu state.
- * The x87 state is always saved, the others conditionally.
- * XSAVEOPT: As XSAVE but (IIRC) only writes the registers blocks
- * that have been modified.
- */
-
#ifdef __lint__
/* Lint has different packing rules and doesn't understand __aligned() */
#define __CTASSERT_NOLINT(x) __CTASSERT(1)
@@ -43,10 +11,43 @@
#endif
/*
- * Layout for code/data pointers relating to FP exceptions.
- * Marked 'packed' because they aren't always 64bit aligned.
- * Since the x86 cpu supports misaligned accesses it isn't
- * worth avoiding the 'packed' attribute.
+ * This file contains definitions of structures that match the memory layouts
+ * used on x86 processors to save floating point registers and other extended
+ * cpu states.
+ *
+ * This includes registers (etc) used by SSE/SSE2/SSE3/SSSE3/SSE4 and the later
+ * AVX instructions.
+ *
+ * The definitions are such that any future 'extended state' should be handled
+ * (provided the kernel doesn't need to know the actual contents).
+ *
+ * The actual structures the cpu accesses must be aligned to 16 bytes for FXSAVE
+ * and 64 for XSAVE. The types aren't aligned because copies do not need extra
+ * alignment.
+ *
+ * The slightly different layout saved by the i387 fsave is also defined.
+ * This is only normally written by pre Pentium II type cpus that don't
+ * support the fxsave instruction.
+ *
+ * Associated save instructions:
+ * FNSAVE: Saves x87 state in 108 bytes (original i387 layout).
+ * Then reinitializes the fpu.
+ * FSAVE:Encodes to FWAIT followed by FNSAVE.
+ * FXSAVE: Saves the x87 state and XMM (aka SSE) registers to the
+ * first 448 (max) bytes of a 512 byte area.
+ * This layout does not match that written by FNSAVE.
+ * XSAVE:Uses the same layout for the x87 and XMM registers,
+ * followed by a 64byte header and separate save areas
+ * for additional extended cpu state.
+ * The x87 state is always saved, the others conditionally.
+ * XSAVEOPT: As XSAVE but only writes the registers blocks that have been
+ * modified.
+ */
+
+/*
+ * Layout for code/data pointers relating to FP exceptions. Marked 'packed'
+ * because they aren't always 64bit aligned. Since the x86 cpu supports
+ * misaligned accesses it isn't worth avoiding the 'packed' attribute.
*/
union fp_addr {
uint64_t fa_64; /* Linear address for 64bit systems */
@@ -59,8 +60,8 @@ union fp_addr {
/* The x87 registers are 80 bits */
struct fpacc87 {
- uint64_t f87_mantissa; /* mantissa */
- uint16_t f87_exp_sign; /* exponent and sign */
+ uint64_t f87_mantissa; /* mantissa */
+ uint16_t
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: maxv Date: Sat Jul 16 13:47:01 UTC 2016 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: Add the cr4 flags for PKE and UMIP. To generate a diff of this commit: cvs rdiff -u -r1.87 -r1.88 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/x86/include/specialreg.h diff -u src/sys/arch/x86/include/specialreg.h:1.87 src/sys/arch/x86/include/specialreg.h:1.88 --- src/sys/arch/x86/include/specialreg.h:1.87 Wed Apr 27 08:51:32 2016 +++ src/sys/arch/x86/include/specialreg.h Sat Jul 16 13:47:01 2016 @@ -1,4 +1,4 @@ -/* $NetBSD: specialreg.h,v 1.87 2016/04/27 08:51:32 msaitoh Exp $ */ +/* $NetBSD: specialreg.h,v 1.88 2016/07/16 13:47:01 maxv Exp $ */ /*- * Copyright (c) 1991 The Regents of the University of California. @@ -81,6 +81,7 @@ #define CR4_PCE 0x0100 /* enable RDPMC instruction for all cpls */ #define CR4_OSFXSR 0x0200 /* enable fxsave/fxrestor and SSE */ #define CR4_OSXMMEXCPT 0x0400 /* enable unmasked SSE exceptions */ +#define CR4_UMIP 0x0800 /* user-mode instruction prevention */ #define CR4_VMXE 0x2000 /* enable VMX operations */ #define CR4_SMXE 0x4000 /* enable SMX operations */ #define CR4_FSGSBASE 0x0001 /* enable *FSBASE and *GSBASE instructions */ @@ -88,6 +89,7 @@ #define CR4_OSXSAVE 0x0004 /* enable xsave and xrestore */ #define CR4_SMEP 0x0010 /* enable SMEP support */ #define CR4_SMAP 0x0020 /* enable SMAP support */ +#define CR4_PKE 0x0040 /* protection key enable */ /* * Extended Control Register XCR0
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: msaitoh Date: Wed Apr 27 08:51:32 UTC 2016 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: Add some bit definitions mainly taken from the latest Intel SDM: - Add SGX, UMIP, RDPID and SGXLC. - Add avx512dq, avx512bw and avx512vl. Fix the bit location of CLFLUSHOPT. To generate a diff of this commit: cvs rdiff -u -r1.86 -r1.87 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/x86/include/specialreg.h diff -u src/sys/arch/x86/include/specialreg.h:1.86 src/sys/arch/x86/include/specialreg.h:1.87 --- src/sys/arch/x86/include/specialreg.h:1.86 Wed Jan 13 07:19:29 2016 +++ src/sys/arch/x86/include/specialreg.h Wed Apr 27 08:51:32 2016 @@ -1,4 +1,4 @@ -/* $NetBSD: specialreg.h,v 1.86 2016/01/13 07:19:29 msaitoh Exp $ */ +/* $NetBSD: specialreg.h,v 1.87 2016/04/27 08:51:32 msaitoh Exp $ */ /*- * Copyright (c) 1991 The Regents of the University of California. @@ -318,6 +318,7 @@ /* %ebx */ #define CPUID_SEF_FSGSBASE __BIT(0) #define CPUID_SEF_TSC_ADJUST __BIT(1) +#define CPUID_SEF_SGX __BIT(2) #define CPUID_SEF_BMI1 __BIT(3) #define CPUID_SEF_HLE __BIT(4) #define CPUID_SEF_AVX2 __BIT(5) @@ -332,6 +333,7 @@ #define CPUID_SEF_MPX __BIT(14) #define CPUID_SEF_PQE __BIT(15) #define CPUID_SEF_AVX512F __BIT(16) +#define CPUID_SEF_AVX512DQ __BIT(17) #define CPUID_SEF_RDSEED __BIT(18) #define CPUID_SEF_ADX __BIT(19) #define CPUID_SEF_SMAP __BIT(20) @@ -341,25 +343,32 @@ #define CPUID_SEF_AVX512ER __BIT(27) #define CPUID_SEF_AVX512CD __BIT(28) #define CPUID_SEF_SHA __BIT(29) +#define CPUID_SEF_AVX512BW __BIT(30) +#define CPUID_SEF_AVX512VL __BIT(31) #define CPUID_SEF_FLAGS "\20" \ - "\1" "FSGSBASE" "\2" "TSCADJUST" "\4" "BMI1" \ + "\1" "FSGSBASE" "\2" "TSCADJUST" "\3" "SGX" "\4" "BMI1" \ "\5" "HLE" "\6" "AVX2" "\7" "FDPEXONLY" "\10" "SMEP" \ "\11" "BMI2" "\12" "ERMS" "\13" "INVPCID" "\14" "RTM" \ "\15" "QM" "\16" "FPUCSDS" "\17" "MPX" "\20" "PQE" \ - "\21" "AVX512F" "\23" "RDSEED" "\24" "ADX" \ - "\25" "SMAP" "\26" "CLFLUSHOPT"\ - "\32" "PT" "\33" "AVX512PF""\34" "AVX512ER" \ - "\35" "AVX512CD""\36" "SHA" + "\21" "AVX512F" "\22" "AVX512DQ" "\23" "RDSEED" "\24" "ADX" \ + "\25" "SMAP" "\28" "CLFLUSHOPT" \ + "\32" "PT" "\33" "AVX512PF" "\34" "AVX512ER" \ + "\35" "AVX512CD""\36" "SHA" "\37" "AVX512BW" "\38" "AVX512VL" /* %ecx */ #define CPUID_SEF_PREFETCHWT1 __BIT(0) +#define CPUID_SEF_UMIP __BIT(2) #define CPUID_SEF_PKU __BIT(3) #define CPUID_SEF_OSPKE __BIT(4) +#define CPUID_SEF_RDPID __BIT(22) +#define CPUID_SEF_SGXLC __BIT(30) #define CPUID_SEF_FLAGS1 "\20" \ - "\1" "PREFETCHWT1""\4" "PKU" \ - "\5" "OSPKE" + "\1" "PREFETCHWT1" "\3" "UMIP" "\4" "PKU" \ + "\5" "OSPKE" \ + "\27" "RDPID" \ + "\37" "SGXLC" /* * CPUID Processor extended state Enumeration Fn000d
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: msaitoh Date: Wed Apr 27 08:47:03 UTC 2016 Modified Files: src/sys/arch/x86/include: cacheinfo.h Log Message: Add new desc 0x64 and 0xc4. To generate a diff of this commit: cvs rdiff -u -r1.21 -r1.22 src/sys/arch/x86/include/cacheinfo.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/x86/include/cacheinfo.h diff -u src/sys/arch/x86/include/cacheinfo.h:1.21 src/sys/arch/x86/include/cacheinfo.h:1.22 --- src/sys/arch/x86/include/cacheinfo.h:1.21 Fri Jan 8 02:25:15 2016 +++ src/sys/arch/x86/include/cacheinfo.h Wed Apr 27 08:47:03 2016 @@ -1,4 +1,4 @@ -/* $NetBSD: cacheinfo.h,v 1.21 2016/01/08 02:25:15 msaitoh Exp $ */ +/* $NetBSD: cacheinfo.h,v 1.22 2016/04/27 08:47:03 msaitoh Exp $ */ #ifndef _X86_CACHEINFO_H_ #define _X86_CACHEINFO_H_ @@ -234,6 +234,7 @@ __CI_TBL(CAI_DTLB, 0x5c, 0xff, 64, __CI_TBL(CAI_DTLB, 0x5d, 0xff, 64,4 * 1024, "4K/4M: 256 entries"),\ __CI_TBL(CAI_ITLB, 0x61, 0xff, 48,4 * 1024, NULL), \ __CI_TBL(CAI_L1_1GBDTLB,0x63, 4, 4,1024*1024 * 1024, NULL), \ +__CI_TBL(CAI_DTLB, 0x64,4,512,4 * 1024, NULL), \ __CI_TBL(CAI_ITLB, 0x6a,8, 64,4 * 1024, NULL), \ __CI_TBL(CAI_DTLB, 0x6b,8,256,4 * 1024, NULL), \ __CI_TBL(CAI_L2_DTLB2, 0x6c,8,128, 0, "2M/4M: 128 entries"),\ @@ -252,6 +253,7 @@ __CI_TBL(CAI_DTLB2,0xc0,4, 8, __CI_TBL(CAI_L2_STLB2, 0xc1,8,1024, 4 * 1024, "4K/2M: 1024 entries"), \ __CI_TBL(CAI_DTLB2,0xc2,4, 16,4 * 1024, "4K/2M: 16 entries"), \ __CI_TBL(CAI_L2_STLB, 0xc3,6,1536, 4 * 1024, NULL), \ +__CI_TBL(CAI_DTLB2,0xc4,4, 32,4 * 1024, "2M/4M: 32 entries"), \ __CI_TBL(CAI_L2_STLB, 0xca,4,512,4 * 1024, NULL), \ __CI_TBL(CAI_ICACHE, 0x06,4,8 * 1024, 32, NULL), \ __CI_TBL(CAI_ICACHE, 0x08,4, 16 * 1024, 32, NULL), \
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: msaitoh Date: Wed Jan 13 07:19:29 UTC 2016 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: Add some AMD's bit definitions from "BIOS and Kernel Developer(BKDG) for AMD Family 15h Models 60h-6Fh Processors". To generate a diff of this commit: cvs rdiff -u -r1.85 -r1.86 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/x86/include/specialreg.h diff -u src/sys/arch/x86/include/specialreg.h:1.85 src/sys/arch/x86/include/specialreg.h:1.86 --- src/sys/arch/x86/include/specialreg.h:1.85 Fri Jan 8 03:26:35 2016 +++ src/sys/arch/x86/include/specialreg.h Wed Jan 13 07:19:29 2016 @@ -1,4 +1,4 @@ -/* $NetBSD: specialreg.h,v 1.85 2016/01/08 03:26:35 msaitoh Exp $ */ +/* $NetBSD: specialreg.h,v 1.86 2016/01/13 07:19:29 msaitoh Exp $ */ /*- * Copyright (c) 1991 The Regents of the University of California. @@ -447,6 +447,7 @@ #define CPUID_WDT 0x2000 /* watchdog timer support */ #define CPUID_LWP 0x8000 /* Light Weight Profiling */ #define CPUID_FMA4 0x0001 /* FMA4 instructions */ +#define CPUID_TCE 0x0002 /* Translation cache Extension */ #define CPUID_NODEID 0x0008 /* NodeID MSR available*/ #define CPUID_TBM 0x0020 /* TBM instructions */ #define CPUID_TOPOEXT 0x0040 /* cpuid Topology Extension */ @@ -455,6 +456,8 @@ #define CPUID_SPM 0x0200 /* Stream Perf Mon */ #define CPUID_DBE 0x0400 /* Data Breakpoint Extension */ #define CPUID_PTSC 0x0800 /* PerfTsc */ +#define CPUID_L2IPERFC 0x1000 /* L2I performance counter Extension */ +#define CPUID_MWAITX 0x2000 /* MWAITX/MONITORX support */ #define CPUID_AMD_FLAGS4 "\20" \ "\1" "LAHF" "\2" "CMPLEGACY" "\3" "SVM" "\4" "EAPIC" \ @@ -462,10 +465,10 @@ "\11" "3DNOWPREFETCH" \ "\12" "OSVW" "\13" "IBS" "\14" "XOP" \ "\15" "SKINIT" "\16" "WDT" "\17" "B14" "\20" "LWP" \ - "\21" "FMA4" "\22" "B17" "\23" "B18" "\24" "NodeID" \ + "\21" "FMA4" "\22" "TCE" "\23" "B18" "\24" "NodeID" \ "\25" "B20" "\26" "TBM" "\27" "TopoExt" "\30" "PCExtC" \ "\31" "PCExtNB" "\32" "StrmPM" "\33" "DBExt" "\34" "PerfTsc" \ - "\35" "B28" "\36" "B29" "\37" "B30" "\40" "B31" + "\35" "L2IPERFC" "\36" "MWAITX" "\37" "B30" "\40" "B31" /* * AMD Advanced Power Management
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: msaitoh Date: Fri Jan 8 02:25:15 UTC 2016 Modified Files: src/sys/arch/x86/include: cacheinfo.h Log Message: Index 0x6c is not 126 entries but 128 entries. The old value was from previous SDM. To generate a diff of this commit: cvs rdiff -u -r1.20 -r1.21 src/sys/arch/x86/include/cacheinfo.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/x86/include/cacheinfo.h diff -u src/sys/arch/x86/include/cacheinfo.h:1.20 src/sys/arch/x86/include/cacheinfo.h:1.21 --- src/sys/arch/x86/include/cacheinfo.h:1.20 Mon Oct 19 02:45:26 2015 +++ src/sys/arch/x86/include/cacheinfo.h Fri Jan 8 02:25:15 2016 @@ -1,4 +1,4 @@ -/* $NetBSD: cacheinfo.h,v 1.20 2015/10/19 02:45:26 msaitoh Exp $ */ +/* $NetBSD: cacheinfo.h,v 1.21 2016/01/08 02:25:15 msaitoh Exp $ */ #ifndef _X86_CACHEINFO_H_ #define _X86_CACHEINFO_H_ @@ -236,7 +236,7 @@ __CI_TBL(CAI_ITLB, 0x61, 0xff, 48, __CI_TBL(CAI_L1_1GBDTLB,0x63, 4, 4,1024*1024 * 1024, NULL), \ __CI_TBL(CAI_ITLB, 0x6a,8, 64,4 * 1024, NULL), \ __CI_TBL(CAI_DTLB, 0x6b,8,256,4 * 1024, NULL), \ -__CI_TBL(CAI_L2_DTLB2, 0x6c,8,126, 0, "2M/4M: 126 entries"),\ +__CI_TBL(CAI_L2_DTLB2, 0x6c,8,128, 0, "2M/4M: 128 entries"),\ __CI_TBL(CAI_L1_1GBDTLB,0x6d,0xff, 16,1024*1024 * 1024, NULL), \ __CI_TBL(CAI_ITLB2,0x76, 0xff, 8, 4 * 1024 * 1024, "2M/4M: 8 entries"), \ __CI_TBL(CAI_DTLB, 0xa0, 0xff, 32,4 * 1024, NULL), \
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: msaitoh Date: Fri Jan 8 02:27:08 UTC 2016 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: Add x86 FPU Data Pointer Updated Only bit from Intel SDM. To generate a diff of this commit: cvs rdiff -u -r1.83 -r1.84 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/x86/include/specialreg.h diff -u src/sys/arch/x86/include/specialreg.h:1.83 src/sys/arch/x86/include/specialreg.h:1.84 --- src/sys/arch/x86/include/specialreg.h:1.83 Fri Aug 14 06:54:22 2015 +++ src/sys/arch/x86/include/specialreg.h Fri Jan 8 02:27:07 2016 @@ -1,4 +1,4 @@ -/* $NetBSD: specialreg.h,v 1.83 2015/08/14 06:54:22 msaitoh Exp $ */ +/* $NetBSD: specialreg.h,v 1.84 2016/01/08 02:27:07 msaitoh Exp $ */ /*- * Copyright (c) 1991 The Regents of the University of California. @@ -321,6 +321,7 @@ #define CPUID_SEF_BMI1 __BIT(3) #define CPUID_SEF_HLE __BIT(4) #define CPUID_SEF_AVX2 __BIT(5) +#define CPUID_SEF_FDPEXONLY __BIT(6) #define CPUID_SEF_SMEP __BIT(7) #define CPUID_SEF_BMI2 __BIT(8) #define CPUID_SEF_ERMS __BIT(9) @@ -342,7 +343,7 @@ #define CPUID_SEF_FLAGS "\20" \ "\1" "FSGSBASE" "\2" "TSCADJUST" "\4" "BMI1" \ - "\5" "HLE" "\6" "AVX2" "\10" "SMEP" \ + "\5" "HLE" "\6" "AVX2" "\7" "FDPEXONLY" "\10" "SMEP" \ "\11" "BMI2" "\12" "ERMS" "\13" "INVPCID" "\14" "RTM" \ "\15" "QM" "\16" "FPUCSDS" "\17" "MPX" "\20" "PQE" \ "\21" "AVX512F" "\23" "RDSEED" "\24" "ADX" \
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: msaitoh Date: Fri Jan 8 03:26:35 UTC 2016 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: Add CLFLUSHOPT bit. To generate a diff of this commit: cvs rdiff -u -r1.84 -r1.85 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/x86/include/specialreg.h diff -u src/sys/arch/x86/include/specialreg.h:1.84 src/sys/arch/x86/include/specialreg.h:1.85 --- src/sys/arch/x86/include/specialreg.h:1.84 Fri Jan 8 02:27:07 2016 +++ src/sys/arch/x86/include/specialreg.h Fri Jan 8 03:26:35 2016 @@ -1,4 +1,4 @@ -/* $NetBSD: specialreg.h,v 1.84 2016/01/08 02:27:07 msaitoh Exp $ */ +/* $NetBSD: specialreg.h,v 1.85 2016/01/08 03:26:35 msaitoh Exp $ */ /*- * Copyright (c) 1991 The Regents of the University of California. @@ -335,6 +335,7 @@ #define CPUID_SEF_RDSEED __BIT(18) #define CPUID_SEF_ADX __BIT(19) #define CPUID_SEF_SMAP __BIT(20) +#define CPUID_SEF_CLFLUSHOPT __BIT(23) #define CPUID_SEF_PT __BIT(25) #define CPUID_SEF_AVX512PF __BIT(26) #define CPUID_SEF_AVX512ER __BIT(27) @@ -347,8 +348,8 @@ "\11" "BMI2" "\12" "ERMS" "\13" "INVPCID" "\14" "RTM" \ "\15" "QM" "\16" "FPUCSDS" "\17" "MPX" "\20" "PQE" \ "\21" "AVX512F" "\23" "RDSEED" "\24" "ADX" \ - "\25" "SMAP" \ - "\32" "PT" "\33" "AVX512PF""\34" "AVX512ER"\ + "\25" "SMAP" "\26" "CLFLUSHOPT"\ + "\32" "PT" "\33" "AVX512PF""\34" "AVX512ER" \ "\35" "AVX512CD""\36" "SHA" /* %ecx */
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: msaitoh Date: Mon Oct 19 02:45:26 UTC 2015 Modified Files: src/sys/arch/x86/include: cacheinfo.h Log Message: Add some TLB entries from the latest Intel SDM. This change might incorrect because the document itself is very strange. To generate a diff of this commit: cvs rdiff -u -r1.19 -r1.20 src/sys/arch/x86/include/cacheinfo.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/x86/include/cacheinfo.h diff -u src/sys/arch/x86/include/cacheinfo.h:1.19 src/sys/arch/x86/include/cacheinfo.h:1.20 --- src/sys/arch/x86/include/cacheinfo.h:1.19 Tue Sep 9 15:11:33 2014 +++ src/sys/arch/x86/include/cacheinfo.h Mon Oct 19 02:45:26 2015 @@ -1,4 +1,4 @@ -/* $NetBSD: cacheinfo.h,v 1.19 2014/09/09 15:11:33 msaitoh Exp $ */ +/* $NetBSD: cacheinfo.h,v 1.20 2015/10/19 02:45:26 msaitoh Exp $ */ #ifndef _X86_CACHEINFO_H_ #define _X86_CACHEINFO_H_ @@ -234,6 +234,10 @@ __CI_TBL(CAI_DTLB, 0x5c, 0xff, 64, __CI_TBL(CAI_DTLB, 0x5d, 0xff, 64,4 * 1024, "4K/4M: 256 entries"),\ __CI_TBL(CAI_ITLB, 0x61, 0xff, 48,4 * 1024, NULL), \ __CI_TBL(CAI_L1_1GBDTLB,0x63, 4, 4,1024*1024 * 1024, NULL), \ +__CI_TBL(CAI_ITLB, 0x6a,8, 64,4 * 1024, NULL), \ +__CI_TBL(CAI_DTLB, 0x6b,8,256,4 * 1024, NULL), \ +__CI_TBL(CAI_L2_DTLB2, 0x6c,8,126, 0, "2M/4M: 126 entries"),\ +__CI_TBL(CAI_L1_1GBDTLB,0x6d,0xff, 16,1024*1024 * 1024, NULL), \ __CI_TBL(CAI_ITLB2,0x76, 0xff, 8, 4 * 1024 * 1024, "2M/4M: 8 entries"), \ __CI_TBL(CAI_DTLB, 0xa0, 0xff, 32,4 * 1024, NULL), \ __CI_TBL(CAI_ITLB, 0xb0,4,128,4 * 1024, NULL), \
CVS commit: src/sys/arch/x86/include
Module Name:src Committed By: msaitoh Date: Fri Aug 14 06:54:22 UTC 2015 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: - Add Hardware-Controlled Performance States (HWP) bits. - Use __BIT() To generate a diff of this commit: cvs rdiff -u -r1.82 -r1.83 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/x86/include/specialreg.h diff -u src/sys/arch/x86/include/specialreg.h:1.82 src/sys/arch/x86/include/specialreg.h:1.83 --- src/sys/arch/x86/include/specialreg.h:1.82 Fri May 8 07:23:56 2015 +++ src/sys/arch/x86/include/specialreg.h Fri Aug 14 06:54:22 2015 @@ -1,4 +1,4 @@ -/* $NetBSD: specialreg.h,v 1.82 2015/05/08 07:23:56 msaitoh Exp $ */ +/* $NetBSD: specialreg.h,v 1.83 2015/08/14 06:54:22 msaitoh Exp $ */ /*- * Copyright (c) 1991 The Regents of the University of California. @@ -279,16 +279,24 @@ * Intel Digital Thermal Sensor and * Power Management, Fn_0006 - %eax. */ -#define CPUID_DSPM_DTS 0x0001 /* Digital Thermal Sensor */ -#define CPUID_DSPM_IDA 0x0002 /* Intel Dynamic Acceleration */ -#define CPUID_DSPM_ARAT 0x0004 /* Always Running APIC Timer */ -#define CPUID_DSPM_PLN 0x0010 /* Power Limit Notification */ -#define CPUID_DSPM_CME 0x0020 /* Clock Modulation Extension */ -#define CPUID_DSPM_PLTM 0x0040 /* Package Level Thermal Management */ +#define CPUID_DSPM_DTS __BIT(0) /* Digital Thermal Sensor */ +#define CPUID_DSPM_IDA __BIT(1) /* Intel Dynamic Acceleration */ +#define CPUID_DSPM_ARAT __BIT(2) /* Always Running APIC Timer */ +#define CPUID_DSPM_PLN __BIT(4) /* Power Limit Notification */ +#define CPUID_DSPM_ECMD __BIT(5) /* Clock Modulation Extension */ +#define CPUID_DSPM_PTM __BIT(6) /* Package Level Thermal Management */ +#define CPUID_DSPM_HWP __BIT(7) /* HWP */ +#define CPUID_DSPM_HWP_NOTIFY __BIT(8) /* HWP Notification */ +#define CPUID_DSPM_HWP_ACTWIN __BIT(9) /* HWP Activity Window */ +#define CPUID_DSPM_HWP_EPP __BIT(10) /* HWP Energy Performance Preference */ +#define CPUID_DSPM_HWP_PLR __BIT(11) /* HWP Package Level Request */ +#define CPUID_DSPM_HDC __BIT(13) /* HDC */ #define CPUID_DSPM_FLAGS \20 \ - \1 DTS \2 IDA \3 ARAT \ - \5 PLN \6 CME \7 PLTM + \1 DTS \2 IDA \3 ARAT \ + \5 PLN \6 ECMD \7 PTM \10 HWP \ + \11 HWP_NOTIFY \12 HWP_ACTWIN \13 HWP_EPP \14 HWP_PLR \ + \16 HDC /* * Intel Digital Thermal Sensor and
