Am 09.05.2016 um 10:08 schrieb Magnus Danielson:
Hi,
On 05/08/2016 09:53 PM, Attila Kinali wrote:
True and not true. Yes, there are many ADCs that do high conversion
rates, but these are optimized for piplined applications where
conversion
happens at a constant rate. Ie they expect a constan
Hoi Bruce,
On Mon, 9 May 2016 23:34:24 + (UTC)
Bruce Griffiths wrote:
> Its probably easier/cheaper to construct a suitable filter for a GSPS ADC
> than to construct a TAC that is fast enough to suit an ADC with a GHz clock.
Probably.
> Minimising the emitter to emitter inductance of a lo
Hoi Attila
Yes, the only way to reduce emitter-emitter inductance is indeed to connect
them on the die. Its even better if the current source transistor collector is
also connected to the common emitter node of the long tailed pair on the die as
this minimises the capacitance at this node.
Alt
Its probably easier/cheaper to construct a suitable filter for a GSPS ADC than
to construct a TAC that is fast enough to suit an ADC with a GHz clock.
Minimising the emitter to emitter inductance of a longtailed pair or equivalent
is key to achieving a fast enough switching time for a suitable T
In this case though we are talking about pushing the TAC resolution to
14 bits or maybe higher and that is about the level where dielectric
absorption starts to become a problem in all but the better film
capacitors. NP0 ceramics are perhaps more than an order of magnitude
worse than the best film
Since the GSPS sampling ADCs all appear to use an input buffer with relatively
low value resistors between the differential inputs or connected to a midpoint
bias voltage, some kind of high impedance buffer is needed between the TAC
capacitor and the ADC input when using such ADCs. The highest c
Hi
Simple answer:
You are likely using an NPO cap and it’s not a big deal.
Bob
> On May 8, 2016, at 9:49 PM, David wrote:
>
> How much will dielectric absorption in the capacitor affect the
> accuracy of the result with such a high conversion rate? I am used to
> dealing with it on much l
Hi,
On 05/08/2016 09:53 PM, Attila Kinali wrote:
On Wed, 4 May 2016 15:26:37 +0200
Magnus Danielson wrote:
Indeed. ADC conversion speed is not a big issue these days, so the Nutt
style of interpolator is just expensive to parallelize for speed, the
time-to-voltage system is better and should
Sure, and then we are back to a transition midpoint timing TDC. Or AC
couple it for a centroid timing TDC. These require a lot more
processing to generate a result compared to a time to amplitude
converter but with economical FPGAs and ARM microcontrollers, maybe
this does not matter.
I was just
Another option is to use a low pass filter to increase the transition times of
the signal to be timestamped and use a pipelined ADC to sample the filter
output.Perhaps something like the attached filter derived from:
http://bears.ucsb.edu/rad/pubs/conference/MTT_S_2004.pdf
May be effective in tha
Hi
> On May 8, 2016, at 7:08 PM, Gerhard Hoffmann wrote:
>
> Am 08.05.2016 um 21:53 schrieb Attila Kinali:
> ...
>
> Maybe I was too short. We have control over the charging current source,
> and when we switch it off, the status quo is kept. Then when the ADC is done,
> we can simply short the
How much will dielectric absorption in the capacitor affect the
accuracy of the result with such a high conversion rate? I am used to
dealing with it on much longer time scales and higher resolutions.
On Mon, 9 May 2016 01:08:05 +0200, you wrote:
>Am 08.05.2016 um 21:53 schrieb Attila Kinali:
>.
On Sun, 8 May 2016 21:53:56 +0200, you wrote:
>On Wed, 4 May 2016 15:26:37 +0200
>Magnus Danielson wrote:
>
>> Indeed. ADC conversion speed is not a big issue these days, so the Nutt
>> style of interpolator is just expensive to parallelize for speed, the
>> time-to-voltage system is better and
Yes, just a synchroniser clocked with the same clock as the ADC.The
interpolator measures the synchroniser delay by charging the capacitor in the
interval between the occurrence of the transition to be time stamped and when
the output of the synchroniser recognises this transition.The ADC sample
Am 08.05.2016 um 21:53 schrieb Attila Kinali:
True and not true. Yes, there are many ADCs that do high conversion
rates, but these are optimized for piplined applications where conversion
happens at a constant rate. Ie they expect a constant conversion clock
with a constant rate. If you want to t
Am 08.05.2016 um 21:53 schrieb Attila Kinali:
...
Maybe I was too short. We have control over the charging current source,
and when we switch it off, the status quo is kept. Then when the ADC is
done,
we can simply short the capacitor in the next clock/s to prepare for the
next cycle.
Attill
On Wed, 4 May 2016 15:26:37 +0200
Magnus Danielson wrote:
> Indeed. ADC conversion speed is not a big issue these days, so the Nutt
> style of interpolator is just expensive to parallelize for speed, the
> time-to-voltage system is better and should have a much better
> recycle-time and thus r
Am 06.05.2016 um 01:00 schrieb Mike Monett:
I have been thinking along the same lines, to combine multiple OCXOS's to
obtain lower phase noise. But an N-way Wilkinson could get tedious. After
you calculate the impedances for each leg, you then have to convert them to
lumped-element equivalents to
Hi
Be careful of isolation specs on some of these combiners / splitters. Often
they are deponent on the return loss
of the signal source. An OCXO that presets a 12 db return loss is doing ok. One
that is past 20 db is doing quite well.
Bob
> On May 5, 2016, at 7:00 PM, Mike Monett wrote:
>
>
Am 05.05.2016 um 01:55 schrieb Bruce Griffiths:
On Wednesday, May 04, 2016 02:22:22 PM Gerhard Hoffmann wrote:
But we stayed with a classical time stretcher, and my private project
pipeline is already full.
Talking about my own pipeline:
I have finally ordered today the first 20 samples of my
On Wednesday, May 04, 2016 02:22:22 PM Gerhard Hoffmann wrote:
> Am 04.05.2016 um 10:46 schrieb Bruce Griffiths:
> > Integrating A Time interval to charge TAC at the front end of a capacitive
> > charge redistribution SAR ADC should allow a conversion time of 300ns or
> > so.. Using 16 such TDCs sh
The data sheet seems to cover it. There is a throughput per channel
limit and a limit on the number of channels available depending on
mode, and a limit on the total output data rate. In the lower
resolution modes, an internal 32 entry FIFO allows burst acquisitions
up to 182 million per second.
For the sensor timestamping you can try replicate an avalanche effect
with a device which uses a pn-pn substrate configuration ... or
something similar to the avalanche photodiodes.
The avalanche photodiode has very high gain and a response time of some
ps (5ps a commercial APD).
This system may
att...@kinali.ch said:
> The limit for TDCs in FPGAs seems to be around 5-20ps RMS (which makes it
> more like 15-50ps in "real" precision) depending on type and technology.
> Going down to below 20ps usually means to take the latest tech FPGA with
> lots of redundant structures, which makes the
Hi,
Indeed. ADC conversion speed is not a big issue these days, so the Nutt
style of interpolator is just expensive to parallelize for speed, the
time-to-voltage system is better and should have a much better
recycle-time and thus result in less hardware needs.
Cheers,
Magnus
On 05/04/2016
time-nuts-requ...@febo.com wrote:
Message: 16
Date: Tue, 3 May 2016 14:31:17 +0200
From: Attila Kinali
To: Discussion of precise time and frequency measurement
Subject: [time-nuts] High rate, high precision/accuracy time interval
counter methods
Message-ID:<20160503143117.3d9
Am 04.05.2016 um 10:46 schrieb Bruce Griffiths:
Integrating A Time interval to charge TAC at the front end of a capacitive
charge redistribution SAR ADC should allow a conversion time of 300ns or so..
Using 16 such TDCs should permit 1ps resolution with a 50MHz timestamp rate
without too many
On 05/04/2016 10:38 AM, Attila Kinali wrote:
On Tue, 3 May 2016 22:31:14 +0200
Magnus Danielson wrote:
An alternative to the edge estimator method is to continuously sample,
mix with a reference frequency, decimate and then do arc-tangent of the
I/Q samples. This is what is used for phase-no
One method is to have the event trigger sampling of a pair of quadrature phase
sinewaves. eg LT1407A-1 dual 14 bit SAR ADC can sample a quadrature pair of
10MHz sine waves with ~ 5ps resolution in the computed phase.
Bruce
On Wednesday, 4 May 2016 10:00 PM, Attila Kinali wrote:
On Tu
Integrating A Time interval to charge TAC at the front end of a capacitive
charge redistribution SAR ADC should allow a conversion time of 300ns or so..
Using 16 such TDCs should permit 1ps resolution with a 50MHz timestamp rate
without too many cascaded gates in the selection logic for the next
On Tue, 3 May 2016 22:31:14 +0200
Magnus Danielson wrote:
> An alternative to the edge estimator method is to continuously sample,
> mix with a reference frequency, decimate and then do arc-tangent of the
> I/Q samples. This is what is used for phase-noise measurement such as
> the Symmetricom
On Tue, 3 May 2016 08:40:53 -0700
"Richard (Rick) Karlquist" wrote:
> You also might consider that over 25 years
> ago, HP developed the 5313X counters with
> interpolators implemented in FPGA's. The
> FPGA's available now are vastly more
> sophisticated and much faster. Perhaps there
> is a wa
On Tuesday, May 03, 2016 02:31:17 PM Attila Kinali wrote:
> Hi,
>
> We had here a discussion about measuring events (ie time stamping
> them precisely) with high rates. As some of you know, Javier and
> his group, Bruce and me are working on a system that should give
> us something better than 10p
I&Q sine sampling works, but a continuous sampling allows for N samples
to reduce the noise by sqrt(N) rather than 2 samples. The white-noise
will be the limiting factor for the higher rates.
Least-square estimation provides a 2.5 dB improvement over straight
sample average.
Cheers,
Magnus
Wouldn't this be a natural application of a centroid or transition
midpoint timing TDC implemented with a pulse shaper, fast ADC, and
FPGA?
What about sampling inphase and quadrature sine waves? This should be
more amendable to a microcontroller only solution and if I had to
start working on some
Rick,
Unless you uses the high-speed SERDES blocks, the jitter and systematic
noises inside FGPAs can be pretty prohibitive.
Enrico Rubiola and his team have made some of the best characterizations
of FPGAs I've seen, but I know from several other experinces that timing
can uhm shift around.
Hi Attila,
On 05/03/2016 02:31 PM, Attila Kinali wrote:
Hi,
We had here a discussion about measuring events (ie time stamping
them precisely) with high rates. As some of you know, Javier and
his group, Bruce and me are working on a system that should give
us something better than 10ps (my guess
HP/Agilent/Keysight laser interferometers
measure at the kind of rates you are talking
about and (last time I heard) could divide
an interference fringe down to 1/512 of a
wavelength. As you say, they definitely use
an ASIC with a ring oscillator. Perhaps
there is some way you could repurpose th
Hi,
We had here a discussion about measuring events (ie time stamping
them precisely) with high rates. As some of you know, Javier and
his group, Bruce and me are working on a system that should give
us something better than 10ps (my guess is that we should get close
to 1ps) at a rate of (guestima
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