>>> Gilles.
>>>>>
>>>>>
>>>>>>> Le 20 juin 2020 à 19:48, Robert LaJeunesse a
>>>>>>> écrit :
>>>>>> Gilles, if I read the Calosso-Rubiola paper correctly a Pi divider is
>>>>>>
Two 74HC393N and one 74HC86N Dip all for less than $ 2 will do the job
Bert Kehren
In a message dated 6/21/2020 3:57:59 PM Eastern Standard Time,
k8yumdoo...@gmail.com writes:
Can you stand a few 10's of nano-Hz error in the 162 kHz signal? If so, a
48-bit
DDS can get you that close to 162
ard square-wave producing digital divider, such as
>>>>> a 74163 (for even divides). There's odd-value (3,5,7) Pi dividers shown
>>>>> at
>>>>> https://www.theremin.us/Circuit_Library/symmetrical_digital_dividers.html.
>>>>> What the Caloss
Can you stand a few 10's of nano-Hz error in the 162 kHz signal? If so, a
48-bit
DDS can get you that close to 162 kHz when the 10 MHz is right on.
However, dealing with the off-the air signal would be problematic as has
been pointed
out, not to mention the added complication of the signal
French time signal is phase modulated. If I recall correctly.
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.us/Circuit_Library/symmetrical_digital_dividers.html.
>>>> What the Calosso-Rubiola paper promotes is the Lambda divider, which is
>>>> depicted in figure 2 of the paper.
>>>>
>>>> Bob L.
>>>>
>>>>> Sent: Friday, June 1
is the Lambda divider, which is depicted in
figure 2 of the paper.
Bob L.
Sent: Friday, June 19, 2020 at 10:27 AM
From: "Gilles Clement"
To: "Poul-Henning Kamp"
Cc: "Discussion of precise time and frequency measurement"
Subject: Re: [time-nuts] Frequency division
heremin.us/Circuit_Library/symmetrical_digital_dividers.html.
>>> What the Calosso-Rubiola paper promotes is the Lambda divider, which is
>>> depicted in figure 2 of the paper.
>>>
>>> Bob L.
>>>
>>>> Sent: Friday, June 19, 2020 at 10:27 AM
>&
.html.
>> What the Calosso-Rubiola paper promotes is the Lambda divider, which is
>> depicted in figure 2 of the paper.
>>
>> Bob L.
>>
>>> Sent: Friday, June 19, 2020 at 10:27 AM
>>> From: "Gilles Clement"
>>> To: &quo
b L.
>
>> Sent: Friday, June 19, 2020 at 10:27 AM
>> From: "Gilles Clement"
>> To: "Poul-Henning Kamp"
>> Cc: "Discussion of precise time and frequency measurement"
>>
>> Subject: Re: [time-nuts] Frequency division by 81
>
measurement"
>
> Subject: Re: [time-nuts] Frequency division by 81
>
> Hi,
> Could you point me to a practical design example of a Pi divider ?
>
>
> Envoyé de mon iPad
>
> > Le 19 juin 2020 à 08:56, Poul-Henning Kamp a écrit :
> >
> >
On the 15 MHz FE 405 we use an XOR and two Flip Flops to divide by 3 with a
symmetrical output. Four of these will give you symmetry and divide by 81
Bert Kehren
In a message dated 6/19/2020 8:14:31 PM Eastern Standard Time, kb...@n1k.org
writes:
Hi
The biggest issue is that there are so
Hi
The biggest issue is that there are so many variables. They never seem
to get nailed down. What you are seeing is the answer to 20 or more
“niche” requirements.
For instance:
Is the “phase noise” requirement close in or broadband? ECL is in general
horrible for broadband phase noise.
Is
Hi
What are we trying to do here?
What is the input frequency?
What is the phase noise of the OCXO?
What is the phase noise requirement on the output?
Are there other system based requirements on the output?
(ADEV maybe ….)
=
Symmetry (by it’s self) going from 50/50 to 45/55 (or
On Fri, 19 Jun 2020 14:49:01 +
"Poul-Henning Kamp" wrote:
> Gilles Clement writes:
> > Could you point me to a practical design example of a Pi divider ?
>
> Look at Fig 2 in Enrico's paper:
>
> > http://rubiola.org/pdf-articles/conference/2013-ifcs-Frequency-dividers.pdf
I saw this a
Am 19.06.20 um 11:42 schrieb Clint Jay:
12F675 is specified for clock input of 20MHz and (without digging too
deep into the way the code works) I think the PICDiv code works with
clock input rather than input to a timer or counter peripheral so
20MHz would be fine. While I'd not recommend it
Gilles Clement writes:
> Could you point me to a practical design example of a Pi divider ?
Look at Fig 2 in Enrico's paper:
> http://rubiola.org/pdf-articles/conference/2013-ifcs-Frequency-dividers.pdf
I would implement it so that the shiftregister is also the divider,
by making it
Hi,
Could you point me to a practical design example of a Pi divider ?
Envoyé de mon iPad
> Le 19 juin 2020 à 08:56, Poul-Henning Kamp a écrit :
>
>
>
>> I need to divide the output of an OCXO by a factor D=81 for testing
>> purposes. So with minimum added phase noise.
>
> Two
Current PICDIV concept generates exactly 50% output duty cycles, so only even
dividing factors are possible.
If we accept a slightly unbalanced duty cycles (ex: one more instruction on the
down side loop than for the up side loop), one could generalize to odd factors.
(An idea suggested by
Thanks for all your replies.
Very interesting, A lot to digest.
Best,
GIlles.
Envoyé de mon iPad
> Le 19 juin 2020 à 01:12, Richard (Rick) Karlquist a
> écrit :
>
>
>
>> On 6/18/2020 4:58 AM, Gilles Clement wrote:
>> Hi
>> I need to divide the output of an OCXO by a factor D=81 for
t; To: Discussion of precise time and frequency measurement <
> time-nuts@lists.febo.com>
> Subject: Re: [time-nuts] Frequency division by 81
>
> Hi
>
> A lot depends on the output frequency of your OCXO. If it puts out 900 MHz,
> that’s a bit different than if it puts out 9 MHz.
You can use one of the Silabs 8051 microcontrollers. They run one clock per
instruction (for the 1 byte instructions like NOP) so dividing by 81 should
not be a problem.
I use them extensively to make programmable dividers. My favorite small
package is a SO-14. They have much smaller devices but
On 6/18/2020 4:58 AM, Gilles Clement wrote:
Hi
I need to divide the output of an OCXO by a factor D=81 for testing purposes.
So with minimum added phase noise.
If you are using any kind of digital divider, let me
recommend that you first condition the signal to be
divided by using an ADI
> I need to divide the output of an OCXO by a factor D=81 for testing purposes.
> So with minimum added phase noise.
Two stages of divide by 9 PI-dividers ?
http://rubiola.org/pdf-articles/conference/2013-ifcs-Frequency-dividers.pdf
--
Poul-Henning Kamp | UNIX since
and frequency measurement
Subject: Re: [time-nuts] Frequency division by 81
Hi
A lot depends on the output frequency of your OCXO. If it puts out 900 MHz,
that’s a bit different than if it puts out 9 MHz. For “normal” OCXO’s in the sub
30 MHz region, CMOS logic will do the division just fine
Hi
The gotcha is that the “HC” logic families have pretty high broadband noise
floors compared to newer parts.
At 20 log (N), divide by 81 gets you about 38 db of phase noise improvement. If
you started off at -130 dbc/Hz,
you come out at -168 dbc / Hz. That (of course) assumes you don’t hit
Hi
A lot depends on the output frequency of your OCXO. If it puts out 900 MHz,
that’s a bit different than if it puts out 9 MHz. For “normal” OCXO’s in the sub
30 MHz region, CMOS logic will do the division just fine. If a PICDIV is a
candidate,
I’m guessing the OCXO is in this range.
You
I've read that the so-called regenerative frequency divider has
exceptionally low
phase noise. You could cascade four of them, each dividing by 3. It's not
the
simplest thing in the world, but might yield really good phase noise
performance.
Back when I worked at TEK on the 2710 (low-cost SA)
For a 10 MHz clock, 74HC would be fine. For small numbers like 81, a
couple of 74HC163s would do it, and be good to go since they're
synchronous anyway.
For large numbers, my go-to divider is the 74HC4040 12-bit ripple
counter. It can be rigged for any fixed integer divide ratio from 3 to
> I need to divide the output of an OCXO by a factor D=81 for testing purposes.
> So with minimum added phase noise. PICDIV-like approches would not work (D
> needs to be divisible by 8 or at least be even) I went through the archives
> and it seems that an Injection Locked Frequency Divider
Why don't you simply divide by 81 with a normal CMOS divider and
synchronize its output with a 7474-like flipflop to the original clock?
The phase noise would be determined only by this last flipflop.
regards, Gerhard
Am 18.06.20 um 13:58 schrieb Gilles Clement:
Hi
I need to divide the
Hi Gilles, I didn't peruse the linked paper, but I usually use a re-sync
FF MC100ep51 or 52 with the clock at the pre-divider rate, and the "D"
coming from in my case an FPGA. thai eliminates the phase noise
contributed by the FPGA. The nice thing with an FPGA, is you can use the
LVDS outputs
Depending on your needs there are many off-the-shelf programmable
frequency divider IC's.
Most of the modern ones are not programmed by strapping pins but by serial
connection to a microcontroller so this may not be your cup of tea.
If so, look at the math and note that 81 = 9*9 or 3*3*3*3.
Two
Hi
I need to divide the output of an OCXO by a factor D=81 for testing purposes.
So with minimum added phase noise.
PICDIV-like approches would not work (D needs to be divisible by 8 or at least
be even)
I went through the archives and it seems that an Injection Locked Frequency
Divider with
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