On 05/31/2013 08:11 AM, Christoffer Dall wrote:
On Mon, May 06, 2013 at 03:17:44PM +0200, Andre Przywara wrote:
(for GIT URL and Changelog see below)
ARM CPUs with the virtualization extension have a new mode called
HYP mode, which allows hypervisors to safely control and monitor
guests. The
Hi everyone,
I have been testing for a while now on the i.mx28 evk, and I noticed
that almost all tftp transfers take some time before they actually
start. It will show a 'T' as first character, then followed by '#'
chars. After enabling some debug info, it appeared that it would always
start by
Dear Robert,
In message camdmj5pj_aqzaxtrdnvs8ju_skvhv7zodrbuyhgjt2jfr4o...@mail.gmail.com
you wrote:
board/boundary/nitrogen6x/nitrogen6x.c | 22 ++
include/configs/nitrogen6x.h | 11 ++-
2 files changed, 32 insertions(+), 1 deletion(-)
Could
Dear Ruud,
In message
15ae5a936f5e3a42a9144e66875a0a89309...@server1-derijp.clb-Benelux.lokaal you
wrote:
I have been testing for a while now on the i.mx28 evk, and I noticed
that almost all tftp transfers take some time before they actually
start. It will show a 'T' as first character,
On Mon, May 06, 2013 at 03:17:44PM +0200, Andre Przywara wrote:
(for GIT URL and Changelog see below)
ARM CPUs with the virtualization extension have a new mode called
HYP mode, which allows hypervisors to safely control and monitor
guests. The current hypervisor (KVM and Xen) implementations
SPANSION recommend S25FL128S supersedes S25FL129P, and the two flash
memory have the same device ID and Memory architecture. So they can
use the same config parameters.
Signed-off-by: Xie Xiaobo x@freescale.com
---
drivers/mtd/spi/spansion.c | 2 +-
1 file changed, 1 insertion(+), 1
On 31/05/2013 08:56, Ruud Commandeur wrote:
Hi everyone,
Hi Ruud,
When tracing the code, it could see that fec_send is called for the 1st
ARP request and also the return value indicates that sending should have
been succeeded (fec_send: status 0xc00 index 0 ret 0). But no package is
On 29/05/2013 16:46, Benoît Thébaudeau wrote:
Hi Alison,
Hi Benoit,
I have just noticed that this was actually in 6/7. Why are you putting
this into a separate patch?
[Alison Wang] Because patch 2/7 is about VF610 CPU support, and
doc/README.vf610 is also a document about
VF610 SoC.
On 05/31/2013 03:02 AM, Christoffer Dall wrote:
Christoffer,
thanks a lot for the thorough review. Comments inline.
On Mon, May 06, 2013 at 03:17:45PM +0200, Andre Przywara wrote:
A prerequisite for using virtualization is to be in HYP mode, which
requires the CPU to be in non-secure state.
On 05/31/2013 05:04 AM, Christoffer Dall wrote:
On Mon, May 06, 2013 at 03:17:46PM +0200, Andre Przywara wrote:
While actually switching to non-secure state is one thing, the
more important part of this process is to make sure that we still
have full access to the interrupt controller (GIC).
On 05/31/2013 07:10 AM, Christoffer Dall wrote:
On Mon, May 06, 2013 at 03:17:47PM +0200, Andre Przywara wrote:
To actually trigger the non-secure switch we just implemented, call
the switching routine from within the bootm command implementation.
This way we automatically enable this feature
On 05/31/2013 07:32 AM, Christoffer Dall wrote:
On Mon, May 06, 2013 at 03:17:48PM +0200, Andre Przywara wrote:
Currently the non-secure switch is only done for the boot processor.
To later allow full SMP support, we have to switch all secondary
cores into non-secure state also.
So we add an
On 05/31/2013 07:43 AM, Christoffer Dall wrote:
On Mon, May 06, 2013 at 03:17:49PM +0200, Andre Przywara wrote:
For the KVM and XEN hypervisors to be usable, we need to enter the
kernel in HYP mode. Now that we already are in non-secure state,
HYP mode switching is within short reach.
While
Hi, Tom.
We would probably want to change it to something like:
- Do you want the standard baud rate table?
Yes: 9600/19200/38400/57600/115200
No: Prompt for string value of comma sep list of rates
And in the right header:
#ifdef CONFIG_SYS_STD_BAUD_RATE
#define BAUDRATTE_TABLE {
Stefano, Wolfgang,
Thanks for your comments. The CONFIG_ARP_TIMEOUT was not set, so it will
take the default of 5 seconds. This is also the time it takes for the
first timeout. If I add a
#define CONFIG_ARP_TIMEOUT200UL
to my board config, I see the ARP request succeed after 2 to 4
Hi Tom,
On 30/05/13 20:07, Tom Rini wrote:
On Thu, May 30, 2013 at 10:37:42AM -0400, Tom Rini wrote:
On Thu, May 30, 2013 at 01:24:42AM +0300, Lubomir Popov wrote:
Tested on OMAP4/5 only, but should work on older OMAPs and
derivatives as well.
- Rewritten i2c_read to operate correctly with
Hi Tom,
[snip]
But, crap, breaks am335x_evm (and probably beaglebones, etc). I'll
dig into this more to see if I can spot something obvious tomorrow.
Made it work on the am335x_evm (tested, with AM3359 on board).
Problem was in the new i2c_probe, which on this board is called by
the SPL
When compressed image is loaded, it must be decompressed
to an aligned address + 2 to avoid unaligned access exception
on some ARM platforms.
Signed-off-by: Piotr Wilczek p.wilc...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
CC: Anatolij Gustschin ag...@denx.de
CC: Wolfgang
On Fri, May 31, 2013 at 07:01:01PM +0900, Masahiro Yamada wrote:
Hi, Tom.
We would probably want to change it to something like:
- Do you want the standard baud rate table?
Yes: 9600/19200/38400/57600/115200
No: Prompt for string value of comma sep list of rates
And in the
There is no other call other than spi_flash_cmd_wait_ready(),
hence removed spi_flash_cmd_poll_bit and use the poll status code
spi_flash_cmd_wait_ready() itself.
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
---
Changes for v2:
- none
drivers/mtd/spi/spi_flash.c
Add support for Numonyx N25Q1024A SPI flash.
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
---
Changes for v2:
- none
drivers/mtd/spi/stmicro.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/mtd/spi/stmicro.c b/drivers/mtd/spi/stmicro.c
index
Add support for Numonyx N25Q1024 SPI flash.
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
---
Changes for v2:
- none
drivers/mtd/spi/stmicro.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/mtd/spi/stmicro.c b/drivers/mtd/spi/stmicro.c
index
Add support for Numonyx N25Q512A SPI flash.
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
---
Changes for v2:
- none
drivers/mtd/spi/stmicro.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/mtd/spi/stmicro.c b/drivers/mtd/spi/stmicro.c
index
Add support for Spansion S25FL512S_256K SPI flash.
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
---
Changes for v2:
- none
drivers/mtd/spi/spansion.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/mtd/spi/spansion.c b/drivers/mtd/spi/spansion.c
This patch provides support to read a flash bank address register.
reading extended/bank address register will give whether the flash
is operated on extended/bank addressing or normal addressing in
3-byte address mode.
Currently added an extended/bank address register reading support
for
Read the flash bank addr register to get the state of bank in
a perticular flash. and also bank write happens only when there is
a change in bank selection from user.
bank read only valid for flashes which has 16Mbytes those are
opearted in 3-byte addr mode, each bank occupies 16Mytes.
Suppose
Instead of using spi_xfer for SPI_XFER_BEGIN and SPI_XFER_END
separatley use common read call spi_flash_read_common() which
does the same.
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
---
Changes for v2:
- none
drivers/mtd/spi/spi_flash.c | 17 +
1 file
Updated the spi_flash framework to handle all sizes of flashes
using bank/extd addr reg facility
The current implementation in spi_flash supports 3-byte address mode
due to this up to 16Mbytes amount of flash is able to access for those
flashes which has an actual size of 16MB.
As most of the
This patch provides support to read a flash extended address
register for winbond and stmicro SPI flashes.
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
---
Changes for v2:
- none
drivers/mtd/spi/spi_flash.c | 2 ++
drivers/mtd/spi/spi_flash_internal.h | 1 +
2
Use the existing spi_flash_addr() for 3-byte addressing
cmd filling in write call.
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
---
Changes for v2:
- none
drivers/mtd/spi/spi_flash.c | 7 ++-
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git
This patch provides support to program a flash bank address
register.
extended/bank address register contains an information to access
the 4th byte addressing in 3-byte address mode.
Currently added an bank address register writing support for
spansion flashes.
reff' the spec for more details
Add support for Numonyx N25Q512 SPI flash.
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
---
Changes for v2:
- none
drivers/mtd/spi/stmicro.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/mtd/spi/stmicro.c b/drivers/mtd/spi/stmicro.c
index
Flag status register polling is required for micron 512Mb flash
devices onwards, for performing erase/program operations.
Like polling for WIP(Write-In-Progress) bit in read status register,
spi_flash_cmd_wait_ready will poll for PEC(Program-Erase-Control)
bit in flag status register.
This patch updated the spi_flash read func to support all
sizes of flashes using bank reg addr facility.
The same support has been added in below patch for erase/write
spi_flash functions:
sf: Support all sizes of flashes using bank addr reg facility
(sha1:
This patch provides support to program a flash extended address
register for winbond and stmicro SPI flashes.
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
---
Changes for v2:
- none
drivers/mtd/spi/spi_flash.c | 2 ++
drivers/mtd/spi/spi_flash_internal.h | 1 +
This series is v2 for the patch series sent few weeks back with a head
sf: Accessing 16MBytes flashes in existing 3-byte addr mode.
The current implementation in sf supports 3-byte address mode due
to this up to 16MB amount of flash is able to access for those
flashes which has an actual size
No real success here yet. By using a scope I did see that at least the
MAC is trying to send the 1st packet (activity on RMII TXD part). On the
Phy, the clock is running, LED's are blinking, but the 1st packet
doesn't come out. Although: occasionally it does. Also no clues found in
the datasheet
On Wed, Apr 24, 2013 at 04:11:20PM +0530, Sricharan R wrote:
The save_boot_params function does not store the data in a
always writable area. So the code is broken for a 'XIP' boot.
This series corrects this by storing it in 'gd' and also
adds a 'C' equivalent function for the same. The
Dear Stefano Babic,
In message 51a86445.3040...@denx.de you wrote:
At first glance the problem should be with the set up of the phy. It
could take longer as expected, or there are some issues with the
specific PHY of the board. An issue in general code of FEC driver is not
probable, because
Dear Piotr Wilczek,
In message 136573-15449-1-git-send-email-p.wilc...@samsung.com you wrote:
When compressed image is loaded, it must be decompressed
to an aligned address + 2 to avoid unaligned access exception
on some ARM platforms.
If you do this, you must also account for the up to 2
On Fri, May 31, 2013 at 10:18:46AM -0400, Tom Rini wrote:
On Wed, Apr 24, 2013 at 04:11:20PM +0530, Sricharan R wrote:
The save_boot_params function does not store the data in a
always writable area. So the code is broken for a 'XIP' boot.
This series corrects this by storing it in 'gd'
Dear Wolfgang, Stefano,
I'm pretty sure I found the cause:
For each tftp transfer the ethernet part is re-initialised. This means
that also fec_init is called. And in fec_init this piece of code
resides:
#ifndef CONFIG_PHYLIB
if (fec-xcv_type != SEVENWIRE)
Hi Ruud,
On 31/05/2013 16:36, Ruud Commandeur wrote:
Dear Wolfgang, Stefano,
I'm pretty sure I found the cause:
For each tftp transfer the ethernet part is re-initialised. This means
that also fec_init is called. And in fec_init this piece of code
resides:
#ifndef CONFIG_PHYLIB
Hi Wolfgang,
From your report, it looks like that the link of the phy is not yet
active when the fec_send is called, and then no ARP message is sent.
The question is if there is no better way to wait for the PHY to
become (really) ready?
The phy is reinitialized after each transaction -
pixis_reset help command prints the message without a new line \n,
which makes the prompt on the same line.
Signed-off-by: York Sun york...@freescale.com
---
board/freescale/common/pixis.c |2 ++
1 file changed, 2 insertions(+)
diff --git a/board/freescale/common/pixis.c
Hi Stefano,
On Fri, May 31, 2013 at 12:46 PM, Stefano Babic sba...@denx.de wrote:
The phy is reinitialized after each transaction - the safiest condition
to boot afterwards the kernel. Or we need a way to stop the phy only
before booting, letting it on for the whole time. But again, this
On Fri, May 31, 2013 at 1:13 PM, Xie Xiaobo x@freescale.com wrote:
SPANSION recommend S25FL128S supersedes S25FL129P, and the two flash
memory have the same device ID and Memory architecture. So they can
use the same config parameters.
Signed-off-by: Xie Xiaobo x@freescale.com
---
Hi Stefano,
On Friday, May 31, 2013 10:59:03 AM, Stefano Babic wrote:
On 29/05/2013 16:46, Benoît Thébaudeau wrote:
Hi Alison,
Hi Benoit,
I have just noticed that this was actually in 6/7. Why are you putting
this into a separate patch?
[Alison Wang] Because patch 2/7 is about
Hi Alison,
On Tuesday, May 28, 2013 10:55:46 AM, Alison Wang wrote:
This patch adds Vybrid VF610 to mxc_ocotp document.
Signed-off-by: Alison Wang b18...@freescale.com
---
Changes in v4: New
Changes in v3: None
Changes in v2: None
doc/README.mxc_ocotp | 1 +
1 file changed, 1
Hi Andre,
On Fri, 31 May 2013 11:23:16 +0200, Andre Przywara
andre.przyw...@linaro.org wrote:
software_interrupt is currently a panic routine. So it is not actually
used by u-boot, it's just there to dump some state and eventually call
reset_cpu().
So I feel that since I am now the only
On Fri, May 31, 2013 at 12:49 AM, Wolfgang Denk w...@denx.de wrote:
Dear Robert,
In message
camdmj5pj_aqzaxtrdnvs8ju_skvhv7zodrbuyhgjt2jfr4o...@mail.gmail.com you
wrote:
board/boundary/nitrogen6x/nitrogen6x.c | 22 ++
include/configs/nitrogen6x.h |
Only called in this file, mark as static.
Signed-off-by: Tom Rini tr...@ti.com
---
arch/arm/cpu/armv7/omap-common/hwinit-common.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv7/omap-common/hwinit-common.c
We need to call the save_omap_boot_params function on am33xx/ti81xx and
other newer TI SoCs, so move the function to boot-common. Only OMAP4+
has the omap_hw_init_context function so add ifdefs to not call it on
am33xx/ti81xx. Call save_omap_boot_params from s_init on am33xx/ti81xx
boards.
Prior to Sricharan's cleanup of the boot parameter saving code, we
did not make use of NON_SECURE_SRAM_START on am33xx, so it wasn't a
problem that the address was pointing to the middle of our running SPL.
Correct to point to the base location of the download image area.
Increase
On 05/23/2013 04:52:26 AM, Jérôme Arzel wrote:
Hi all,
I have an issue when I compile U-Boot for my target machine (P1022DS,
36-bit).
Here is the error message:
release.S: Assembler messages:
release.S:154: Error: operand out of range (0xf144 is not between
0x and 0x)
Dear Stefano,
[Joe added to Cc: list]
In message 51a8c479.6010...@denx.de you wrote:
This means (in this case) that miiphy_restart_aneg() is called. And here
the phy gets a software reset and autonegotiation restart command, wich
can take up to 500 msces according to the datasheet. So
Dear Stefano Babic,
In message 51a8c5da.3090...@denx.de you wrote:
The question is if there is no better way to wait for the PHY to
become (really) ready?
The phy is reinitialized after each transaction - the safiest condition
to boot afterwards the kernel. Or we need a way to stop the
On 5/31/2013 11:58 AM, Wolfgang Denk wrote:
Dear Stefano Babic,
In message 51a8c5da.3090...@denx.de you wrote:
The question is if there is no better way to wait for the PHY to
become (really) ready?
The phy is reinitialized after each transaction - the safiest condition
to boot afterwards the
New i2c_read, i2c_write and i2c_probe functions, tested on OMAP4
(4430/60/70), OMAP5 (5430) and AM335X (3359); should work on older
OMAPs and derivatives as well. The only anticipated exception would
be the OMAP2420, which shall require driver modification.
- Rewritten i2c_read to operate
The following changes since commit 8bcb6f43e98ffc76e998349e0ec32a0e359160d4:
Update MAINTAINERS file for sandbox (2013-05-17 17:04:39 -0400)
are available in the git repository at:
git://git.denx.de/u-boot-nand-flash.git master
for you to fetch changes up to
On Thu, May 30, 2013 at 09:29:21PM +0200, Albert ARIBAUD wrote:
Hello Tom,
The following changes since commit
a71d45d706a5b51c348160163b6c159632273fed:
powerpc/mpc85xx: Clear L1 D-cache lock (2013-05-24 16:54:14 -0500)
are available in the git repository at:
Tom == Tom Rini tr...@ti.com writes:
Tom Prior to Sricharan's cleanup of the boot parameter saving code, we
Tom did not make use of NON_SECURE_SRAM_START on am33xx, so it wasn't a
Tom problem that the address was pointing to the middle of our running SPL.
Tom Correct to point to the base
On Fri, May 31, 2013 at 02:52:17PM -0500, Scott Wood wrote:
The following changes since commit 8bcb6f43e98ffc76e998349e0ec32a0e359160d4:
Update MAINTAINERS file for sandbox (2013-05-17 17:04:39 -0400)
are available in the git repository at:
git://git.denx.de/u-boot-nand-flash.git
On 05/31/2013 04:28:41 PM, Tom Rini wrote:
On Fri, May 31, 2013 at 02:52:17PM -0500, Scott Wood wrote:
The following changes since commit
8bcb6f43e98ffc76e998349e0ec32a0e359160d4:
Update MAINTAINERS file for sandbox (2013-05-17 17:04:39 -0400)
are available in the git repository at:
On Fri, May 31, 2013 at 04:44:45PM -0500, Scott Wood wrote:
On 05/31/2013 04:28:41 PM, Tom Rini wrote:
On Fri, May 31, 2013 at 02:52:17PM -0500, Scott Wood wrote:
The following changes since commit
8bcb6f43e98ffc76e998349e0ec32a0e359160d4:
Update MAINTAINERS file for sandbox
v2: Amended the resync commit due to include/mtd/mtd-abi.h being
missing (it was present locally as an uncommitted file, which is why I
didn't see build failures).
The following changes since commit 8bcb6f43e98ffc76e998349e0ec32a0e359160d4:
Update MAINTAINERS file for sandbox (2013-05-17
[1] http://www.mail-archive.com/u-boot at lists.denx.de/msg108301.html
This gives 404 not found...
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On Fri, May 31, 2013 at 11:26:06AM +0200, Andre Przywara wrote:
On 05/31/2013 05:04 AM, Christoffer Dall wrote:
On Mon, May 06, 2013 at 03:17:46PM +0200, Andre Przywara wrote:
While actually switching to non-secure state is one thing, the
more important part of this process is to make sure
On Fri, May 31, 2013 at 11:23:16AM +0200, Andre Przywara wrote:
On 05/31/2013 03:02 AM, Christoffer Dall wrote:
Christoffer,
thanks a lot for the thorough review. Comments inline.
On Mon, May 06, 2013 at 03:17:45PM +0200, Andre Przywara wrote:
A prerequisite for using virtualization is
On Fri, May 31, 2013 at 08:36:12AM +0200, Andre Przywara wrote:
On 05/31/2013 08:11 AM, Christoffer Dall wrote:
On Mon, May 06, 2013 at 03:17:44PM +0200, Andre Przywara wrote:
(for GIT URL and Changelog see below)
ARM CPUs with the virtualization extension have a new mode called
HYP
On Fri, May 31, 2013 at 11:30:32AM +0200, Andre Przywara wrote:
On 05/31/2013 07:10 AM, Christoffer Dall wrote:
On Mon, May 06, 2013 at 03:17:47PM +0200, Andre Przywara wrote:
To actually trigger the non-secure switch we just implemented, call
the switching routine from within the bootm
On Fri, May 31, 2013 at 11:34:38AM +0200, Andre Przywara wrote:
On 05/31/2013 07:43 AM, Christoffer Dall wrote:
On Mon, May 06, 2013 at 03:17:49PM +0200, Andre Przywara wrote:
For the KVM and XEN hypervisors to be usable, we need to enter the
kernel in HYP mode. Now that we already are in
On Fri, May 31, 2013 at 11:32:40AM +0200, Andre Przywara wrote:
On 05/31/2013 07:32 AM, Christoffer Dall wrote:
On Mon, May 06, 2013 at 03:17:48PM +0200, Andre Przywara wrote:
Currently the non-secure switch is only done for the boot processor.
To later allow full SMP support, we have to
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