SE 14.7 and not Vivado. We have just begun to
> use Vivado for our Virtex 7 board e.g SKARAB. As far as I am aware, all
> the the ROACH2 development in SKA-SA has been done using Xilinx ISE 14., as
> it supports Virtex 6 devices.
>
> Kind Regards,
>
> Adam
>
>
&
Hi Adam
I got ISE to run. It open up die GUI. How do I start the sysgen with MATLAB?
Sorry about the queations.
Thank you for your help
Heystek
On Sun, Aug 14, 2016 at 12:06 PM, Heystek Grobler <heystekgrob...@gmail.com>
wrote:
> Good day Adam
>
> I have been working throug
gt; files.
>
> I have also attached scripts if you just want to run the programs
> individually - you will need to edit the path to where your installs are.
>
> Good luck. This should get you going. If the scripts bomb out then it is
> likely that your paths are not correct - check t
> files, but I gave you mine as I know it works.
>
> Kind Regards,
>
> Adam
>
> On Mon, Aug 15, 2016 at 10:58 AM, Heystek Grobler <
> heystekgrob...@gmail.com> wrote:
>
>> Hi Adam
>>
>> I will try these files! Do I run the startup.m file in matlab
en?id=1o7Wl7wzB7VE1Cckk60B35WerJv
>> l5crXa7Q5xbcoYgE0
>>
>> This should be read in conjunction with the CASPER wiki page -
>> https://casper.berkeley.edu/wiki/MSSGE_Setup_with_Xilinx_1
>> 4.x_and_Matlab_2012b - did you follow "tweaks to be able to compile"?
&g
Good Day
My name is Heystek Grobler. I am an electrical en electronic engineering
science student and for my final year project (skripsie) I'm developing a
wideband spectrometer on a ROACH-2 board.
Currently I have a problem with Xilinx System Generator and MATLAB. The
Simulink Model runs
> fix things then there might be stranger issues at play.
>
> Regards,
> James
>
>
> On Tue, Aug 16, 2016 at 5:36 PM, Heystek Grobler <heystekgrob...@gmail.com
> > wrote:
>
>> Hi James and Adam
>>
>> I got it working. The chmod +x startsg command did the
ld be a bit easier to debug if you posted the terminal session,
>> along with the commands you ran.
>>
>> Also, please run "ls -l" in the directory and post that as well. It might
>> just be that you need to give the file executable permissions.
>>
>> Regard
e assumption that you are based near the Cape Town area? If
>> I am correct and if you are still experiencing difficulties why not bring
>> your machine and pop over? I think this may be the easiest solution :).
>> Just email me directly if you favour this option.
>>
>
> chmod +x startsg
>
> Then you should be fine.
>
> Regards,
> James
>
>
> On Mon, Aug 15, 2016 at 7:46 PM, Heystek Grobler <heystekgrob...@gmail.com
> > wrote:
>
>> Hi Adam and James
>>
>> I am working on my personal computer. I will ask
>> If you're trying to build one of the tutorials, make sure you're either
>> using the correct library version -- see the instructions at
>> https://casper.berkeley.edu/wiki/Tutorials (which I hope has been kept
>> up to date) -- or, after opening a tutorial, run
>> &
on
> would at least help you narrow down the possibilities as to what's wrong
> (i.e. whether it's the kernel on the ROACH2).
>
> Disclaimer: I work only on ROACH, but I'm fairly certain the procedure
> would be the same.
>
> Regards,
> James
>
>
> On Fri, Sep 30, 2016 at 1:36 PM
Good day everyone
I am having difficulties programming the ROACH 2 board. I am following the
instructions of CASPER tutorial one.
I Have compiled the fpg file and is using the following steps from the
tutorial.
1. I entered ipython into the terminal
2. import casperfpga
3.
now your setup.
>
> Kind Regards,
>
> Adam
>
>
> On Fri, Sep 30, 2016 at 3:38 PM, Heystek Grobler <heystekgrob...@gmail.com
> > wrote:
>
>> Hi James
>>
>> I will try it. Through the terminal I can ping the board, but I cant open
>> a Teln
o Heystek,
>
> If you're still in the Python environment, then PySpead is the one you
> want.
>
> Regards,
> James
>
>
> On Fri, Oct 7, 2016 at 10:59 AM, Heystek Grobler <heystekgrob...@gmail.com
> > wrote:
>
>> Good Day
>>
>> After
t; Cheers
> Jack
>
> On Tue, 20 Sep 2016 at 13:32 Heystek Grobler <heystekgrob...@gmail.com>
> wrote:
>
>> Hi Michael
>>
>> Thanks for your help. I will try to obtain a license for the DSP System
>> Toolbox.
>>
>> Have a wonderful evening
&g
Good evening
I am trying to do the casper tutorial nr 3 on Ubuntu 14.04 LTS with ISE
14.7.
When I say update model in Simulink or run System generator I get the
following error:
Failed to load library 'dspsigops' referenced by 'tut3/adc/Downsamplei0'
Caused by:
Unable to load block diagram
Toolbox unfortunately, in order to compile the ADC
> blocks. This is typically a paid-for toolbox, though my local IT Services
> were helpful and had a few spare server licences.
>
>
>
> BW
> Michael
>
>
>
> *From:* Heystek Grobler [mailto:heystekgrob...@gmail.
Hi Michael
This is the toolboxes that I have:
MATLAB Version: 8.0.0.783 (R2012b)
MATLAB License Number: 724504
Operating System: Linux 3.19.0-68-generic #76~14.04.1-Ubuntu SMP Fri Aug 12
11:46:25 UTC 2016 x86_64
Java Version: Java 1.6.0_17-b04 with Sun Microsystems Inc. Java HotSpot(TM)
64-Bit
always a chance it will work, but my guess is you'll run into all
> kinds of strange problems. If you can, I'd *strongly* recommend trying to
> get hold of a supported MATLAB version.
>
> Jack
>
> On Wed, 21 Sep 2016 at 00:43 Heystek Grobler <heystekgrob...@gmail.com>
> wro
> fractions of your ADC bandwidth.
>
> Regards,
> James
>
>
> On Mon, Oct 17, 2016 at 9:52 PM, Heystek Grobler <heystekgrob...@gmail.com
> > wrote:
>
>> Hi Everyone
>>
>> I got it wot king using the following commands:
>>
>> ipython --py
ays done
> with no problems.)
>
> Before you try that though, perhaps just try importing spead in ipython as
> Ryan did. What are the error messages?
>
> Regards,
> James
>
>
> On Fri, Oct 7, 2016 at 11:23 AM, Heystek Grobler <heystekgrob...@gmail.com
> >
ite your own script, using this one as a
> guide. You'd learn a lot about how things work in the process. Not a quick
> fix to your problem, I'll admit, but it'll be an education.
>
> Regards,
> James
>
>
> On Tue, Oct 11, 2016 at 1:33 PM, Heystek Grobler <heystekgro
ey wrote:
> >
> > Some of the earlier scripts had bad error handling. If anything fails
> before the host object was successfully created, then you get this error
> because it tries to close the connection before exiting.
> >
> > Jason
> >
> > On 11 Oct 2016, at 16:09,
in the
> terminal and see if it displays on the screen.
>
> Good luck,
> Jason
>
>
>
>
> On 3/22/2017 3:08 PM, Heystek Grobler wrote:
>
> Hi
>
> When I use dev/tty* I can see the adapter. This is the adapter Im using
>
> https://www.unitek-products.co
Hi Jason
I got my hands on a JTAG. I went through the CASPER debricking tutorial
page but I dont understand how to use the converter script? Do you perhaps
know how to use it?
Thanks for all of your help
Heystek
On Mon, Mar 27, 2017 at 11:54 AM, Heystek Grobler <heystekgrob...@gmail.com>
ootup.pdf
>
> And, this procedure as well...
> https://casper.berkeley.edu/wiki/ROACH_kernel_uboot_update
>
> Hope this helps,
> Jason
>
>
>
> On 3/29/2017 8:45 AM, Heystek Grobler wrote:
>
> Hi Jason
>
> I got my hands on a JTAG. I went through the CASPER debri
Good day
I have an interesting problem. I'm used to working on a ROACH2 and now I
must do a project on a ROACH1 board.
When Running the casperfpga package I received this error:
In [1]: import casperfpga
In [2]: fpga=casperfpga.katcp_fpga.KatcpFpga('192.168.33.3')
In [3]:
are needed to simulate and netlist designs using blocks
from Xilinx System Generator for DSP blockset.
Does anyone perhaps know how to solve this?
Thanks for the help
Heystek Grobler
--
You received this message because you are subscribed to the Google Groups
"casper@lists.berkeley.edu&q
> xlAddSysgen([getenv('XILINX_PATH'), '/ISE'])
>
> Toss in an extra slash at the end of the path:
> xlAddSysgen([getenv('XILINX_PATH'), '/ISE/'])
>
> Now, I still haven't sorted the REST of the debian/xilinx issues
> that's tomorrows problem :-)
>
>
>
> On 08/11/2017
, James Smith <jsm...@ska.ac.za> wrote:
> Hello Heystek,
>
> Where is your Xilinx library installed? See if you can cd to the directory
> that it refers to?
>
> Regards,
> James
>
>
> On Fri, Aug 11, 2017 at 11:17 AM, Heystek Grobler <
> heystekgrob...@g
oing to have to check those environment variables, and see whether
> they're actually pointing to their targets.
>
>
> On Fri, Aug 11, 2017 at 11:29 AM, Heystek Grobler <
> heystekgrob...@gmail.com> wrote:
>
>> Hi James
>>
>> I Installed Xilinx under:
>>
”];
then
LD_LIBRARY_PATH=${XILINX_PATH}/ISE/lib/lin64;
echo “Using LD_LIBRARY_PATH=${LD_LIBRARY_PATH}”
export LD_LIBRARY_PATH;
fi
Then Matlab and Xilinx will work on Debian.
Have a great day
Heystek
On Fri, Aug 11, 2017 at 10:58 AM, Heystek Grobler <heystekgrob...@gmail.com>
Good day everyone
I have encountered a weird problem. Everything was working fine until
today. I cant upload a .bof file to my roach1. I keep getting this error:
#log error 2947729786047 poco ulpoad\_process\_exitet\_with\_code\_69
I have tried uploading the file through kapcp and telnet but
> Long shot - could you have run out of space on the roach ?
>>
>> On Mon, May 15, 2017 at 7:39 AM, Heystek Grobler
>> <heystekgrob...@gmail.com> wrote:
>> > Good day everyone
>> >
>> > I have encountered a weird problem. Everything was working f
to the katadc and gave it a square wave at 50MHz.
Am I doing something stupid? Or is there another yellow block that I should
rather use.
Have a great day
Heystek Grobler
--
You received this message because you are subscribed to the Google Groups
"casper@lists.berkeley.edu" group.
To u
connected your katadc? (Both physically and with the yellow block)?
>
> Regards,
> James
>
>
> On Wed, May 17, 2017 at 9:46 AM, Heystek Grobler <heystekgrob...@gmail.com
> > wrote:
>
>> Good day everyone
>>
>> I am trying to implement tutorial 3 on a
Hi everyone
Does anyone know what is the best clock signal for a ROACH1 and ROACH2
board and will a sign wave do and at what level?
Thanks for all the help
Heystek
--
You received this message because you are subscribed to the Google Groups
"casper@lists.berkeley.edu" group.
To unsubscribe
to be able to compile a bof
file. Does anyone perhaps know what inputs I should connect/use?
Have a great day
Thanks for the help
Heystek Grobler
--
You received this message because you are subscribed to the Google Groups
"casper@lists.berkeley.edu" group.
To unsubscribe from
, Heystek Grobler <heystekgrob...@gmail.com>
wrote:
> Good day
>
> I have an interesting problem. I'm used to working on a ROACH2 and now I
> must do a project on a ROACH1 board.
>
> When Running the casperfpga package I received this error:
>
> In [1]: impo
d suggest putting software registers into atten0 and atten1 then
> writing to them from a Python script. You can adjust the attenuation from 0
> dB to 31.5 dB in 0.5 dB increments using a 5-bit number.
>
> Regards,
> James
>
>
>
> On Mon, May 8, 2017 at 2:17 PM, Heystek Gro
Good day!
I had a simular problem at the beginning of the year with a ROACH1 board.
What are the symptoms of your board? What happens when you hit the power
button?
Kind regards
Heystek
On Tue, 12 Sep 2017 at 6:50 PM pei...@xao.ac.cn wrote:
> Hi All,
>
> We have a ROACH2
edit (line 66)
File 'implementation/system.twr' not found.
>>
Could it be the pcores?
Thanks for the help
Heystek
On Mon, Aug 28, 2017 at 10:23 AM, Amit Bansod <aban...@mpifr-bonn.mpg.de>
wrote:
> Hi,
>
> Can you try to update design (ctrl + D) to see if you get more informatio
Good day everyone!
I have one more weird problem. If I run casper_xps and start the
compilation, everything works until the file creation part. I keep getting
this error:
casper_xps
Detected Linux OS#
## System Update ##
#
"./mkbof" instead of just "mkbof"?
>
> Dave
>
>
> On Aug 31, 2017, at 23:50, Heystek Grobler <heystekgrob...@gmail.com>
> wrote:
>
> Hi Michael
>
> If I run mkbof -o system.bof –s core_info.tab -t 3 system.bit it gives
> the following
Hi Everyone :-)
My apologies for bugging everyone again.
I want to know I would I be able to compile/create a .bof file if I un-tick
the last box on the casper_xps screen?
I have a unique problem where casper_xps does not run if the last box is
ticked.
Thanks for the help
Heystek :-)
--
You
ve a look at the memo I wrote on the Casper memos page (the one
> with SmartXplorer in the title) which tells you how to do this.
>
>
>
> Cheers
>
> Michael
>
>
>
> *From:* Heystek Grobler [mailto:heystekgrob...@gmail.com]
> *Sent:* 31 August 2017 20:22
> *To:*
rocess Exec Failed:2
ERROR:EDK -
Error while running "gmake -f system.make netlist".
ERROR: synthesizing XPS module failed!
Process "XPS Process: Synthesize XPS Source" failed
So it seams like that gmake -f is the problem?
On Fri, Sep 1, 2017 at 9:42 AM, Heystek Grobler &l
Hi Michael!
I have found my problem. My OS did not have the “make” library installed.
Everything is compiling now.
Thanks for all the help :-)
Heystek
On Fri, Sep 1, 2017 at 11:09 AM, Heystek Grobler <heystekgrob...@gmail.com>
wrote:
> Hi Michael
>
> I have also tried compiling
Hi Francisco
Thats good news!
Have a great day
Heystek
On Fri, 17 Nov 2017 at 19:54, Francisco Casado <fcas...@ug.uchile.cl> wrote:
> Thank you! I managed to get things working :)
>
>
>
>
>
> 2017-11-14 15:35 GMT-03:00 Heystek Grobler <heystekgrob...@gmail.com&g
Hi Francisco
I had exactly the same issue about a year ago. Luckily the Matlab licences
are backwards compatible. You say that your university has a 2015 Matlab
licence? Then you can use that licence to download and use a 2012 version
from the Matlab site.
I hope that it helps
Heystek
On
Good day CASPERites
I am trying to compile a deign for a ROACH2 but I get the following error:
NGDBUILD Design Results Summary:
Number of errors: 2
Number of warnings: 10272
Total REAL time to NGDBUILD completion: 2 min 48 sec
Total CPU time to NGDBUILD completion: 2 min 41 sec
One
Hey Jack and Adam
https://github.com/casper-astro/mlib_devel/issues/7
That is the exact error I can into
Heystek
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Hey Michael
Did you try this procedure?
https://casper.ssl.berkeley.edu/wiki/ROACH_kernel_uboot_update
Did you manage to solve it?
Heystek
On Fri, Mar 15, 2019 at 5:45 PM Michael Peel wrote:
> Hi all,
>
> I’m currently trying to set up a ROACH2 (for the first time), and have run
> into a
ersion of the library you're using?
>
> Cheers
> Jack
>
> On Fri, 8 Mar 2019 at 01:15, Heystek Grobler
> wrote:
>
>> Hey Franco and Jack
>>
>> I have cheked that I have done the post install "fixes"
>>
>> I have traced the error to the
ed, 6 Mar 2019 at 09:47, Franco wrote:
>
>> I'm not sure but did you make the modifications required
>> post-installation:
>> https://github.com/casper-astro/tutorials_devel/wiki#modifications-to-be-run-after-installs
>> ?
>>
>> I remember having a similar e
lying an FFT to frequency-domain data will get you back
> into the time domain, multiplied by some scaling factor. You need both halves
> of the symmetric FFT though, so the output of e.g. the fft_wideband_real
> wouldn't be meaningful to apply another FFT to it.
>
> Regards,
> Jame
Good day Casperites
I have an interesting question. I am using a FFT in simulink for the use in a
spectrometer design. I want to test the output of the FFT by using some kind of
scope. Simulink only has spectrum scope, that would be perfect, but the scope
does a second FFT on the signal. The
Good day everyone.
I have encountered a weird problem. I have a python script that makes use of
pylab. When importinf pylab, I get this error:
PyUnicodeUCS4_FromString
I have tried to use import matplotlib.pyplot as plt and I get the same error. I
have googled it, but nothing seems to help.
;
> I haven’t seen this before. Is there anything in your working directory that
> the import statement could be confusing with your desired module? Perhaps try
> changing your working directory.
>
> GL
> Mike
>
> From: Heystek Grobler [mailto:heystekgrob...@gmai
Good day everyone
I am running a design but ran into this problem:
xflow done!
touch __xps/system_routed
xilperl /opt/Xilinx_ISE/14.7/ISE_DS/EDK/data/fpga_impl/observe_par.pl
-error yes implementation/system.par
Analyzing implementation/system.par
to a point where the place-and-route can find
> a layout that satisfies timing requirements.
>
> It's a bit of a black art, always hit and miss for me.
>
> Regards,
> James
>
>
>
>
> On Wed, Aug 26, 2020 at 8:00 AM Heystek Grobler <mailto:heystekgrob...@
oj/myproj.runs/impl_1/top_timing_summary_routed.rpt
>
> Just a note - this file is usually fairly large as text files go ~20MB.
>
> Regards,
> Andrew
>
> On Wed, Aug 26, 2020 at 10:22 AM Heystek Grobler <mailto:heystekgrob...@gmail.com>> wrote:
> Hey James and Andre
u
> can force a name-change if you want using the network manager (I did it in
> RHEL, unsure about Ubuntu) but better to find a solution from Mathworks if
> you can. What does the indicated solution say?
>
> Good luck,
> Mike
>
>
> From: Heystek Grobler [mailto
Hello everyone
I have a bit of a problem. The first time that I am experiencing it. I am
trying to install Matlab 2012B on a Ubuntu machine (That I redid), but the
installation gives this error:
[image: Screenshot from 2020-08-17 17-55-44.png]
Does anyone perhaps know how to fix this?
Heystek
ou will need to change as well (e.g. if you
> have /etc/network/interfaces - you'll need to update that too).
>
>
>
> Regards,
>
> james
>
>
>
>
>
> On Tue, Aug 18, 2020 at 10:51 AM Heystek Grobler
> wrote:
>
> Hey Mike
>
>
>
> Thank you for
e:
>
>> Hi Heystek,
>>
>> It's possible that you then have another issue that causes the build
>> process to exit prior to generating that file. You'll need to debug that
>> first.
>>
>> Regards,
>> Andrew
>>
>> On Wed, Aug 26, 2020 at
go.
>
> Cheers
> Jack
>
> On Tue, 11 Aug 2020 at 14:39, Heystek Grobler <mailto:heystekgrob...@gmail.com>> wrote:
> Hey James
>
> Below is a snipped:
>
>
>
>> On 11 Aug 2020, at 15:24, James Smith > <mailto:jsm...@ska.ac.za>> wrote:
Good day everyone
I am compiling a design for Roach2. I can into this error when running
casper_xps:
"xilinx input gateways cannot be used in a design. Only gpio blocks”
How can I solve this or am I doing something stupid?
Thanks for the help
Heystek
--
You received this message because
in your design, you are trying to use a Xilinx block as an input.
> Replace it with one of the yellow blocks from the Casper tools, and you
> should be okay. (Usually this will be a software register or a BRAM block.)
>
> Regards,
> James
>
>
> On Tue, A
Hey James
Below is a snipped:
> On 11 Aug 2020, at 15:24, James Smith wrote:
>
> Send a screen snip of what you've got, Heystek?
>
> On Tue, Aug 11, 2020 at 1:22 PM Heystek Grobler <mailto:heystekgrob...@gmail.com>> wrote:
> Hey James and Mugundhan
>
> Tha
Good day everyone.
I was hoping that someone can perhaps help me or can point me in the right
direction.
I want to write sine and cosine waves to BRAM blocks in order to implement
a local oscillator. I have a basic idea of how to do this by making use of
a struct that needs to be packed, but in
d can
> generate different frequencies with the same lookup table. Amplitude can be
> scaled as needed.
>
> Hope this helps.
>
> Regards,
> Andrew
>
> On Fri, Nov 26, 2021 at 3:49 PM Heystek Grobler <mailto:heystekgrob...@gmail.com>> wrote:
> Hey Andrew
- 2^-31. Reducing the
>> magnitude of your sinusoid so that the peak value is below this maximum
>> would work. Or alternatively, scaling your values by an amount less than
>> 2^31 would have the same effect.
>>
>> Morag
>>
>> On Thu, Nov 25, 2021 at 8:5
ens wrote:
>
> Hi Heystek
>
> Simulink has a maximum BRAM size of 64k (16 bits address size). A 32 bit
> address size would equate to 4G addresses, which is far larger than the
> amount of BRAM available in the FPGA.
>
> Regards
> Andrew
>
> On Fri, Nov
re trying to write to it?
>
> Morag
>
> On Thu, Nov 25, 2021 at 6:59 PM Heystek Grobler <mailto:heystekgrob...@gmail.com>> wrote:
> Hey Morag and Jack
>
> Thank you for the suggestions.
>
> I played around a little bit. if I create the sine wave the s
ocumentation/user_guides/ug363.pdf>)
> describes this mapping. The one detail that is not covered there is when
> the FPGA data port is 64 bits wide. In that case, you need to convert the
> 64-bit value to big endian, but then swap the low 32-bits and high-32 bits,
> though
Hey Jack.
Should I then try to get a SysGen/ModelComposer license for 2021.1 or is there
a way to still use Vivado 2020.06 with the RFSoC?
Thank you for the help!
Heystek
-
Heystek Grobler
0832721009
heystekgrob...@gmail.com
. Will it suffice if the University gets the Xilinx
ML Enterprise Edition and SysGen or should something else be added to it?
Thank you for the help!
Heystek
-
Heystek Grobler
0832721009
heystekgrob...@gmail.com
On Sun, Oct 1, 2023 at 6:09 PM
-
Heystek Grobler
0832721009
heystekgrob...@gmail.com
> On 13 Jun 2022, at 05:32, Wang wrote:
>
> Hello CASPER,
>
> How's it going?I am currently using ROACH2.
>
> However, there are always some problems when booting up, and I want to try
> another Linux system.
my way around
the casper stuff.
I hope it helps.
Heystek
> On 13 Jun 2022, at 14:42, 王钊 wrote:
>
> Thank you much Heystek!
>
> You've been very helpful to me.
>
> Heystek Grobler mailto:heystekgrob...@gmail.com>>
> 于2022年6月13日周一 19:33写道:
> Hey Wang
Hey Mitch.
Thank you for the reply.
The Python version that my system is returning is 3.7.13.
Should I rather use Python 3.8? I have noticed that matlab2021a does not
support python3.9.
Thank you
-
Heystek Grobler
0832721009
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