Re: [google gcc-4_9]: Backport trunk:r232727 fix for PR/69403.

LGTM thanks Carrot On Thu, Jan 28, 2016 at 11:53 AM, Han Shen wrote: > Backport trunk:r232727 fix for PR/69403 - wrong > thumb2_ior_scc_strict_it insn pattern. > > Note this only affect armv7-a tuned for armv8 arch, tested / booted > affected ChromeOS book. > > Ok for

[PATCH, Google] Backport trunk patch r220860 to google/4.9 branch

Hi In aarch64 backend of google/4.9 branch, the split pattern for insn aarch64_lshr_sisd_or_int_mode3 destroys one of the source operands, causes the later usage of the operand get a wrong value (google bug 17907351). The bug has been fixed in trunk by r220860. This patch backports it to

Re: [PATCH, Google] Notify df framework when removing an insn in simplify-got

On Tue, Jun 9, 2015 at 11:43 PM, Richard Sandiford richard.sandif...@arm.com wrote: Carrot Wei car...@google.com writes: Index: simplify-got.c === --- simplify-got.c (revision 224174) +++ simplify-got.c (working copy) @@ -169,7

[PATCH, Google] Notify df framework when removing an insn in simplify-got

Hi I forgot to notify df framework when I removed an insn, it caused df verification failure described in google bug b/16155462. The following patch passed regression test on arm qemu in both thumb and arm modes. OK for google 4.9 branch? Index: simplify-got.c

[PATCH, GOOGLE] Backport patch r212222 to google 4.9 branch

Hi The more strict devirtualization condition in this patch helps to fix google bug b/19872411. Bootstraped and regression tested on x86-64. OK for google 4.9 branch? patch Description: Binary data

[GOOGLE] Avoid calling walk_aliased_vdefs in O0 function

This patch fixes google internal bug b/19277289. It can only be reproduced in google 4.9 branch. In function param_change_prob, there is following function call walk_aliased_vdefs (refd, gimple_vuse (stmt), record_modified, info, NULL); If the source code is compiled with optimization, but cfun

[Google] Port patch r215585 to Google/4.9 branch

Hi In Google application we hit the same problem as https://gcc.gnu.org/bugzilla/show_bug.cgi?id=63341, so we also need the patch r215585 for Google/4.9 branch. It passed following tests: bootstrap and regression test on x86-64. regression test on ppc. Google reference 18687126. OK for

Re: [Google] Port patch r215585 to Google/4.9 branch

Yes, it has been long time since last merge, so it is good idea to do another merge. On Tue, Dec 16, 2014 at 11:32 AM, Xinliang David Li davi...@google.com wrote: The fix is already in upstream gcc-4.9 branch? If yes, we just need a merge. David On Tue, Dec 16, 2014 at 11:30 AM, Carrot Wei

Re: [PATCH PR63530] Fix the pointer alignment in vectorization

to DR_MISALIGNMENT. 2014-10-22 Guozhi Wei car...@google.com PR tree-optimization/63530 gcc.dg/vect/pr63530.c: New testcase. On Tue, Oct 21, 2014 at 1:04 AM, Richard Biener richard.guent...@gmail.com wrote: On Mon, Oct 20, 2014 at 10:10 PM, Carrot Wei car...@google.com wrote

Re: [PATCH PR63530] Fix the pointer alignment in vectorization

Biener richard.guent...@gmail.com wrote: On Fri, Oct 17, 2014 at 7:58 PM, Carrot Wei car...@google.com wrote: I miss a testcase. I also miss a comment before this code explaining why DR_MISALIGNMENT if not -1 is valid and why it is not valid if DR_MISALIGNMENT (dr) == -1 means some unknown

[PATCH PR63530] Fix the pointer alignment in vectorization

Hi In current vectorization pass, when a new vector pointer is created, its alignment is not set correctly. We should use DR_MISALIGNMENT (dr) since only this alignment is adjusted when loop peeling or multi version is occurred. This patch passed following tests: x86_64 bootstrap. x86_64

Re: [Google 4.9] Backport of r210828

LGTM. Your description could be more detail, such as which tests on which target. On Tue, Oct 7, 2014 at 2:06 PM, Sterling Augustine saugust...@google.com wrote: The enclosed patch for google 4.9 is a backport of r210828 from trunk. googleref:b/14623977 The given tests now pass when run by

Re: [Patch AArch64] Fix extended register width

Ping. On Mon, Sep 22, 2014 at 11:41 AM, Carrot Wei car...@google.com wrote: Hi The extended register width in add/adds/sub/subs/cmp instructions is not always the same as target register, it depends on both target register width and extension type. But in current implementation the extended

[Patch AArch64] Fix extended register width

Hi The extended register width in add/adds/sub/subs/cmp instructions is not always the same as target register, it depends on both target register width and extension type. But in current implementation the extended register width is always the same as target register. We have noticed it can

Re: [Patch AArch64] Fix for PR62040

...@gmail.com wrote: On 20 August 2014 20:51, Carrot Wei car...@google.com wrote: Good suggestion. Add the testcase. thanks Guozhi Wei 2014-08-20 Guozhi Wei car...@google.com PR target/62040 * gcc.target/aarch64/pr62040.c: New test. Index: pr62040.c

Re: [Patch AArch64] Fix for PR62040

AArch64 maintainers, could you help to review following patches? https://gcc.gnu.org/ml/gcc-patches/2014-08/msg01966.html https://gcc.gnu.org/ml/gcc-patches/2014-08/msg02060.html thanks Guozhi Wei On Wed, Aug 20, 2014 at 12:51 PM, Carrot Wei car...@google.com wrote: Good suggestion. Add

[Patch AArch64] Fix for PR62262

Hi In insn pattern *andim_ashiftmode_bfiz, if the operands[2] is larger than the size of register, gcc may generate invalid assembler code. If operands[2] is larger than the size of the underlying type of INTVAL, the following insn condition may also be undefined. exact_log2 ((INTVAL

Re: [Patch AArch64] Fix for PR62040

...@arm.com wrote: Hi Carrot, cc'ing the aarch64 maintainers... On 20/08/14 00:43, Carrot Wei wrote: Hi Current AArch64 backend can generate rtl expressions like (vec_duplicate:DI (const_int 0 [0])), which causes ICE in simplify_const_unary_operation because vec_duplicate should generate

[Patch AArch64] Fix for PR62040

Hi Current AArch64 backend can generate rtl expressions like (vec_duplicate:DI (const_int 0 [0])), which causes ICE in simplify_const_unary_operation because vec_duplicate should generate vector mode only. As suggested by Andrew in the bug entry, I split the original insn patterns to avoid

Re: [PATCH powerpc64] Add a new constraint to insn movdi_internal64

, Aug 06, 2014 at 04:48:26PM -0700, Carrot Wei wrote: - mtvsrd %x0,%1 - [(set_attr type store,load,*,*,*,*,fpstore,fpload,fp,mfjmpr,mtjmpr,*,mftgpr,mffgpr,mftgpr,mffgpr) - (set_attr length 4,4,4,4,4,20,4,4,4,4,4,4,4,4,4,4)]) + mtvsrd %x0,%1 + xxlxor %x0,%x0 + [(set_attr type store

Re: [PATCH, AArch64] Fix for PR61202

...@gmail.com wrote: On 20 May 2014 18:37, Carrot Wei car...@google.com wrote: Hi James Thank you for pointing this out. In the new patch I removed the modification of vqdmulh_n_s32 and vqdmulhq_n_s32. Passed dejagnu testing on aarch64 qemu again. OK for trunk, 4.9 and 4.8? 2014-05-20

[PATCH, AArch64] Fix for PR61202

Hi The last operand of instruction sqdmulh can only be low fp registers, so we should use constraint x. But the intrinsic functions use w. This patch fixed the constrains in these intrinsics. Passed dejagnu test on aarch64 qemu. OK for trunk, 4.9 and 4.8? thanks Guozhi Wei 2014-05-19 Guozhi

Re: [PATCH, AArch64] Fix for PR61202

): Change the last operand's constraint. (vqdmulhq_n_s16): Likewise. On Mon, May 19, 2014 at 11:50 PM, James Greenhalgh james.greenha...@arm.com wrote: On Tue, May 20, 2014 at 07:18:40AM +0100, Carrot Wei wrote: Hi Hi, The last operand of instruction sqdmulh can only be low fp

[PATCH] Fix a typo in sparseset_pop

Hi The following patch fixes an obvious wrong index used to access the dense array. The patch has passed the bootstrap and regression tests on x86-64. OK for trunk? thanks Carrot 2014-02-23 Guozhi Wei car...@google.com * sparseset.h (sparseset_pop): Fix the wrong index. Index:

Re: [google/gcc-4_7]Add new validator file for native ppc toolchain

OK for google/gcc-4_7. On Wed, Jun 5, 2013 at 2:45 PM, Jing Yu jin...@google.com wrote: Add new validator manifest xfail file for native powerpc64 toolchain. Ok for google/gcc-4_7? Tested: ./validate_failures.py --manifest=powerpc64-grtev3-linux-gnu-native.xfail -- results=gcc/gcc.sum

[GOOGLE] Remove records in powerpc64-grtev3-linux-gnu.xfail

Hi Since b/8397853 has been fixed, the related tests now passed, so we can remove them from powerpc64-grtev3-linux-gnu.xfail now. Tested with ./buildit --run_tests. OK for google 4.7 branch? thanks Carrot 2013-05-29 Guozhi Wei car...@google.com * powerpc64-grtev3-linux-gnu.xfail (***

Re: [Patch][google/gcc-4_8] Backport trunk@198547 for pr target/56732

OK for google branches. On Thu, May 9, 2013 at 1:40 PM, Han Shen(沈涵) shen...@google.com wrote: Hi, I'm to backport trunk patch @198547 for pr target/56732 to google branch google/gcc-4_8. This patch fixes arm ICE. Ok for google/gcc-4_8? [patch attached] H.

[RFC] Make the new var decl STATIC in function dw2_output_indirect_constant_1

Hi In function dw2_output_indirect_constant_1 a new var decl is created. Only When the variable is not PUBLIC it is allocated static storage. Does anybody know why the variable is not allocated static storage by marking TREE_STATIC when it is PUBLIC? The following patch marks the STATIC flag in

[GOOGLE] Check conditions before calling varpool_node

This patch fixed google bug entry 6124850. The usage of varpool_node has some restrictions on the corresponding var decl. In LIPO mode function notice_global_symbol may call varpool_node with a decl that doesn't satisfy these restrictions since the function notice_global_symbol can be directly or

Re: [GOOGLE] Check conditions before calling varpool_node

didn't consider the restrictions of varpool_node since it couldn't be called from there? thanks Carrot David On Thu, May 9, 2013 at 11:39 AM, Carrot Wei car...@google.com wrote: This patch fixed google bug entry 6124850. The usage of varpool_node has some restrictions on the corresponding var

Re: [Patch][google/gcc-4_8] Backport trunk@198344 into google/gcc-4_8

OK for google branch. Should it also be in gcc4.8 branch? thanks Carrot On Tue, May 7, 2013 at 12:01 PM, Han Shen(沈涵) shen...@google.com wrote: Backport trunk@198344 - another fix to PR rtl-optimization/56847 - to google/gcc-4_8 branch. The first fix was trunk@198101 -

Re: [google][4.7] Move the building of gcov constructor function after initialization of gcov_info_var

. thanks, David On Thu, May 2, 2013 at 11:06 AM, Carrot Wei car...@google.com wrote: This patch fixes google bug 8397853 and targets google 4.7 branch. In LIPO mode, when coverage_obj_init is called, cgraph_state is CGRAPH_STATE_FINISHED. The variable gcov_info_var is created but not initialized

Re: [PATCH] Refactor coverage.c, outline the construction of gcov constructor

On Fri, May 3, 2013 at 1:03 AM, Richard Biener richard.guent...@gmail.com wrote: On Thu, May 2, 2013 at 10:41 PM, Carrot Wei car...@google.com wrote: This patch outline the construction of gcov constructor from coverage_obj_init as a separate function build_init_ctor. It passed bootstrap

Re: [PATCH] Refactor coverage.c, outline the construction of gcov constructor

commited as 198591. On Fri, May 3, 2013 at 11:51 AM, Xinliang David Li davi...@google.com wrote: Please do what Richard suggested. gcov_info_type can be obtained from gcov_info_var decl. David On Fri, May 3, 2013 at 11:31 AM, Carrot Wei car...@google.com wrote: On Fri, May 3, 2013 at 1:03

[google][4.7] Move the building of gcov constructor function after initialization of gcov_info_var

This patch fixes google bug 8397853 and targets google 4.7 branch. In LIPO mode, when coverage_obj_init is called, cgraph_state is CGRAPH_STATE_FINISHED. The variable gcov_info_var is created but not initialized. When cgraph_build_static_cdtor is called, the new function and variables are

[PATCH] Refactor coverage.c, outline the construction of gcov constructor

This patch outline the construction of gcov constructor from coverage_obj_init as a separate function build_init_ctor. It passed bootstrap and regression test on x86-64. OK for trunk and google 4.7 branch? thanks Carrot 2013-05-02 Guozhi Wei car...@google.com * coverage.c

Re: [PATCH] Prevent cselib substitution of FP, SP, SFP

Hi Jakub I have run it on 4.6, it passes the following testing: x86-64 bootstrap x86-64 regression test regression test on arm qemu Is it OK for gcc4.6? Ahmad, is it OK for google/gcc-4_6/ and google/gcc-4_6-mobile ? thanks Carrot On Wed, Sep 12, 2012 at 2:01 PM, Carrot Wei car...@google.com

Re: [PATCH] Prevent cselib substitution of FP, SP, SFP

Hi Jakub The same problem also affects gcc4.6, http://gcc.gnu.org/bugzilla/show_bug.cgi?id=54398. Could this be ported to 4.6 branch? thanks Carrot On Mon, Feb 13, 2012 at 11:54 AM, Jakub Jelinek ja...@redhat.com wrote: On Wed, Jan 04, 2012 at 05:21:38PM +, Marcus Shawcroft wrote: Alias

Re: [google/gcc-4_7] Backport arm hardfp patch from trunk

OK for google/gcc-4_7. thanks Carrot On Tue, Aug 14, 2012 at 7:14 AM, Han Shen(沈涵) shen...@google.com wrote: Hi Carrot, could you take a look at this patch? Thanks! The modification is in upstream trunk patch revision - 186859. The same patch has been back ported to google/gcc-4_6

Re: [ARM Patch 1/3]PR53189: optimizations of 64bit logic operation with constant

On Tue, Jul 17, 2012 at 9:47 PM, Ramana Radhakrishnan ramana.radhakrish...@linaro.org wrote: Carrot, Sorry about the delayed response. On 3 July 2012 12:28, Carrot Wei car...@google.com wrote: On Thu, Jun 28, 2012 at 12:14 AM, Ramana Radhakrishnan ramana.radhakrish...@linaro.org wrote

Re: [ARM Patch 1/3]PR53189: optimizations of 64bit logic operation with constant

On Wed, Jul 18, 2012 at 5:39 PM, Ramana Radhakrishnan ramana.radhakrish...@linaro.org wrote: On 18 July 2012 09:20, Carrot Wei car...@google.com wrote: On Tue, Jul 17, 2012 at 9:47 PM, Ramana Radhakrishnan ramana.radhakrish...@linaro.org wrote: Carrot, Sorry about the delayed response

[Ping, ARM]PR53189: optimizations of 64bit logic operation with constant

Hi The following patches implemented the optimizations suggested by PR53189, optimizations of 64bit logic operation with constant. Could any maintainer help to review it? http://gcc.gnu.org/ml/gcc-patches/2012-07/msg00087.html http://gcc.gnu.org/ml/gcc-patches/2012-07/msg00169.html

Re: [ARM Patch 3/3]PR53189: optimizations of 64bit logic operation with constant

, %1, %2\; + case 1: return \orn%?\\t%0, %1, #%B2\; + case 2: return \#\; + } + } TARGET_32BIT GET_CODE (operands[2]) == CONST_INT !(const_ok_for_arm (INTVAL (operands[2])) On Tue, Jun 5, 2012 at 5:14 PM, Carrot Wei car...@google.com wrote: Hi This is the fourth

Re: [ARM Patch 2/3]PR53189: optimizations of 64bit logic operation with constant

\\; + } + } + +if (which_alternative == 0) + return \eor%?\\t%0, %1, %2\; +else + return \#\; + } TARGET_32BIT GET_CODE (operands[2]) == CONST_INT !const_ok_for_arm (INTVAL (operands[2])) On Wed, May 30, 2012 at 5:22 PM, Carrot Wei car...@google.com wrote: Hi This is the third part

Re: [ARM Patch 1/3]PR53189: optimizations of 64bit logic operation with constant

On Thu, Jun 28, 2012 at 12:14 AM, Ramana Radhakrishnan ramana.radhakrish...@linaro.org wrote: On 28 May 2012 11:08, Carrot Wei car...@google.com wrote: Hi This is the second part of the patches that deals with 64bit and. It directly extends the patterns anddi3, anddi3_insn and anddi3_neon

Re: [ARM Patch 1/n] PR53447: optimizations of 64bit ALU operation with constant

On Fri, Jun 29, 2012 at 9:57 PM, Ramana Radhakrishnan ramana.radhakrish...@linaro.org wrote: On 29 June 2012 12:23, Carrot Wei car...@google.com wrote: Hi So the following is updated patch. Tested on qemu with arm/thumb modes Assuming this testing was with and without neon ? Because

Re: [ARM Patch 1/n] PR53447: optimizations of 64bit ALU operation with constant

Hi So the following is updated patch. Tested on qemu with arm/thumb modes without regression. thanks Carrot 2012-06-29 Wei Guozhi car...@google.com PR target/53447 * gcc.target/arm/pr53447-1.c: New testcase. * gcc.target/arm/pr53447-2.c: New testcase. 2012-06-29

Re: [ARM Patch 1/n] PR53447: optimizations of 64bit ALU operation with constant

Hi Ramana Thanks for the review, please see my inlined comments. On Thu, Jun 28, 2012 at 12:02 AM, Ramana Radhakrishnan ramana.radhakrish...@linaro.org wrote: On 8 June 2012 10:12, Carrot Wei car...@google.com wrote: Hi In rtl expression, substract a constant c is expressed as add

Re: [ARM Patch 1/n] PR53447: optimizations of 64bit ALU operation with constant

On Thu, Jun 28, 2012 at 5:37 PM, Ramana Radhakrishnan ramana.radhakrish...@linaro.org wrote: On 28 June 2012 10:03, Carrot Wei car...@google.com wrote: Hi Ramana Thanks for the review, please see my inlined comments. On Thu, Jun 28, 2012 at 12:02 AM, Ramana Radhakrishnan ramana.radhakrish

Re: [PING ARM Patches] PR53447: optimizations of 64bit ALU operation with constant

ping^2 thanks Carrot On Mon, Jun 18, 2012 at 6:17 PM, Carrot Wei car...@google.com wrote: Hi Could ARM maintainers review following patches? http://gcc.gnu.org/ml/gcc-patches/2012-06/msg00497.html 64bit add/sub constants. http://gcc.gnu.org/ml/gcc-patches/2012-05/msg01834.html 64bit

Re: [PING ARM Patches] PR53447: optimizations of 64bit ALU operation with constant

duplicated the alternatives in normal cases. thanks Carrot On Wed, Jun 20, 2012 at 9:58 AM, Michael Hope michael.h...@linaro.org wrote: On 18 June 2012 22:17, Carrot Wei car...@google.com wrote: Hi Could ARM maintainers review following patches? http://gcc.gnu.org/ml/gcc-patches/2012-06/msg00497

[PING ARM Patches] PR53447: optimizations of 64bit ALU operation with constant

Hi Could ARM maintainers review following patches? http://gcc.gnu.org/ml/gcc-patches/2012-06/msg00497.html 64bit add/sub constants. http://gcc.gnu.org/ml/gcc-patches/2012-05/msg01834.html 64bit and with constants. http://gcc.gnu.org/ml/gcc-patches/2012-05/msg01974.html 64bit xor with

Re: [ARM Patch 1/n] PR53447: optimizations of 64bit ALU operation with constant

, Carrot Wei car...@google.com wrote: In the original patch, if add r0, c is not possible, but sub r0, -c is possible, it will use the sub instruction. Although they generate same result, but they may generate different CF flag, and cause subsequent adc to compute out wrong result. So I updated

Re: [ARM Patch 1/n] PR53447: optimizations of 64bit ALU operation with constant

(ARM_SIGN_EXTEND (v 0x)); + } +else + { + operands[5] = gen_highpart (SImode, operands[2]); + operands[2] = gen_lowpart (SImode, operands[2]); + } } [(set_attr conds clob) (set_attr length 8)] On Mon, Jun 4, 2012 at 5:55 PM, Carrot Wei car...@google.com wrote

[ARM Patch 4/n]PR53447: optimizations of 64bit ALU operation with constant

Hi This is the fourth part of the patches that deals with 64bit ior. It directly extends the patterns iordi3, iordi3_insn and iordi3_neon to handle 64bit constant operands. Tested on arm qemu without regression. OK for trunk? thanks Carrot 2012-06-05 Wei Guozhi car...@google.com PR

Re: [ARM Patch 1/n] PR53447: optimizations of 64bit ALU operation with constant

] = gen_lowpart (SImode, operands[2]); + } } [(set_attr conds clob) (set_attr length 8)] On Sat, May 26, 2012 at 9:42 PM, Carrot Wei car...@google.com wrote: Hi, As described in PR53447, many 64bit ALU operations with constant can be optimized to use corresponding 32bit

[ARM Patch 3/n]PR53447: optimizations of 64bit ALU operation with constant

Hi This is the third part of the patches that deals with 64bit xor. It extends the patterns xordi3, xordi3_insn and xordi3_neon to handle 64bit constant operands. Tested on arm qemu without regression. OK for trunk? thanks Carrot 2012-05-30 Wei Guozhi car...@google.com PR

[ARM Patch 2/n]PR53447: optimizations of 64bit ALU operation with constant

Hi This is the second part of the patches that deals with 64bit and. It directly extends the patterns anddi3, anddi3_insn and anddi3_neon to handle 64bit constant operands. Tested on arm qemu without regression. OK for trunk? thanks Carrot 2012-05-28 Wei Guozhi car...@google.com PR

[ARM Patch 1/n] PR53447: optimizations of 64bit ALU operation with constant

Hi, As described in PR53447, many 64bit ALU operations with constant can be optimized to use corresponding 32bit instructions with immediate operands. This is the first part of the patches that deals with 64bit add. It directly extends the patterns adddi3, arm_adddi3 and adddi3_neon to handle

Re: [google/gcc-4_6_2-mobile] Port of Android target support in i386 for google/gcc-4_6_2-mobile branch

OK for Google branches. On Mon, May 7, 2012 at 12:21 PM, Jing Yu jin...@google.com wrote: I would like to port this patch to google/gcc-4_6 and also google/gcc-4_6_2-mobile. From reading the patch, it does not change config for non-Android target. bootstrap,crosstool tests finished

Re: [PATCH] Fix sibcall argument overlap checking if pretend_args_size (PR target/52129)

On Fri, Feb 10, 2012 at 2:13 PM, Jing Yu jin...@google.com wrote: On Thu, Feb 9, 2012 at 12:54 AM, Carrot Wei car...@google.com wrote: Hi Richard and Jakub Since 4.6 contains the same bug, I would like to back port it to 4.6 branch. Could you approve it for 4.6? Jing and Doug Could you

Re: [PATCH] Fix sibcall argument overlap checking if pretend_args_size (PR target/52129)

Hi Richard and Jakub Since 4.6 contains the same bug, I would like to back port it to 4.6 branch. Could you approve it for 4.6? Jing and Doug Could you approve it for google/gcc-4_6-mobile branch? thanks Carrot On Mon, Feb 6, 2012 at 9:14 PM, Richard Guenther richard.guent...@gmail.com wrote:

Re: [PATCH] Fix sibcall argument overlap checking if pretend_args_size (PR target/52129)

Hi Jakub Instead of disabling the sibcall, it could also be a valid tail call optimization by moving the str after ldmia, and change the used register(It should be handled by RA automatically), as following ... add r4, r1, r4, lsl #2 ldmia r2, {r1, r2}

Re: RFA: Avoid unnecessary clearing in union initialisers

On Fri, Dec 9, 2011 at 4:56 PM, Richard Sandiford richard.sandif...@linaro.org wrote: Carrot Wei car...@google.com writes: Since it also affects 4.6 branch, can this and r176270 also be ported to gcc4.6? Always worth asking, but in this case, I'm not sure it's appropriate. The patch

Re: RFA: Avoid unnecessary clearing in union initialisers

Since it also affects 4.6 branch, can this and r176270 also be ported to gcc4.6? thanks Carrot On Wed, Jul 13, 2011 at 12:34 AM, Richard Sandiford richard.sandif...@linaro.org wrote: PR 48183 is caused by the fact that we don't really support integers (or least integer constants) wider than

Re: [PATCH, PR43814] Assume function arguments of pointer type are aligned.

Hi Tom What's the behavior of your patch to the following case typedef int int_unaligned __attribute__((aligned(1))); int foo (int_unaligned *p) { return *p; } thanks Carrot On Tue, Sep 20, 2011 at 7:13 PM, Tom de Vries vr...@codesourcery.com wrote: Hi Richard, I have a patch for PR43814.

Re: [google] Backport r174965 from trunk to google/gcc-4_6 (issue4852046)

ping On Mon, Aug 8, 2011 at 11:00 AM, Guozhi Wei car...@google.com wrote: Hi I want to backport r174965 from trunk to google/gcc-4_6, which fixed vect-72.c failure in target arm, as described in http://gcc.gnu.org/ml/gcc-patches/2011-06/msg00927.html Tested with buildit and regression

Re: [testcase, arm] Adjust the negative offset of fp memory access in vfp-1.c

Ping On Wed, Jul 20, 2011 at 4:33 PM, Carrot Wei car...@google.com wrote: Oops, the ChangeLog should be 2011-07-20  Wei Guozhi  car...@google.com        * gcc.target/arm/vfp-1.c (test_ldst): Adjust negative offset. thanks Carrot On Wed, Jul 20, 2011 at 4:30 PM, Carrot Wei car

[PATCH] PR49799: Don't generate illegal bit field extraction instruction

Hi In function combine.c:make_compound_operation, it tries to transforms the expression (ashiftrt (ashift foo C1) C2) with C2 = C1 into SIGN_EXTRACT. It works pretty well in usual cases. But for the test case in PR49799, there is an expression (X (tmp-1)) 16 tmp is an uninitialized

Re: [PATCH] PR49799: Don't generate illegal bit field extraction instruction

, 2011 at 03:38:07PM +0800, Carrot Wei wrote: OK for trunk and 4.6? ChangeLog: 2011-07-28  Wei Guozhi  car...@google.com         PR rtl-optimization/49799         * combine.c (make_compound_operation): Check if the bit field is valid         before change it to bit field extraction

Re: [PATCH] PR49799: Don't generate illegal bit field extraction instruction

); thanks a lot. Carrot On Thu, Jul 28, 2011 at 4:47 PM, Jakub Jelinek ja...@redhat.com wrote: On Thu, Jul 28, 2011 at 04:40:53PM +0800, Carrot Wei wrote: ChangeLog: 2011-07-28  Wei Guozhi  car...@google.com         PR rtl-optimization/49799         * pr49799.c : New test case. Space

[testcase, arm] Adjust the negative offset of fp memory access in vfp-1.c

Hi The patch r169271 conservatively limits the offset of fp memory access to (-256..1024), but didn't adjust the related test case, so vfp-1.c fails in thumb2 mode after the patch. This patch modifies test case vfp-1.c accordingly. Tested with make check-gcc

Re: [testcase, arm] Adjust the negative offset of fp memory access in vfp-1.c

Oops, the ChangeLog should be 2011-07-20 Wei Guozhi car...@google.com * gcc.target/arm/vfp-1.c (test_ldst): Adjust negative offset. thanks Carrot On Wed, Jul 20, 2011 at 4:30 PM, Carrot Wei car...@google.com wrote: Hi The patch r169271 conservatively limits the offset of fp

Re: [google] Backport patch r175881 from gcc-4_6-branch to google/gcc-4_6 (issue4695051)

Hi Diego The previous patch was done with svn merge. This new version is done with svnmerge.py. Again tested with make check-g++ RUNTESTFLAGS=--target_board=arm-sim/thumb/arch=armv7-a dg.exp=anon-ns1.C make check-g++ RUNTESTFLAGS=dg.exp=anon-ns1.C BTW, there are some unexpected property

Re: [PATCH, ARM] PR47855 Compute attr length for thumb2 insns, 3/3 (issue4475042)

Thanks for the review. Richard, what's the situation of unaligned memory access and how does it conflict with this patch? thanks Carrot On Tue, Jun 7, 2011 at 6:42 PM, Nick Clifton ni...@redhat.com wrote: Hi Carrot, 2011-05-06  Guozhi Wei  car...@google.com        PR target/47855        *

Re: -fdump-passes -fenable-xxx=func_name_list

It also breaks arm backend. ../trunk/configure '--build=x86_64-build_pc-linux-gnu' '--host=x86_64-build_pc-linux-gnu' '--target=arm-unknown-linux-gnueabi' '--with-sysroot=/home/carrot/x-tools/arm-unknown-linux-gnueabi/arm-unknown-linux-gnueabi/sys-root' '--disable-multilib' '--with-float=soft'

Re: [google]Skip target-libiberty for arm*-*-linux-androideabi (issue4564050)

OK. thanks Carrot On Tue, Jun 7, 2011 at 1:09 AM, jin...@google.com wrote: The trunk version has been approved and committed as r174710. Backport it to google/main. The google/main version has the same logic but is slightly different since trunk has a different code structure here. OK for

Re: [google]Backport r174549 Fix 3 test cases incorrectly run in Thumb/Xscale (issue4524090)

OK for google/main. thanks Carrot On Thu, Jun 2, 2011 at 12:51 PM, Jing Yu jin...@google.com wrote: http://gcc.gnu.org/ml/gcc-patches/2010-10/msg00134.html Backport r174549 to fix three testcases that are specific to ARM mode and therefore should be skipped when compiling for thumb. Thanks,

Re: [google] Disable getpagesize() for Android toolchain (issue4515131)

Hi I've tested the #ifndef __ANDROID__ on arm qemu without regression. And also built Android toolchain without this error. thanks Carrot 2011-05-26 Jing Yu jin...@google.com * ChangeLog.google-main: New file. * getpagesize.c(getpagesize): Disable it for bionic. Index:

[PING] 3 ARM patches

Hi http://gcc.gnu.org/ml/gcc-patches/2011-03/msg01973.html Use ldrd and strd to access two consecutive words http://gcc.gnu.org/ml/gcc-patches/2011-05/msg00490.html Compute attr length for thumb2 insns http://gcc.gnu.org/ml/gcc-patches/2011-05/msg01092.html Replace 32 bit instructions with 16

Re: [PATCH: PR target/46975] Replace 32 bit instructions with 16 bit instructions in thumb2

On Fri, Dec 17, 2010 at 8:18 PM, Richard Earnshaw rearn...@arm.com wrote: On Thu, 2010-12-16 at 14:45 -0800, Carrot Wei wrote: Hi Compile the following c code with options -march=armv7-a -mthumb -Os int foo (int s) {     return s == 1; } GCC 4.6 generates: foo:    0

[PING] 2 ARM patches

Hi http://gcc.gnu.org/ml/gcc-patches/2011-03/msg01973.html Use ldrd and strd to access two consecutive words http://gcc.gnu.org/ml/gcc-patches/2011-05/msg00490.html Compute attr length for thumb2 insns thanks Carrot

Re: [PATCH, ARM] PR47855 Compute attr length for thumb2 insns, 3/3 (issue4475042)

On Thu, May 5, 2011 at 5:42 PM, Richard Earnshaw rearn...@arm.com wrote: On Thu, 2011-05-05 at 14:51 +0800, Guozhi Wei wrote: Hi This is the third part of the fixing for http://gcc.gnu.org/bugzilla/show_bug.cgi?id=47855 This patch contains the length computation/refinement for insn

Re: [google] Use R_ARM_GOT_PREL to simplify global address loading from GOT (issue4433079)

On Thu, Apr 28, 2011 at 10:08 PM, dnovi...@google.com wrote: I only have some stylistic comments for this patch.  The new pass looks OK to me, but I do not know this area well enough to do a good review. In your ChangeLog entries, please remove the directory prefix from the file names.

Re: [google] Use R_ARM_GOT_PREL to simplify global address loading from GOT (issue4433079)

Yes, after porting it to google/main. Carrot On Thu, Apr 28, 2011 at 10:26 PM, Diego Novillo dnovi...@google.com wrote: Will you be proposing this patch for trunk as well? Diego.

Re: [google] remove redundant push {lr} for -mthumb (issue4441050)

I will try this method for trunk later. thanks Carrot On Wed, Apr 20, 2011 at 4:48 PM, Richard Earnshaw rearn...@arm.com wrote: On Wed, 2011-04-20 at 16:26 +0800, Carrot Wei wrote: On Tue, Apr 19, 2011 at 8:55 PM, Richard Earnshaw rearn...@arm.com wrote: On Tue, 2011-04-19 at 17:41 +0800

Re: [google] remove redundant push {lr} for -mthumb (issue4441050)

On Tue, Apr 19, 2011 at 5:57 PM, Richard Guenther richard.guent...@gmail.com wrote: On Tue, Apr 19, 2011 at 11:41 AM, Guozhi Wei car...@google.com wrote: Reload pass tries to determine the stack frame, so it needs to check the push/pop lr optimization opportunity. One of the criteria is if

Re: [PATCH, ARM] PR47855 Compute attr length for some thumb2 insns, 2/3

, 2011-04-14 at 21:19 +0800, Carrot Wei wrote: On Fri, Apr 8, 2011 at 6:51 PM, Ramana Radhakrishnan ramana.radhakrish...@linaro.org wrote: On 08/04/11 10:57, Carrot Wei wrote: Hi This is the second part of the fixing for http://gcc.gnu.org/bugzilla/show_bug.cgi?id=47855 This patch

Re: [PATCH, ARM] PR47855 Compute attr length for some thumb2 insns

arm_attr_length_push_multi (operands[2], operands[1])))] ) (define_insn stack_tie On Thu, Apr 7, 2011 at 7:30 PM, Ramana Radhakrishnan ramana.radhakrish...@linaro.org wrote: On 07/04/11 12:08, Carrot Wei wrote: On Thu, Apr 7, 2011 at 5:31 PM, Richard Sandiford richard.sandif...@linaro.org  wrote: Hi

Re: [PATCH, ARM] PR47855 Compute attr length for some thumb2 insns

On Thu, Apr 7, 2011 at 5:31 PM, Richard Sandiford richard.sandif...@linaro.org wrote: Hi Carrot, Sorry if this has already been reported, but the patch breaks bootstrap of arm-linux-gnueabi (or cross builds with --enable-werror).  The problem is that this... uses a statement expression --

Re: [PATCH, ARM] PR47855 Compute attr length for some thumb2 insns

Hi Ramana On Wed, Mar 30, 2011 at 6:35 AM, Ramana Radhakrishnan ramana.radhakrish...@linaro.org wrote: Hi Carrot,        How about adding an alternative only enabled for T2 that uses the `l' constraint and inventing new constraints for some of the constant values that are valid for 16 bit

Re: [PATCH: ARM] PR 45335 Use ldrd and strd to access two consecutive words

-2.c: Changed to store 3 words. * gcc.target/arm/pr40457-3.c: Changed to store 3 words. On Thu, Mar 24, 2011 at 8:25 AM, Mike Stump mikest...@comcast.net wrote: On Jan 18, 2011, at 6:59 AM, Carrot Wei wrote: +(define_insn *ldrd +  [(parallel [(set (match_operand:SI 0

[PATCH, ARM] PR47855 Compute attr length for some thumb2 insns

Hi As described in http://gcc.gnu.org/bugzilla/show_bug.cgi?id=47855, there are many insn patterns don't compute attribute length correctly. This patch is the first and simplest part of the fixing. This patch has been tested on qemu. thanks Carrot ChangeLog: 2011-03-26 Wei Guozhi

Re: [PATCH: PR target/46975] Replace 32 bit instructions with 16 bit instructions in thumb2

Ping On Sat, Dec 18, 2010 at 3:30 AM, Carrot Wei car...@google.com wrote: On Fri, Dec 17, 2010 at 4:18 AM, Richard Earnshaw rearn...@arm.com wrote: On Thu, 2010-12-16 at 14:45 -0800, Carrot Wei wrote: Hi Compile the following c code with options -march=armv7-a -mthumb -Os int foo (int s

Re: [PATCH: ARM] PR 45335 Use ldrd and strd to access two consecutive words

The trunk is opened again, could any maintainers continue to review this patch? thanks Carrot On Tue, Jan 18, 2011 at 10:59 PM, Carrot Wei car...@google.com wrote: Ramana's method is to put the instruction output and counting in on place. So it's easy to keep them synchronized. My latest