On Mon, May 10, 2004 at 11:34:23AM -0800, Dave Baldwin enlightened us
thusly
> > I am not getting away from powering on, but I can avoid testing in
> > that situation by resetting on a watchdog timer. But are you telling
> > me that uPs in general _presume_ a power up reset even when the
> > reset might be from the watchdog? Bah!
>
> No I didn't mean that. But each does have a sequence that it goes
> thru at each reset.
I must be getting to be a real pain at this stage, Dave, and thanks for
taking me through this.
Let me summarise: Power on is a variable condition; resets with power
already applied varies to another pattern. The first clock pulse out of
reduced clock signals (E or pin 64 on HD6303XP, for instance) will not
be a reliable guide to the the beginning of meaningful activity. So I
will have to recognise address values.
>
> > Then I have to presume the integrity of the address bus. If I can't
> > get 0x0000 hex on the address bus, I can't begin. Mind you, if a
> > board is that badly shot, I'd probably find heat somewhere.
>
> A minor point but a number of microprocessors don't go to 0x0000 hex
> at reset. Reset vectors in some cases are in the 0xFF00 hex page and
> I believe the Motorola 68xx and the Hitachi 63xx are among those.
> Come to think of it, I believe that x86 reset goes to 0xFFFF00 hex to
> get it's first instruction after a reset.
As long as they all go to 0x 0000 fairly quick, I don't care. In this
scenario, internal reads are more or less invisible. My specific
intention is to be there while the uP wakes up it's support chips.
/imagination running wild
This could be good; If, for instance, I know the 8255 is on 0x22h, I
could start monitoring on seeing address 0x22h and read for 50 cycles
to see what the uP says to the 8255, and hear what the 8255 says back.
And from Bob Paddock: (Grateful thanks also Bob).
> The 6303 will fetch a two byte word from FFFE and jump to that
> location, on reset. RAM is at zero. As I recall, been a long time.
> I don't think I have any of the data sheets left here.
I have that datasheet, if I need it. I hope to avoid boning up at length
on uPs. It's a slow business. But it does go to 'that location'
(0x0000h) fairly quickly.
>
> > Then, let's think: Another settable address, or a presettable number
> > of clock cycles for the stop signal? Mebbe factor in ram & rom
> > checks.
> >
> > /tries to think it out. fails.
> >
> > Better do both cycle count and address recognition for the stop to
> > be sure to be sure. The quest for stability begins.
>
> Guess that's why some companies get big bucks for trying to solve this
> problem. Not easy to come in after the fact and troubleshoot these
> things.
Not from me :-D. I never had big bucks.
So, to summarise, I need to be able to do the following:
1. Output a start signal on a presettable address (from the
address bus). Often this would be 0x0000h
2. Given this start signal, output a stop on a clock count.
3. Alternatively, stop on another address.
4. Probably an optional reset signal just after the stop would
be nice to get another sample. Saves farting with a watchdog, and works
when there isn't such a device on the board.
That leaves out the nicety of uP signal lines, but in fact I can simply
tack those on to high order address bytes.
I'll think it out in hardware first, rather than set up another uP and
find out about timing problems.
All of this is probably do-able from 1 Eprom clip on the board for
boards with an eprom. After that, it gets messy here due to the range of
uPs I meet (80xx, 8088, 8085, Z80, TMS7000, PICs, ATMELs, HD64xxxx,
68xx, & 65xx being the common ones)
--
With best Regards,
Declan Moriarty.
--
Author: Declan Moriarty
INET: [EMAIL PROTECTED]
Fat City Hosting, San Diego, California -- http://www.fatcity.com
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