Is there any reason why the behaviour of a uP should vary from reset to
reset? I need repeatability over clock cycles for some range; about 10
clock cycles might be enough.
I want to test using clock cycle for clock cycle sampling. The digital
signature analysers (HP5004, 5005, & 5006) manufactured by HP offer a
checksum of a data stream, but very poor triggering options, which I am
seeking to extend :-D.
But if the cpu took an extra clock cycle to settle after a reset, the
result would be screwed. Is this a possibility?
The idea is to take a checksum of the data lines while a board wakes
up and checks everything.
--
With best Regards,
Declan Moriarty.
--
Author: Declan Moriarty
INET: [EMAIL PROTECTED]
Fat City Hosting, San Diego, California -- http://www.fatcity.com
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