> I am not getting away from powering on, but I can avoid testing in that
> situation by resetting on a watchdog timer. But are you telling me
> that uPs in general _presume_ a power up reset even when the reset might
> be from the watchdog? Bah!
>
> > > Then I would have a high on the reduced cpu clock ( 'E' or pin 64 on
> > > the HD6303XP & HD6303YP) until the xtal was set going. The time

> Then I have to presume the integrity of the address bus. If I can't get
> 0x0000 hex on the address bus, I can't begin. 

The 6303 will fetch a two byte word from FFFE and jump to that location,
on reset.  RAM is at zero.  As I recall, been a long time.  I don't think
I have any of the data sheets left here.

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Author: Bob Paddock
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