> Is there any reason why the behaviour of a uP should vary from reset to > reset? I need repeatability over clock cycles for some range; about 10 > clock cycles might be enough.
I can think of a lot of reasons from power supply conditions to reset circuit variations. Also, what kind of uP? Don't some have to wait for internal circuits to settle? Some only sample the reset line periodically like they do the interrupts. > I want to test using clock cycle for clock cycle sampling. The digital > signature analysers (HP5004, 5005, & 5006) manufactured by HP offer a > checksum of a data stream, but very poor triggering options, which I am > seeking to extend :-D. > > But if the cpu took an extra clock cycle to settle after a reset, the > result would be screwed. Is this a possibility? Note that power on reset can take hundreds to thousands of clock cycles waiting for the oscillator/clock to settle, I think it's very likely to happen. > The idea is to take a checksum of the data lines while a board wakes > up and checks everything. That may take a lot to get that idea to work. Lots of variation in that process. -=-=-=-=-=-=- "http://www.psyber.com/~dibsed"; -=-=-=-=-=-=- DIBs Electronic Design | Dave Baldwin: [EMAIL PROTECTED] Adapt and overcome. | Buy a book and read it. -=-=--=-=--=-=--=-=--=-=-=-=--=-=--=-=--=-=--=-=--=-=--=-=- -- Author: Dave Baldwin INET: [EMAIL PROTECTED] Fat City Hosting, San Diego, California -- http://www.fatcity.com --------------------------------------------------------------------- To REMOVE yourself from this mailing list, send an E-Mail message to: [EMAIL PROTECTED] (note EXACT spelling of 'ListGuru') and in the message BODY, include a line containing: UNSUB CHIPDIR-L (or the name of mailing list you want to be removed from). You may also send the HELP command for other information (like subscribing).
