On Wed, May 05, 2004 at 02:49:20AM -0800, Bob Paddock enlightened us
thusly
>
> > > > Is there any reason why the behaviour of a uP should vary from
> > > > reset to reset?
> >
> >
> > The HD6303xp & HD 6303YP are in mind.
>
> There are three mode pins that are read on reset on the 6303 family.
> Check the voltage levels at those pins as I recall they have odd
> thresholds. Hitachi gives diodes tied to reset as examples in the
> data sheets.
What are they? I see all the usual stuff: xtal, extal, reset,/read,
/write, read/write, /standby, /nmi, BA(Bus Availability) /LIR (Load
Instruction Register), and MP0,1 (Mode Program). I suppose if the MP
pins were wrong, that would screw things nicely. But they are held to
rails.
>
> We had a problem like that with them in the past. The chip might
> think it was in internal bus mode when you really wanted external bus
> mode for example.
>
> >No uP was mentioned on purpose.
>
> More details, equal better answers. I was about to delete this tread
> because I didn't think there was anything I could contribute to it,
> until I saw the 6303.
This was an attempt to drag the HP5006A I own off the 'never used'
shelf. For a guy like me, establishing the veracity of a data stream at
_any_ point is useful in verifying the board as good. It takes some of
the maybe's out of a repair. If I can be definite something is fixed, I
reduce the horrible business of fitters going out with a board that
doesn't work.
What the 5006 provides, however is a clock, start, and stop pulse. If
the tests are being designed in, this is no problem. I wanted to be able
to verify various uP boards by storing such data as checksums. Most
boards lack a suitable level change to be applied as start & stop. So I
cannot get a repeatable signal - no 2 checksums are the same :-(.
Like I said, back to the drawing board.
/goes off and waits for another 'bright' idea
--
With best Regards,
Declan Moriarty.
--
Author: Declan Moriarty
INET: [EMAIL PROTECTED]
Fat City Hosting, San Diego, California -- http://www.fatcity.com
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