On Sat, Dec 11, 2010 at 10:06:29PM -0800, Kirk Wallace wrote:
> On Sun, 2010-12-12 at 15:59 +1100, Erik Christiansen wrote:
> ... snip
> >  That's controlled by the C1/C2 ratio. Consider the
> > charge Q tranferred from C1 to C2 on one pulse:
> > 
> >    C1*V1 = Q = C2*V2
> > 
> > If C2 = 10*C1, then V2 = V1/10  , minus diode drops.
> 
> I found that even without a resistor across the bucket cap the bucket
> would leak pretty rapidly. I don't know if the leak was into the scope
> probe or something else. The 1X/10X probe setting didn't seem to make a
> difference. I would think this unknown leak would make the calculations
> more difficult, unless one could model the leak. The .1 to .3 uF C1/C2
> ratio seemed to pass all tests on the bench.

Well if the probe is 1Mohm, then the timeconstant is of the order of a
third of a second, with the probe in place. Since the input resistance
for a CMOS gate can be 10^14 Ohms (I haven't checked a schmitt gate,
though), it can be used as a very high impedance monitor. If C2 is
charged by briefly connecting +5v, after D2 & R2 are disconnected, then
"CP GOOD" should remain high for several months. After checking that it
stays high for minutes, you can reconnect D2, and repeat the experiment,
to see if it is leaky. If it is, then D1 is also, if C1 is OK. If
nothing makes much difference, then C2 is leaky. If it's e.g. a
"greencap", out of the junkbox, then that's eminently possible.

> ... snip
> > Hopefully that'll further help avoid the need to figure it all out the
> > hard way. (Just yell out if too many details are spoiling the
> > investigative fun. :-)
> > 
> > Erik
> 
> When I was much younger, I was pretty decent at math and pursued
> mechanical engineering because I was fascinated by the thought of being
> able the mathematically model a physical system and actually have the
> real system match. I dropped out, but I still like to try to play with
> math. Although, most times it's easier to guess and just get-r-done.

Yeah, just enough maths to get the componentry dimensioned, then build
it and see how it goes, suits me too. I was just average, so specialised
in digital electronics, back in the early '70s. There was less maths
and all the career scope of a nascent technology.

> I revised my circuit:
> http://www.wallacecompany.com/machine_shop/EMC2/Charge%20Pump/chpmp-5b.png 

I'm sorry that I always seem to find something to critique on those
circuits, but whereas parallelling a couple of schmitt gates should work
OK on a rapidly changing input, there is much greater risk of slightly
different input thresholds causing the outputs to contest, thereby
trying to short +5v to ground, when the input is slowly changing.
(Counted in nanoseconds)

There is then a lot to be said for removing IC1C, so the slow input is
discriminated only once. If pins 1 & 3 are then connected, any small
same-chip threshold variation will have negligible effect, because here
the input flank is rather vertical.

> I need to add a voltage regulator and filter caps, but there is no magic
> there. I've noticed Matt's circuit is leaner because it doesn't need
> one. My circuit might be improved with some I/O protection, but that
> will make it more complex.

For just one 74HC14, a resistor and 5.1v zener diode will do.

> I've ordered some 74HC14's in order to build my latest try, but I'm
> getting the itch to move on.

A bigger ratio between C1 and C2 would make it easier to reject a single
input spike. But I can understand the attraction of seeing what the
laternatives can do.

Erik

-- 
Universities are places of knowledge. The freshmen each bring a little
in with them, and the seniors take none away, so knowledge accumulates.

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