Great! Many thanks for the reply, Bob. Could I ask a few more questions to try to get a better understanding of what's going on?
1. Does the SDR software skip the 9854's FTW of 0x4000(+ more zeroes) that would be used if the DDS chip was set to 50 MHz? I'm trying to explain to myself why I don't see the beautiful spur-free spectrum that I see when the DDS is tuned to *exactly* 50 MHz (receiver tuned to 50.011 plus pocket change) with Spur Reduction OFF, compared to when Spur Reduction is ON and I tune through the point where the FTW ought to be 0x4000... . 2. If clock leaks are worse at submultiples of 200 MHz, how does this manifest itself? Again, my panadapter looks fantastic when the divisor of 200 MHz is exactly 4. It's only as I tune off this point that it quickly degrades. In other words, at a divisor of exactly 4, clock leakage (per the SDR1K's panadapter display, at least) wouldn't seem to be an issue. 3. Regarding the 9958 - how does the 10-bit DAC of the 9958 affect spur performance compared to the 9854's 12-bit DAC? Per my understanding, even if one has chosen FTW's that "zero-out" the phase-remainder (so that there is no phase "quantization error"), there is still an amplitude error introduced by the phase-to-amplitude converter's sin/cos conversion of the phase to an amplitude that's 10 or 12 bits wide (depending upon DAC resolution), and even with a completely linear DAC and no clock leakage, I'd think this should result in spurs, too. Are these spurs significant? (I'm just trying to gauge the drawbacks of the 9958 - it's faster, but the DAC resolution is less). Thanks for any insights you can provide! - Jeff, WA6AHL -----Original Message----- From: Robert McGwier [mailto:[EMAIL PROTECTED] Sent: Wednesday, December 07, 2005 1:17 PM To: [EMAIL PROTECTED] Cc: 'Jeff Anderson'; flexradio@flex-radio.biz Subject: Re: [Flexradio] Interesting behavior when connected to a dummy load Gents: Please bring up the message I put out a couple of days ago. I ended it with the AD9854 has leakage of clock and some modest DAC nonlinearities that cause some spurs. Jeff has discovered the worst of them. 200 MHz (clock)/ 50 MHz (frequency of interest) is 4. The clock leaks on all submulitples of 200 MHz but the ones at 50 MHz are the worst. This is an internal fault of the AD9854 and its worst feature. With a slightly more complex spur reduction routine, that uses both sides of the 1/f hump at zero, we could help considerably and never see these things. You would still see the impact of reciprocal mixing but its impact would be greatly diminished. As I said before, Analog Devices has learned a lot and we are learning along with them. Bob
