The number of DMA data bursts and the size of each DMA data burst is decided dynamically by the host and device.
Yes.
The number and size of each burst has nothing to do with the sector size or block size of the device.
a) In practice this is incorrect.
For example, the last UDma bus trace I sampled happened to contain data of the pattern x 0000 0001 0002 ... which made it easy for me to see every actual crc I review happened to land within a word or two of a 2 KiB block boundary.
b) In theory this may be incorrect.
Specifically I've never yet heard a straight answer on how often the host or device should force a crc to defend the strength of the crc. I mis/remember 48-bit Ata and 32-bit Atapi both let the host ask to copy xFFFF lba's. At 2 KiB/lba that's just short of 128 MiB.
Does our t13.org crc which Wintel practice proves reliable at 64 KiB/cdb remain reliable at 128 MiB/burst?
I don't know.
Do you?
For example the transfer of 4 sectors of data (2048 bytes) might result in 103 DMA data bursts or 37 DMA data bursts or only one DMA data burst.
Yes.
If there is more than one DMA data burst the size of each burst could appear to be randomly decided by the host and device.
Could be. Myself I have never yet seen a trace that didn't have some apparent structure.
For whatever reason this has never been clearly stated by the DMA descriptions in ATA-x or ATA/ATAPI-x.
Agreed, t13.org never has published a straight story on how we count bytes. Not in PIO, not in SWDMA, not in MWDMA, and not in UDMA. Read/ write mostly works without anyone trying hard to count bytes accurately.
Pat LaVarre
