Oi. Anybody know what we meant by the English we published as:
--- orphaned at page 236 of 244 in d1532v2r4.pdf
E.5.3.2 CRC calculation and comparison
...
The longer the Ultra DMA burst size the greater the likelihood of an undetected error. Burst lengths longer than 131,072 bytes will increase the probability of undetected errors above that of the ATA/ATAPI-6 and earlier standards.
---
? What throws me is the postscript:
above that of the ATA/ATAPI-6 and earlier standards.
UDMA is in ATA/PI 6, yes? So what did we change in ATA/PI 7 to make UDMA less reliable? Just kicked up the burst rate? Was the crc strength limit of the ATA/PI 6 burst rates actually infinite?? Really???
I'm no expert on that document, but so far as I know the document places no limit on bytes per burst. I agree that's silly. crc strength is not infinite.
In ATA/ATAPI-7 see the last paragraph in clause E.5.3.2 - there is a "recommendation" that a burst should not be more than 131072 bytes.
Thank you! I had not found that, before now. Now I have found the above.
This message is from the T13 list server. Rumour tells me some hosts and devices implement just enough of the standard to work with some of the others, leaving out fully arbitrary support for termination at any time.
Maybe, but that would be very dangerous and I've never seen this in shipping devices.
In shipping hosts I've seen less than arbitrary termination handling only secondhand.
Secondhand. Not thirdhand, but admittedly not firsthand either.
My walkaway was that for interoperability my devices should terminate no more often than necessary, within the 128 KiB recommendation. I fail to meet this recommendation when bridging to 8-bit SCSI in particular.
Also I fear trouble when my hosts have to terminate at 4 KiB or worse for lack of more buffer, but I haven't actually seen that break yet.
For example, I don't often see a UDma trace pause repeatedly inside a block. And "what ain't tested don't work so good".
A device has no control over when a host might pause or terminate and the host may do that due to PCI bus activity that the device can not predict or control.
Yes.
To actually interoperate reliably the device and the host have to meet and exceed the theoretical spec we print. A device or host that does not actually support arbitrary pause or terminate does not meet spec.
Good luck finding hardware you can afford that will tell you if a particular device or host commonly does or does not miscompare in response to arbitrary pause and terminate.
Pat LaVarre
