> On June 17, 2013, 2:58 p.m., Andreas Hansson wrote: > > src/mem/SimpleDRAM.py, line 121 > > <http://reviews.gem5.org/r/1927/diff/1/?file=36224#file36224line121> > > > > I would rather see an interface width in bits (e.g. 64) and a burst > > length in "beats", so 8 in this case.
yes, that would be better. So, I'll add an interface width in bits and burst length in beats for each DRAM. I'll try to do it on June 30th (can't before that). > On June 17, 2013, 2:58 p.m., Andreas Hansson wrote: > > src/mem/SimpleDRAM.py, line 185 > > <http://reviews.gem5.org/r/1927/diff/1/?file=36224#file36224line185> > > > > Would it not make more sense to express the row buffer as a MemorySize > > param and thus in kb/bytes? yes, that's what I suggested in my email too. the reason that I did not do that is that I did not want to divert from your design significantly. I knew you guys will raise a lot of questions, so I tried to stick with the original code as much as I can, so I get fewer questions :). Now that you want it, sure I'll do it. > On June 17, 2013, 2:58 p.m., Andreas Hansson wrote: > > src/mem/SimpleDRAM.py, line 198 > > <http://reviews.gem5.org/r/1927/diff/1/?file=36224#file36224line198> > > > > I think if we do indeed do this change we should have a clock and do as > > Nilay suggests. This also opens up the complication that the WideIO config > > is SDR and the others are DDR so that has to be captured somehow. it is good to have clocks involved here, but I think it adds unnecessary complexity. > On June 17, 2013, 2:58 p.m., Andreas Hansson wrote: > > src/mem/simple_dram.cc, line 101 > > <http://reviews.gem5.org/r/1927/diff/1/?file=36226#file36226line101> > > > > I think this patch should include the support for splitting cache lines > > into multiple DRAM bursts. At least the two patches should be committed as > > one. Some notes here. The current DRAM controller models transaction queues, but it does not model a DRAM command queue. As far as I know, when a dram controller gets a request that should be split into multiple bursts, it keeps it as a single transaction, but the number of associated dram commands increases linearly with the number of bursts. Since, we don't have a command queue, I could not think of a simple way to do this (by simple I mean something that can be done in an hour). I am not a DRAM guru, and I was told this is how dram controller takes care of multiple burst requests. So, if you have any suggestions/comments here, I would love to know. - Amin ----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/1927/#review4441 ----------------------------------------------------------- On June 17, 2013, 4:13 a.m., Amin Farmahini wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/1927/ > ----------------------------------------------------------- > > (Updated June 17, 2013, 4:13 a.m.) > > > Review request for Default. > > > Repository: gem5 > > > Description > ------- > > This patch gets rid of bytesPerCacheLine parameter and makes the DRAM > configuration separate from cache line size. > Instead of bytesPerCacheLine, I define a parameter for DRAM called > burst_length. The burst_length parameter shows the size of a DRAM burst in > bytes and is 64 bytes for all current DRAM configurations. Note, this > parameter is coupled with tBURST. > Also, I replace lines_per_rowbuffer with bursts_per_rowbuffer, because > lines_per_rowbuffer is defined based on 64-byte cache lines which makes the > code unportable. > > Next patch could be to add support for requests larger than burst length. > > > Diffs > ----- > > src/mem/SimpleDRAM.py UNKNOWN > src/mem/simple_dram.hh UNKNOWN > src/mem/simple_dram.cc UNKNOWN > > Diff: http://reviews.gem5.org/r/1927/diff/ > > > Testing > ------- > > None > > > Thanks, > > Amin Farmahini > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
