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src/mem/SimpleDRAM.py <http://reviews.gem5.org/r/1927/#comment4174> Hi Nilay, You cannot compute this from params as the cache line size is determined in the C++ code. - Andreas Hansson On June 17, 2013, 4:13 a.m., Amin Farmahini wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/1927/ > ----------------------------------------------------------- > > (Updated June 17, 2013, 4:13 a.m.) > > > Review request for Default. > > > Repository: gem5 > > > Description > ------- > > This patch gets rid of bytesPerCacheLine parameter and makes the DRAM > configuration separate from cache line size. > Instead of bytesPerCacheLine, I define a parameter for DRAM called > burst_length. The burst_length parameter shows the size of a DRAM burst in > bytes and is 64 bytes for all current DRAM configurations. Note, this > parameter is coupled with tBURST. > Also, I replace lines_per_rowbuffer with bursts_per_rowbuffer, because > lines_per_rowbuffer is defined based on 64-byte cache lines which makes the > code unportable. > > Next patch could be to add support for requests larger than burst length. > > > Diffs > ----- > > src/mem/SimpleDRAM.py UNKNOWN > src/mem/simple_dram.hh UNKNOWN > src/mem/simple_dram.cc UNKNOWN > > Diff: http://reviews.gem5.org/r/1927/diff/ > > > Testing > ------- > > None > > > Thanks, > > Amin Farmahini > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
