On Sunday, 29 October 2017 12:03:35 UTC+4, SWISSNIXIE - Jonathan F. wrote: > > Nick, note that the 3.4W are "absolute maximum" which usually means the > part is going to die if you go over that.
I did note that - I state "up to 3.4W" - good engineering practice means you should still consider that... Also, the PLCC package you use is about 300mm^2. at 1.2W, that's about 4mW/mm^2 The HV5523 QFN package is only 45mm^2, so at peak power that's 77mW/mm^2, i.e. nearly 20 times the power density of your chip. Even if it was only 1.2W, that would still be 27mW/mm^2, i.e. 7 times the power density you are seeing with the HV5122. The "plated-through hole underneath" technique works OK if done sensibly, but you still have to ensure that there is sufficient copper flooding to dissipate the heat. Nick -- You received this message because you are subscribed to the Google Groups "neonixie-l" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. To post to this group, send an email to [email protected]. To view this discussion on the web, visit https://groups.google.com/d/msgid/neonixie-l/d1476c6a-ebe0-468a-bd48-8e2d2fd9aa83%40googlegroups.com. For more options, visit https://groups.google.com/d/optout.
