Having a thermal pad does wonders. A PLCC package, in socket or not, has to dissipate heat mainly through its body, because heat transfers to other parts of the board only via legs. In practice, almost all power is dissipated through plastic. Thermal pad allows to mostly transfer the heat to other metal bodies (copper area). However, the 3,4W is alot of heat and looking at conditions for such continous dissipation, the whole concept of a small PCB area is lost - 3x4" 4-layer board ( I assume that 3 layers are connected to the pad). In reality I doubt dissipating more than 1W on such piece would be allowable with thermal vias to other side and half a square inch of plane on the other side. However, judging from the datasheet, you can safely drive 3 CD-47 (with their 25mA cathode current) and still be way under 1W.
Back to the spacing topic: Mains voltage routing norms are way more strict than that. Mains isolation is calculated using alot higher voltage, I recall a number about 1200Vpp. Some norms I found require that the mains voltage should be at absolute minimum spaced 1,5mm from other traces and 2mm is recommended for basic design (and 4mm between primary and secondary). The norms I've taken for calculating minimum spacing were included in online clearance calculators and they assume the given voltage is peak AC or DC. I really think that it would be unwise to use this chip to drive voltages close to 200V due to possiblity of arcing between pads. In nixie clock that would result in just two digits glowing at once, but that would still count as a failure. I'd like to see any report from testing this chip (pad width vs leaking current). W dniu niedziela, 29 października 2017 15:05:03 UTC+1 użytkownik Nick napisał: > > On Sunday, 29 October 2017 12:03:35 UTC+4, SWISSNIXIE - Jonathan F. wrote: >> >> Nick, note that the 3.4W are "absolute maximum" which usually means the >> part is going to die if you go over that. > > > I did note that - I state "up to 3.4W" - good engineering practice means > you should still consider that... > > Also, the PLCC package you use is about 300mm^2. at 1.2W, that's about > 4mW/mm^2 > > The HV5523 QFN package is only 49mm^2, so at peak power that's 70mW/mm^2, > i.e. nearly 18 times the power density of your chip. > > Even if it was only 1.2W, that would still be 25mW/mm^2, i.e. 6 times the > power density you are seeing with the HV5122. > > The "plated-through hole underneath" technique works OK if done sensibly, > but you still have to ensure that there is sufficient copper flooding to > dissipate the heat. > > Nick > > EDITED: Changed the QFN size from 45 to 49mm^2 > > > -- You received this message because you are subscribed to the Google Groups "neonixie-l" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. To post to this group, send an email to [email protected]. To view this discussion on the web, visit https://groups.google.com/d/msgid/neonixie-l/a29365b1-d0a9-4488-8d06-0d94dd1aaf13%40googlegroups.com. For more options, visit https://groups.google.com/d/optout.
